include/asm-powerpc/pgtable.h

   1 #ifndef _ASM_POWERPC_PGTABLE_H
   2 #define _ASM_POWERPC_PGTABLE_H
   3 #ifdef __KERNEL__
   4
   5 #ifndef CONFIG_PPC64
   6 #include <asm-ppc/pgtable.h>
   7 #else
   8
   9 /*
  10  * This file contains the functions and defines necessary to modify and use
  11  * the ppc64 hashed page table.
  12  */
  13
  14 #ifndef __ASSEMBLY__
  15 #include <linux/config.h>
  16 #include <linux/stddef.h>
  17 #include <asm/processor.h>              /* For TASK_SIZE */
  18 #include <asm/mmu.h>
  19 #include <asm/page.h>
  20 #include <asm/tlbflush.h>
  21 struct mm_struct;
  22 #endif /* __ASSEMBLY__ */
  23
  24 #ifdef CONFIG_PPC_64K_PAGES
  25 #include <asm/pgtable-64k.h>
  26 #else
  27 #include <asm/pgtable-4k.h>
  28 #endif
  29
  30 #define FIRST_USER_ADDRESS      0
  31
  32 /*
  33  * Size of EA range mapped by our pagetables.
  34  */
  35 #define PGTABLE_EADDR_SIZE (PTE_INDEX_SIZE + PMD_INDEX_SIZE + \
  36                             PUD_INDEX_SIZE + PGD_INDEX_SIZE + PAGE_SHIFT)
  37 #define PGTABLE_RANGE (1UL << PGTABLE_EADDR_SIZE)
  38
  39 #if TASK_SIZE_USER64 > PGTABLE_RANGE
  40 #error TASK_SIZE_USER64 exceeds pagetable range
  41 #endif
  42
  43 #if TASK_SIZE_USER64 > (1UL << (USER_ESID_BITS + SID_SHIFT))
  44 #error TASK_SIZE_USER64 exceeds user VSID range
  45 #endif
  46
  47 /*
  48  * Define the address range of the vmalloc VM area.
  49  */
  50 #define VMALLOC_START (0xD000000000000000ul)
  51 #define VMALLOC_SIZE  (0x80000000000UL)
  52 #define VMALLOC_END   (VMALLOC_START + VMALLOC_SIZE)
  53
  54 /*
  55  * Define the address range of the imalloc VM area.
  56  */
  57 #define PHBS_IO_BASE    VMALLOC_END
  58 #define IMALLOC_BASE    (PHBS_IO_BASE + 0x80000000ul)   /* Reserve 2 gigs for PHBs */
  59 #define IMALLOC_END     (VMALLOC_START + PGTABLE_RANGE)
  60
  61 /*
  62  * Region IDs
  63  */
  64 #define REGION_SHIFT            60UL
  65 #define REGION_MASK             (0xfUL << REGION_SHIFT)
  66 #define REGION_ID(ea)           (((unsigned long)(ea)) >> REGION_SHIFT)
  67
  68 #define VMALLOC_REGION_ID       (REGION_ID(VMALLOC_START))
  69 #define KERNEL_REGION_ID        (REGION_ID(PAGE_OFFSET))
  70 #define USER_REGION_ID          (0UL)
  71
  72 /*
  73  * Common bits in a linux-style PTE.  These match the bits in the
  74  * (hardware-defined) PowerPC PTE as closely as possible. Additional
  75  * bits may be defined in pgtable-*.h
  76  */
  77 #define _PAGE_PRESENT   0x0001 /* software: pte contains a translation */
  78 #define _PAGE_USER      0x0002 /* matches one of the PP bits */
  79 #define _PAGE_FILE      0x0002 /* (!present only) software: pte holds file offset */
  80 #define _PAGE_EXEC      0x0004 /* No execute on POWER4 and newer (we invert) */
  81 #define _PAGE_GUARDED   0x0008
  82 #define _PAGE_COHERENT  0x0010 /* M: enforce memory coherence (SMP systems) */
  83 #define _PAGE_NO_CACHE  0x0020 /* I: cache inhibit */
  84 #define _PAGE_WRITETHRU 0x0040 /* W: cache write-through */
  85 #define _PAGE_DIRTY     0x0080 /* C: page changed */
  86 #define _PAGE_ACCESSED  0x0100 /* R: page referenced */
  87 #define _PAGE_RW        0x0200 /* software: user write access allowed */
  88 #define _PAGE_HASHPTE   0x0400 /* software: pte has an associated HPTE */
  89 #define _PAGE_BUSY      0x0800 /* software: PTE & hash are busy */
  90
  91 #define _PAGE_BASE      (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_COHERENT)
  92
  93 #define _PAGE_WRENABLE  (_PAGE_RW | _PAGE_DIRTY)
  94
  95 /* __pgprot defined in asm-powerpc/page.h */
  96 #define PAGE_NONE       __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED)
  97
  98 #define PAGE_SHARED     __pgprot(_PAGE_BASE | _PAGE_RW | _PAGE_USER)
  99 #define PAGE_SHARED_X   __pgprot(_PAGE_BASE | _PAGE_RW | _PAGE_USER | _PAGE_EXEC)
 100 #define PAGE_COPY       __pgprot(_PAGE_BASE | _PAGE_USER)
 101 #define PAGE_COPY_X     __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
 102 #define PAGE_READONLY   __pgprot(_PAGE_BASE | _PAGE_USER)
 103 #define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
 104 #define PAGE_KERNEL     __pgprot(_PAGE_BASE | _PAGE_WRENABLE)
 105 #define PAGE_KERNEL_CI  __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \
 106                                _PAGE_WRENABLE | _PAGE_NO_CACHE | _PAGE_GUARDED)
 107 #define PAGE_KERNEL_EXEC __pgprot(_PAGE_BASE | _PAGE_WRENABLE | _PAGE_EXEC)
 108
 109 #define PAGE_AGP        __pgprot(_PAGE_BASE | _PAGE_WRENABLE | _PAGE_NO_CACHE)
 110 #define HAVE_PAGE_AGP
 111
 112 /* PTEIDX nibble */
 113 #define _PTEIDX_SECONDARY       0x8
 114 #define _PTEIDX_GROUP_IX        0x7
 115
 116
 117 /*
 118  * POWER4 and newer have per page execute protection, older chips can only
 119  * do this on a segment (256MB) basis.
 120  *
 121  * Also, write permissions imply read permissions.
 122  * This is the closest we can get..
 123  *
 124  * Note due to the way vm flags are laid out, the bits are XWR
 125  */
 126 #define __P000  PAGE_NONE
 127 #define __P001  PAGE_READONLY
 128 #define __P010  PAGE_COPY
 129 #define __P011  PAGE_COPY
 130 #define __P100  PAGE_READONLY_X
 131 #define __P101  PAGE_READONLY_X
 132 #define __P110  PAGE_COPY_X
 133 #define __P111  PAGE_COPY_X
 134
 135 #define __S000  PAGE_NONE
 136 #define __S001  PAGE_READONLY
 137 #define __S010  PAGE_SHARED
 138 #define __S011  PAGE_SHARED
 139 #define __S100  PAGE_READONLY_X
 140 #define __S101  PAGE_READONLY_X
 141 #define __S110  PAGE_SHARED_X
 142 #define __S111  PAGE_SHARED_X
 143
 144 #ifndef __ASSEMBLY__
 145
 146 /*
 147  * ZERO_PAGE is a global shared page that is always zero: used
 148  * for zero-mapped memory areas etc..
 149  */
 150 extern unsigned long empty_zero_page[PAGE_SIZE/sizeof(unsigned long)];
 151 #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
 152 #endif /* __ASSEMBLY__ */
 153
 154 #ifdef CONFIG_HUGETLB_PAGE
 155
 156 #define HAVE_ARCH_UNMAPPED_AREA
 157 #define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
 158
 159 #endif
 160
 161 #ifndef __ASSEMBLY__
 162
 163 /*
 164  * Conversion functions: convert a page and protection to a page entry,
 165  * and a page entry and page directory to the page they refer to.
 166  *
 167  * mk_pte takes a (struct page *) as input
 168  */
 169 #define mk_pte(page, pgprot)    pfn_pte(page_to_pfn(page), (pgprot))
 170
 171 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot)
 172 {
 173         pte_t pte;
 174
 175
 176         pte_val(pte) = (pfn << PTE_RPN_SHIFT) | pgprot_val(pgprot);
 177         return pte;
 178 }
 179
 180 #define pte_modify(_pte, newprot) \
 181   (__pte((pte_val(_pte) & _PAGE_CHG_MASK) | pgprot_val(newprot)))
 182
 183 #define pte_none(pte)           ((pte_val(pte) & ~_PAGE_HPTEFLAGS) == 0)
 184 #define pte_present(pte)        (pte_val(pte) & _PAGE_PRESENT)
 185
 186 /* pte_clear moved to later in this file */
 187
 188 #define pte_pfn(x)              ((unsigned long)((pte_val(x)>>PTE_RPN_SHIFT)))
 189 #define pte_page(x)             pfn_to_page(pte_pfn(x))
 190
 191 #define pmd_set(pmdp, pmdval)   (pmd_val(*(pmdp)) = (pmdval))
 192 #define pmd_none(pmd)           (!pmd_val(pmd))
 193 #define pmd_bad(pmd)            (pmd_val(pmd) == 0)
 194 #define pmd_present(pmd)        (pmd_val(pmd) != 0)
 195 #define pmd_clear(pmdp)         (pmd_val(*(pmdp)) = 0)
 196 #define pmd_page_kernel(pmd)    (pmd_val(pmd) & ~PMD_MASKED_BITS)
 197 #define pmd_page(pmd)           virt_to_page(pmd_page_kernel(pmd))
 198
 199 #define pud_set(pudp, pudval)   (pud_val(*(pudp)) = (pudval))
 200 #define pud_none(pud)           (!pud_val(pud))
 201 #define pud_bad(pud)            ((pud_val(pud)) == 0)
 202 #define pud_present(pud)        (pud_val(pud) != 0)
 203 #define pud_clear(pudp)         (pud_val(*(pudp)) = 0)
 204 #define pud_page(pud)           (pud_val(pud) & ~PUD_MASKED_BITS)
 205
 206 #define pgd_set(pgdp, pudp)     ({pgd_val(*(pgdp)) = (unsigned long)(pudp);})
 207
 208 /*
 209  * Find an entry in a page-table-directory.  We combine the address region
 210  * (the high order N bits) and the pgd portion of the address.
 211  */
 212 /* to avoid overflow in free_pgtables we don't use PTRS_PER_PGD here */
 213 #define pgd_index(address) (((address) >> (PGDIR_SHIFT)) & 0x1ff)
 214
 215 #define pgd_offset(mm, address)  ((mm)->pgd + pgd_index(address))
 216
 217 #define pmd_offset(pudp,addr) \
 218   (((pmd_t *) pud_page(*(pudp))) + (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1)))
 219
 220 #define pte_offset_kernel(dir,addr) \
 221   (((pte_t *) pmd_page_kernel(*(dir))) + (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)))
 222
 223 #define pte_offset_map(dir,addr)        pte_offset_kernel((dir), (addr))
 224 #define pte_offset_map_nested(dir,addr) pte_offset_kernel((dir), (addr))
 225 #define pte_unmap(pte)                  do { } while(0)
 226 #define pte_unmap_nested(pte)           do { } while(0)
 227
 228 /* to find an entry in a kernel page-table-directory */
 229 /* This now only contains the vmalloc pages */
 230 #define pgd_offset_k(address) pgd_offset(&init_mm, address)
 231
 232 /*
 233  * The following only work if pte_present() is true.
 234  * Undefined behaviour if not..
 235  */
 236 static inline int pte_read(pte_t pte)  { return pte_val(pte) & _PAGE_USER;}
 237 static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_RW;}
 238 static inline int pte_exec(pte_t pte)  { return pte_val(pte) & _PAGE_EXEC;}
 239 static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY;}
 240 static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED;}
 241 static inline int pte_file(pte_t pte) { return pte_val(pte) & _PAGE_FILE;}
 242
 243 static inline void pte_uncache(pte_t pte) { pte_val(pte) |= _PAGE_NO_CACHE; }
 244 static inline void pte_cache(pte_t pte)   { pte_val(pte) &= ~_PAGE_NO_CACHE; }
 245
 246 static inline pte_t pte_rdprotect(pte_t pte) {
 247         pte_val(pte) &= ~_PAGE_USER; return pte; }
 248 static inline pte_t pte_exprotect(pte_t pte) {
 249         pte_val(pte) &= ~_PAGE_EXEC; return pte; }
 250 static inline pte_t pte_wrprotect(pte_t pte) {
 251         pte_val(pte) &= ~(_PAGE_RW); return pte; }
 252 static inline pte_t pte_mkclean(pte_t pte) {
 253         pte_val(pte) &= ~(_PAGE_DIRTY); return pte; }
 254 static inline pte_t pte_mkold(pte_t pte) {
 255         pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
 256 static inline pte_t pte_mkread(pte_t pte) {
 257         pte_val(pte) |= _PAGE_USER; return pte; }
 258 static inline pte_t pte_mkexec(pte_t pte) {
 259         pte_val(pte) |= _PAGE_USER | _PAGE_EXEC; return pte; }
 260 static inline pte_t pte_mkwrite(pte_t pte) {
 261         pte_val(pte) |= _PAGE_RW; return pte; }
 262 static inline pte_t pte_mkdirty(pte_t pte) {
 263         pte_val(pte) |= _PAGE_DIRTY; return pte; }
 264 static inline pte_t pte_mkyoung(pte_t pte) {
 265         pte_val(pte) |= _PAGE_ACCESSED; return pte; }
 266 static inline pte_t pte_mkhuge(pte_t pte) {
 267         return pte; }
 268
 269 /* Atomic PTE updates */
 270 static inline unsigned long pte_update(pte_t *p, unsigned long clr)
 271 {
 272         unsigned long old, tmp;
 273
 274         __asm__ __volatile__(
 275         "1:     ldarx   %0,0,%3         # pte_update\n\
 276         andi.   %1,%0,%6\n\
 277         bne-    1b \n\
 278         andc    %1,%0,%4 \n\
 279         stdcx.  %1,0,%3 \n\
 280         bne-    1b"
 281         : "=&r" (old), "=&r" (tmp), "=m" (*p)
 282         : "r" (p), "r" (clr), "m" (*p), "i" (_PAGE_BUSY)
 283         : "cc" );
 284         return old;
 285 }
 286
 287 /* PTE updating functions, this function puts the PTE in the
 288  * batch, doesn't actually triggers the hash flush immediately,
 289  * you need to call flush_tlb_pending() to do that.
 290  * Pass -1 for "normal" size (4K or 64K)
 291  */
 292 extern void hpte_update(struct mm_struct *mm, unsigned long addr,
 293                         pte_t *ptep, unsigned long pte, int huge);
 294
 295 static inline int __ptep_test_and_clear_young(struct mm_struct *mm,
 296                                               unsigned long addr, pte_t *ptep)
 297 {
 298         unsigned long old;
 299
 300         if ((pte_val(*ptep) & (_PAGE_ACCESSED | _PAGE_HASHPTE)) == 0)
 301                 return 0;
 302         old = pte_update(ptep, _PAGE_ACCESSED);
 303         if (old & _PAGE_HASHPTE) {
 304                 hpte_update(mm, addr, ptep, old, 0);
 305                 flush_tlb_pending();
 306         }
 307         return (old & _PAGE_ACCESSED) != 0;
 308 }
 309 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
 310 #define ptep_test_and_clear_young(__vma, __addr, __ptep)                   \
 311 ({                                                                         \
 312         int __r;                                                           \
 313         __r = __ptep_test_and_clear_young((__vma)->vm_mm, __addr, __ptep); \
 314         __r;                                                               \
 315 })
 316
 317 /*
 318  * On RW/DIRTY bit transitions we can avoid flushing the hpte. For the
 319  * moment we always flush but we need to fix hpte_update and test if the
 320  * optimisation is worth it.
 321  */
 322 static inline int __ptep_test_and_clear_dirty(struct mm_struct *mm,
 323                                               unsigned long addr, pte_t *ptep)
 324 {
 325         unsigned long old;
 326
 327         if ((pte_val(*ptep) & _PAGE_DIRTY) == 0)
 328                 return 0;
 329         old = pte_update(ptep, _PAGE_DIRTY);
 330         if (old & _PAGE_HASHPTE)
 331                 hpte_update(mm, addr, ptep, old, 0);
 332         return (old & _PAGE_DIRTY) != 0;
 333 }
 334 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_DIRTY
 335 #define ptep_test_and_clear_dirty(__vma, __addr, __ptep)                   \
 336 ({                                                                         \
 337         int __r;                                                           \
 338         __r = __ptep_test_and_clear_dirty((__vma)->vm_mm, __addr, __ptep); \
 339         __r;                                                               \
 340 })
 341
 342 #define __HAVE_ARCH_PTEP_SET_WRPROTECT
 343 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
 344                                       pte_t *ptep)
 345 {
 346         unsigned long old;
 347
 348         if ((pte_val(*ptep) & _PAGE_RW) == 0)
 349                 return;
 350         old = pte_update(ptep, _PAGE_RW);
 351         if (old & _PAGE_HASHPTE)
 352                 hpte_update(mm, addr, ptep, old, 0);
 353 }
 354
 355 /*
 356  * We currently remove entries from the hashtable regardless of whether
 357  * the entry was young or dirty. The generic routines only flush if the
 358  * entry was young or dirty which is not good enough.
 359  *
 360  * We should be more intelligent about this but for the moment we override
 361  * these functions and force a tlb flush unconditionally
 362  */
 363 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH
 364 #define ptep_clear_flush_young(__vma, __address, __ptep)                \
 365 ({                                                                      \
 366         int __young = __ptep_test_and_clear_young((__vma)->vm_mm, __address, \
 367                                                   __ptep);              \
 368         __young;                                                        \
 369 })
 370
 371 #define __HAVE_ARCH_PTEP_CLEAR_DIRTY_FLUSH
 372 #define ptep_clear_flush_dirty(__vma, __address, __ptep)                \
 373 ({                                                                      \
 374         int __dirty = __ptep_test_and_clear_dirty((__vma)->vm_mm, __address, \
 375                                                   __ptep);              \
 376         flush_tlb_page(__vma, __address);                               \
 377         __dirty;                                                        \
 378 })
 379
 380 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
 381 static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
 382                                        unsigned long addr, pte_t *ptep)
 383 {
 384         unsigned long old = pte_update(ptep, ~0UL);
 385
 386         if (old & _PAGE_HASHPTE)
 387                 hpte_update(mm, addr, ptep, old, 0);
 388         return __pte(old);
 389 }
 390
 391 static inline void pte_clear(struct mm_struct *mm, unsigned long addr,
 392                              pte_t * ptep)
 393 {
 394         unsigned long old = pte_update(ptep, ~0UL);
 395
 396         if (old & _PAGE_HASHPTE)
 397                 hpte_update(mm, addr, ptep, old, 0);
 398 }
 399
 400 /*
 401  * set_pte stores a linux PTE into the linux page table.
 402  */
 403 static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
 404                               pte_t *ptep, pte_t pte)
 405 {
 406         if (pte_present(*ptep)) {
 407                 pte_clear(mm, addr, ptep);
 408                 flush_tlb_pending();
 409         }
 410         pte = __pte(pte_val(pte) & ~_PAGE_HPTEFLAGS);
 411
 412 #ifdef CONFIG_PPC_64K_PAGES
 413         if (mmu_virtual_psize != MMU_PAGE_64K)
 414                 pte = __pte(pte_val(pte) | _PAGE_COMBO);
 415 #endif /* CONFIG_PPC_64K_PAGES */
 416
 417         *ptep = pte;
 418 }
 419
 420 /* Set the dirty and/or accessed bits atomically in a linux PTE, this
 421  * function doesn't need to flush the hash entry
 422  */
 423 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
 424 static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry, int dirty)
 425 {
 426         unsigned long bits = pte_val(entry) &
 427                 (_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_RW | _PAGE_EXEC);
 428         unsigned long old, tmp;
 429
 430         __asm__ __volatile__(
 431         "1:     ldarx   %0,0,%4\n\
 432                 andi.   %1,%0,%6\n\
 433                 bne-    1b \n\
 434                 or      %0,%3,%0\n\
 435                 stdcx.  %0,0,%4\n\
 436                 bne-    1b"
 437         :"=&r" (old), "=&r" (tmp), "=m" (*ptep)
 438         :"r" (bits), "r" (ptep), "m" (*ptep), "i" (_PAGE_BUSY)
 439         :"cc");
 440 }
 441 #define  ptep_set_access_flags(__vma, __address, __ptep, __entry, __dirty) \
 442         do {                                                               \
 443                 __ptep_set_access_flags(__ptep, __entry, __dirty);         \
 444                 flush_tlb_page_nohash(__vma, __address);                   \
 445         } while(0)
 446
 447 /*
 448  * Macro to mark a page protection value as "uncacheable".
 449  */
 450 #define pgprot_noncached(prot)  (__pgprot(pgprot_val(prot) | _PAGE_NO_CACHE | _PAGE_GUARDED))
 451
 452 struct file;
 453 extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
 454                                      unsigned long size, pgprot_t vma_prot);
 455 #define __HAVE_PHYS_MEM_ACCESS_PROT
 456
 457 #define __HAVE_ARCH_PTE_SAME
 458 #define pte_same(A,B)   (((pte_val(A) ^ pte_val(B)) & ~_PAGE_HPTEFLAGS) == 0)
 459
 460 #define pte_ERROR(e) \
 461         printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
 462 #define pmd_ERROR(e) \
 463         printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e))
 464 #define pgd_ERROR(e) \
 465         printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
 466
 467 extern pgd_t swapper_pg_dir[];
 468
 469 extern void paging_init(void);
 470
 471 #ifdef CONFIG_HUGETLB_PAGE
 472 #define hugetlb_free_pgd_range(tlb, addr, end, floor, ceiling) \
 473         free_pgd_range(tlb, addr, end, floor, ceiling)
 474 #endif
 475
 476 /*
 477  * This gets called at the end of handling a page fault, when
 478  * the kernel has put a new PTE into the page table for the process.
 479  * We use it to put a corresponding HPTE into the hash table
 480  * ahead of time, instead of waiting for the inevitable extra
 481  * hash-table miss exception.
 482  */
 483 struct vm_area_struct;
 484 extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t);
 485
 486 /* Encode and de-code a swap entry */
 487 #define __swp_type(entry)       (((entry).val >> 1) & 0x3f)
 488 #define __swp_offset(entry)     ((entry).val >> 8)
 489 #define __swp_entry(type, offset) ((swp_entry_t){((type)<< 1)|((offset)<<8)})
 490 #define __pte_to_swp_entry(pte) ((swp_entry_t){pte_val(pte) >> PTE_RPN_SHIFT})
 491 #define __swp_entry_to_pte(x)   ((pte_t) { (x).val << PTE_RPN_SHIFT })
 492 #define pte_to_pgoff(pte)       (pte_val(pte) >> PTE_RPN_SHIFT)
 493 #define pgoff_to_pte(off)       ((pte_t) {((off) << PTE_RPN_SHIFT)|_PAGE_FILE})
 494 #define PTE_FILE_MAX_BITS       (BITS_PER_LONG - PTE_RPN_SHIFT)
 495
 496 /*
 497  * kern_addr_valid is intended to indicate whether an address is a valid
 498  * kernel address.  Most 32-bit archs define it as always true (like this)
 499  * but most 64-bit archs actually perform a test.  What should we do here?
 500  * The only use is in fs/ncpfs/dir.c
 501  */
 502 #define kern_addr_valid(addr)   (1)
 503
 504 #define io_remap_pfn_range(vma, vaddr, pfn, size, prot)         \
 505                 remap_pfn_range(vma, vaddr, pfn, size, prot)
 506
 507 void pgtable_cache_init(void);
 508
 509 /*
 510  * find_linux_pte returns the address of a linux pte for a given
 511  * effective address and directory.  If not found, it returns zero.
 512  */static inline pte_t *find_linux_pte(pgd_t *pgdir, unsigned long ea)
 513 {
 514         pgd_t *pg;
 515         pud_t *pu;
 516         pmd_t *pm;
 517         pte_t *pt = NULL;
 518
 519         pg = pgdir + pgd_index(ea);
 520         if (!pgd_none(*pg)) {
 521                 pu = pud_offset(pg, ea);
 522                 if (!pud_none(*pu)) {
 523                         pm = pmd_offset(pu, ea);
 524                         if (pmd_present(*pm))
 525                                 pt = pte_offset_kernel(pm, ea);
 526                 }
 527         }
 528         return pt;
 529 }
 530
 531 #include <asm-generic/pgtable.h>
 532
 533 #endif /* __ASSEMBLY__ */
 534
 535 #endif /* CONFIG_PPC64 */
 536 #endif /* __KERNEL__ */
 537 #endif /* _ASM_POWERPC_PGTABLE_H */