?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
radeonfb: Add support for Radeon Xpress 200M (RS485)
[usb.git] / drivers / video / aty / radeon_base.c
blob47ca62fe7c3e6edef11f6869fe44599f6609a74e
1 /*
2 * drivers/video/aty/radeon_base.c
3 *
4 * framebuffer driver for ATI Radeon chipset video boards
5 *
6 * Copyright 2003 Ben. Herrenschmidt <benh@kernel.crashing.org>
7 * Copyright 2000 Ani Joshi <ajoshi@kernel.crashing.org>
8 *
9 * i2c bits from Luca Tettamanti <kronos@kronoz.cjb.net>
10 *
11 * Special thanks to ATI DevRel team for their hardware donations.
12 *
13 * ...Insert GPL boilerplate here...
14 *
15 * Significant portions of this driver apdated from XFree86 Radeon
16 * driver which has the following copyright notice:
17 *
18 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
19 * VA Linux Systems Inc., Fremont, California.
20 *
21 * All Rights Reserved.
22 *
23 * Permission is hereby granted, free of charge, to any person obtaining
24 * a copy of this software and associated documentation files (the
25 * "Software"), to deal in the Software without restriction, including
26 * without limitation on the rights to use, copy, modify, merge,
27 * publish, distribute, sublicense, and/or sell copies of the Software,
28 * and to permit persons to whom the Software is furnished to do so,
29 * subject to the following conditions:
30 *
31 * The above copyright notice and this permission notice (including the
32 * next paragraph) shall be included in all copies or substantial
33 * portions of the Software.
34 *
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
37 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
39 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
41 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
42 * DEALINGS IN THE SOFTWARE.
43 *
44 * XFree86 driver authors:
45 *
46 * Kevin E. Martin <martin@xfree86.org>
47 * Rickard E. Faith <faith@valinux.com>
48 * Alan Hourihane <alanh@fairlite.demon.co.uk>
49 *
50 */
51
52
53 #define RADEON_VERSION "0.2.0"
54
55 #include <linux/module.h>
56 #include <linux/moduleparam.h>
57 #include <linux/kernel.h>
58 #include <linux/errno.h>
59 #include <linux/string.h>
60 #include <linux/mm.h>
61 #include <linux/slab.h>
62 #include <linux/delay.h>
63 #include <linux/time.h>
64 #include <linux/fb.h>
65 #include <linux/ioport.h>
66 #include <linux/init.h>
67 #include <linux/pci.h>
68 #include <linux/vmalloc.h>
69 #include <linux/device.h>
70
71 #include <asm/io.h>
72 #include <asm/uaccess.h>
73
74 #ifdef CONFIG_PPC_OF
75
76 #include <asm/pci-bridge.h>
77 #include "../macmodes.h"
78
79 #ifdef CONFIG_BOOTX_TEXT
80 #include <asm/btext.h>
81 #endif
82
83 #endif /* CONFIG_PPC_OF */
84
85 #ifdef CONFIG_MTRR
86 #include <asm/mtrr.h>
87 #endif
88
89 #include <video/radeon.h>
90 #include <linux/radeonfb.h>
91
92 #include "../edid.h" // MOVE THAT TO include/video
93 #include "ati_ids.h"
94 #include "radeonfb.h"
95
96 #define MAX_MAPPED_VRAM (2048*2048*4)
97 #define MIN_MAPPED_VRAM (1024*768*1)
98
99 #define CHIP_DEF(id, family, flags) \
100 { PCI_VENDOR_ID_ATI, id, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (flags) | (CHIP_FAMILY_##family) }
101
102 static struct pci_device_id radeonfb_pci_table[] = {
103 /* Radeon Xpress 200m */
104 CHIP_DEF(PCI_CHIP_RS480_5955, RS480, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
105 /* Mobility M6 */
106 CHIP_DEF(PCI_CHIP_RADEON_LY, RV100, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
107 CHIP_DEF(PCI_CHIP_RADEON_LZ, RV100, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
108 /* Radeon VE/7000 */
109 CHIP_DEF(PCI_CHIP_RV100_QY, RV100, CHIP_HAS_CRTC2),
110 CHIP_DEF(PCI_CHIP_RV100_QZ, RV100, CHIP_HAS_CRTC2),
111 CHIP_DEF(PCI_CHIP_RN50, RV100, CHIP_HAS_CRTC2),
112 /* Radeon IGP320M (U1) */
113 CHIP_DEF(PCI_CHIP_RS100_4336, RS100, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
114 /* Radeon IGP320 (A3) */
115 CHIP_DEF(PCI_CHIP_RS100_4136, RS100, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
116 /* IGP330M/340M/350M (U2) */
117 CHIP_DEF(PCI_CHIP_RS200_4337, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
118 /* IGP330/340/350 (A4) */
119 CHIP_DEF(PCI_CHIP_RS200_4137, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
120 /* Mobility 7000 IGP */
121 CHIP_DEF(PCI_CHIP_RS250_4437, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
122 /* 7000 IGP (A4+) */
123 CHIP_DEF(PCI_CHIP_RS250_4237, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
124 /* 8500 AIW */
125 CHIP_DEF(PCI_CHIP_R200_BB, R200, CHIP_HAS_CRTC2),
126 CHIP_DEF(PCI_CHIP_R200_BC, R200, CHIP_HAS_CRTC2),
127 /* 8700/8800 */
128 CHIP_DEF(PCI_CHIP_R200_QH, R200, CHIP_HAS_CRTC2),
129 /* 8500 */
130 CHIP_DEF(PCI_CHIP_R200_QL, R200, CHIP_HAS_CRTC2),
131 /* 9100 */
132 CHIP_DEF(PCI_CHIP_R200_QM, R200, CHIP_HAS_CRTC2),
133 /* Mobility M7 */
134 CHIP_DEF(PCI_CHIP_RADEON_LW, RV200, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
135 CHIP_DEF(PCI_CHIP_RADEON_LX, RV200, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
136 /* 7500 */
137 CHIP_DEF(PCI_CHIP_RV200_QW, RV200, CHIP_HAS_CRTC2),
138 CHIP_DEF(PCI_CHIP_RV200_QX, RV200, CHIP_HAS_CRTC2),
139 /* Mobility M9 */
140 CHIP_DEF(PCI_CHIP_RV250_Ld, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
141 CHIP_DEF(PCI_CHIP_RV250_Le, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
142 CHIP_DEF(PCI_CHIP_RV250_Lf, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
143 CHIP_DEF(PCI_CHIP_RV250_Lg, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
144 /* 9000/Pro */
145 CHIP_DEF(PCI_CHIP_RV250_If, RV250, CHIP_HAS_CRTC2),
146 CHIP_DEF(PCI_CHIP_RV250_Ig, RV250, CHIP_HAS_CRTC2),
147 /* Mobility 9100 IGP (U3) */
148 CHIP_DEF(PCI_CHIP_RS300_5835, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
149 CHIP_DEF(PCI_CHIP_RS350_7835, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
150 /* 9100 IGP (A5) */
151 CHIP_DEF(PCI_CHIP_RS300_5834, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
152 CHIP_DEF(PCI_CHIP_RS350_7834, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
153 /* Mobility 9200 (M9+) */
154 CHIP_DEF(PCI_CHIP_RV280_5C61, RV280, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
155 CHIP_DEF(PCI_CHIP_RV280_5C63, RV280, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
156 /*Mobility Xpress 200 */
157 CHIP_DEF(PCI_CHIP_RS485_5975, R300, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
158 /* 9200 */
159 CHIP_DEF(PCI_CHIP_RV280_5960, RV280, CHIP_HAS_CRTC2),
160 CHIP_DEF(PCI_CHIP_RV280_5961, RV280, CHIP_HAS_CRTC2),
161 CHIP_DEF(PCI_CHIP_RV280_5962, RV280, CHIP_HAS_CRTC2),
162 CHIP_DEF(PCI_CHIP_RV280_5964, RV280, CHIP_HAS_CRTC2),
163 /* 9500 */
164 CHIP_DEF(PCI_CHIP_R300_AD, R300, CHIP_HAS_CRTC2),
165 CHIP_DEF(PCI_CHIP_R300_AE, R300, CHIP_HAS_CRTC2),
166 /* 9600TX / FireGL Z1 */
167 CHIP_DEF(PCI_CHIP_R300_AF, R300, CHIP_HAS_CRTC2),
168 CHIP_DEF(PCI_CHIP_R300_AG, R300, CHIP_HAS_CRTC2),
169 /* 9700/9500/Pro/FireGL X1 */
170 CHIP_DEF(PCI_CHIP_R300_ND, R300, CHIP_HAS_CRTC2),
171 CHIP_DEF(PCI_CHIP_R300_NE, R300, CHIP_HAS_CRTC2),
172 CHIP_DEF(PCI_CHIP_R300_NF, R300, CHIP_HAS_CRTC2),
173 CHIP_DEF(PCI_CHIP_R300_NG, R300, CHIP_HAS_CRTC2),
174 /* Mobility M10/M11 */
175 CHIP_DEF(PCI_CHIP_RV350_NP, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
176 CHIP_DEF(PCI_CHIP_RV350_NQ, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
177 CHIP_DEF(PCI_CHIP_RV350_NR, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
178 CHIP_DEF(PCI_CHIP_RV350_NS, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
179 CHIP_DEF(PCI_CHIP_RV350_NT, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
180 CHIP_DEF(PCI_CHIP_RV350_NV, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
181 /* 9600/FireGL T2 */
182 CHIP_DEF(PCI_CHIP_RV350_AP, RV350, CHIP_HAS_CRTC2),
183 CHIP_DEF(PCI_CHIP_RV350_AQ, RV350, CHIP_HAS_CRTC2),
184 CHIP_DEF(PCI_CHIP_RV360_AR, RV350, CHIP_HAS_CRTC2),
185 CHIP_DEF(PCI_CHIP_RV350_AS, RV350, CHIP_HAS_CRTC2),
186 CHIP_DEF(PCI_CHIP_RV350_AT, RV350, CHIP_HAS_CRTC2),
187 CHIP_DEF(PCI_CHIP_RV350_AV, RV350, CHIP_HAS_CRTC2),
188 /* 9800/Pro/FileGL X2 */
189 CHIP_DEF(PCI_CHIP_R350_AH, R350, CHIP_HAS_CRTC2),
190 CHIP_DEF(PCI_CHIP_R350_AI, R350, CHIP_HAS_CRTC2),
191 CHIP_DEF(PCI_CHIP_R350_AJ, R350, CHIP_HAS_CRTC2),
192 CHIP_DEF(PCI_CHIP_R350_AK, R350, CHIP_HAS_CRTC2),
193 CHIP_DEF(PCI_CHIP_R350_NH, R350, CHIP_HAS_CRTC2),
194 CHIP_DEF(PCI_CHIP_R350_NI, R350, CHIP_HAS_CRTC2),
195 CHIP_DEF(PCI_CHIP_R360_NJ, R350, CHIP_HAS_CRTC2),
196 CHIP_DEF(PCI_CHIP_R350_NK, R350, CHIP_HAS_CRTC2),
197 /* Newer stuff */
198 CHIP_DEF(PCI_CHIP_RV380_3E50, RV380, CHIP_HAS_CRTC2),
199 CHIP_DEF(PCI_CHIP_RV380_3E54, RV380, CHIP_HAS_CRTC2),
200 CHIP_DEF(PCI_CHIP_RV380_3150, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
201 CHIP_DEF(PCI_CHIP_RV380_3154, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
202 CHIP_DEF(PCI_CHIP_RV370_5B60, RV380, CHIP_HAS_CRTC2),
203 CHIP_DEF(PCI_CHIP_RV370_5B62, RV380, CHIP_HAS_CRTC2),
204 CHIP_DEF(PCI_CHIP_RV370_5B64, RV380, CHIP_HAS_CRTC2),
205 CHIP_DEF(PCI_CHIP_RV370_5B65, RV380, CHIP_HAS_CRTC2),
206 CHIP_DEF(PCI_CHIP_RV370_5460, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
207 CHIP_DEF(PCI_CHIP_RV370_5464, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
208 CHIP_DEF(PCI_CHIP_R420_JH, R420, CHIP_HAS_CRTC2),
209 CHIP_DEF(PCI_CHIP_R420_JI, R420, CHIP_HAS_CRTC2),
210 CHIP_DEF(PCI_CHIP_R420_JJ, R420, CHIP_HAS_CRTC2),
211 CHIP_DEF(PCI_CHIP_R420_JK, R420, CHIP_HAS_CRTC2),
212 CHIP_DEF(PCI_CHIP_R420_JL, R420, CHIP_HAS_CRTC2),
213 CHIP_DEF(PCI_CHIP_R420_JM, R420, CHIP_HAS_CRTC2),
214 CHIP_DEF(PCI_CHIP_R420_JN, R420, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
215 CHIP_DEF(PCI_CHIP_R420_JP, R420, CHIP_HAS_CRTC2),
216 CHIP_DEF(PCI_CHIP_R423_UH, R420, CHIP_HAS_CRTC2),
217 CHIP_DEF(PCI_CHIP_R423_UI, R420, CHIP_HAS_CRTC2),
218 CHIP_DEF(PCI_CHIP_R423_UJ, R420, CHIP_HAS_CRTC2),
219 CHIP_DEF(PCI_CHIP_R423_UK, R420, CHIP_HAS_CRTC2),
220 CHIP_DEF(PCI_CHIP_R423_UQ, R420, CHIP_HAS_CRTC2),
221 CHIP_DEF(PCI_CHIP_R423_UR, R420, CHIP_HAS_CRTC2),
222 CHIP_DEF(PCI_CHIP_R423_UT, R420, CHIP_HAS_CRTC2),
223 CHIP_DEF(PCI_CHIP_R423_5D57, R420, CHIP_HAS_CRTC2),
224 /* Original Radeon/7200 */
225 CHIP_DEF(PCI_CHIP_RADEON_QD, RADEON, 0),
226 CHIP_DEF(PCI_CHIP_RADEON_QE, RADEON, 0),
227 CHIP_DEF(PCI_CHIP_RADEON_QF, RADEON, 0),
228 CHIP_DEF(PCI_CHIP_RADEON_QG, RADEON, 0),
229 { 0, }
230 };
231 MODULE_DEVICE_TABLE(pci, radeonfb_pci_table);
232
233
234 typedef struct {
235 u16 reg;
236 u32 val;
237 } reg_val;
238
239
240 /* these common regs are cleared before mode setting so they do not
241 * interfere with anything
242 */
243 static reg_val common_regs[] = {
244 { OVR_CLR, 0 },
245 { OVR_WID_LEFT_RIGHT, 0 },
246 { OVR_WID_TOP_BOTTOM, 0 },
247 { OV0_SCALE_CNTL, 0 },
248 { SUBPIC_CNTL, 0 },
249 { VIPH_CONTROL, 0 },
250 { I2C_CNTL_1, 0 },
251 { GEN_INT_CNTL, 0 },
252 { CAP0_TRIG_CNTL, 0 },
253 { CAP1_TRIG_CNTL, 0 },
254 };
255
256 /*
257 * globals
258 */
259
260 static char *mode_option;
261 static char *monitor_layout;
262 static int noaccel = 0;
263 static int default_dynclk = -2;
264 static int nomodeset = 0;
265 static int ignore_edid = 0;
266 static int mirror = 0;
267 static int panel_yres = 0;
268 static int force_dfp = 0;
269 static int force_measure_pll = 0;
270 #ifdef CONFIG_MTRR
271 static int nomtrr = 0;
272 #endif
273 static int force_sleep;
274 static int ignore_devlist;
275 #ifdef CONFIG_PMAC_BACKLIGHT
276 static int backlight = 1;
277 #else
278 static int backlight = 0;
279 #endif
280
281 /*
282 * prototypes
283 */
284
285 static void radeon_unmap_ROM(struct radeonfb_info *rinfo, struct pci_dev *dev)
286 {
287 if (!rinfo->bios_seg)
288 return;
289 pci_unmap_rom(dev, rinfo->bios_seg);
290 }
291
292 static int __devinit radeon_map_ROM(struct radeonfb_info *rinfo, struct pci_dev *dev)
293 {
294 void __iomem *rom;
295 u16 dptr;
296 u8 rom_type;
297 size_t rom_size;
298
299 /* If this is a primary card, there is a shadow copy of the
300 * ROM somewhere in the first meg. We will just ignore the copy
301 * and use the ROM directly.
302 */
303
304 /* Fix from ATI for problem with Radeon hardware not leaving ROM enabled */
305 unsigned int temp;
306 temp = INREG(MPP_TB_CONFIG);
307 temp &= 0x00ffffffu;
308 temp |= 0x04 << 24;
309 OUTREG(MPP_TB_CONFIG, temp);
310 temp = INREG(MPP_TB_CONFIG);
311
312 rom = pci_map_rom(dev, &rom_size);
313 if (!rom) {
314 printk(KERN_ERR "radeonfb (%s): ROM failed to map\n",
315 pci_name(rinfo->pdev));
316 return -ENOMEM;
317 }
318
319 rinfo->bios_seg = rom;
320
321 /* Very simple test to make sure it appeared */
322 if (BIOS_IN16(0) != 0xaa55) {
323 printk(KERN_DEBUG "radeonfb (%s): Invalid ROM signature %x "
324 "should be 0xaa55\n",
325 pci_name(rinfo->pdev), BIOS_IN16(0));
326 goto failed;
327 }
328 /* Look for the PCI data to check the ROM type */
329 dptr = BIOS_IN16(0x18);
330
331 /* Check the PCI data signature. If it's wrong, we still assume a normal x86 ROM
332 * for now, until I've verified this works everywhere. The goal here is more
333 * to phase out Open Firmware images.
334 *
335 * Currently, we only look at the first PCI data, we could iteratre and deal with
336 * them all, and we should use fb_bios_start relative to start of image and not
337 * relative start of ROM, but so far, I never found a dual-image ATI card
338 *
339 * typedef struct {
340 * u32 signature; + 0x00
341 * u16 vendor; + 0x04
342 * u16 device; + 0x06
343 * u16 reserved_1; + 0x08
344 * u16 dlen; + 0x0a
345 * u8 drevision; + 0x0c
346 * u8 class_hi; + 0x0d
347 * u16 class_lo; + 0x0e
348 * u16 ilen; + 0x10
349 * u16 irevision; + 0x12
350 * u8 type; + 0x14
351 * u8 indicator; + 0x15
352 * u16 reserved_2; + 0x16
353 * } pci_data_t;
354 */
355 if (BIOS_IN32(dptr) != (('R' << 24) | ('I' << 16) | ('C' << 8) | 'P')) {
356 printk(KERN_WARNING "radeonfb (%s): PCI DATA signature in ROM"
357 "incorrect: %08x\n", pci_name(rinfo->pdev), BIOS_IN32(dptr));
358 goto anyway;
359 }
360 rom_type = BIOS_IN8(dptr + 0x14);
361 switch(rom_type) {
362 case 0:
363 printk(KERN_INFO "radeonfb: Found Intel x86 BIOS ROM Image\n");
364 break;
365 case 1:
366 printk(KERN_INFO "radeonfb: Found Open Firmware ROM Image\n");
367 goto failed;
368 case 2:
369 printk(KERN_INFO "radeonfb: Found HP PA-RISC ROM Image\n");
370 goto failed;
371 default:
372 printk(KERN_INFO "radeonfb: Found unknown type %d ROM Image\n", rom_type);
373 goto failed;
374 }
375 anyway:
376 /* Locate the flat panel infos, do some sanity checking !!! */
377 rinfo->fp_bios_start = BIOS_IN16(0x48);
378 return 0;
379
380 failed:
381 rinfo->bios_seg = NULL;
382 radeon_unmap_ROM(rinfo, dev);
383 return -ENXIO;
384 }
385
386 #ifdef CONFIG_X86
387 static int __devinit radeon_find_mem_vbios(struct radeonfb_info *rinfo)
388 {
389 /* I simplified this code as we used to miss the signatures in
390 * a lot of case. It's now closer to XFree, we just don't check
391 * for signatures at all... Something better will have to be done
392 * if we end up having conflicts
393 */
394 u32 segstart;
395 void __iomem *rom_base = NULL;
396
397 for(segstart=0x000c0000; segstart<0x000f0000; segstart+=0x00001000) {
398 rom_base = ioremap(segstart, 0x10000);
399 if (rom_base == NULL)
400 return -ENOMEM;
401 if (readb(rom_base) == 0x55 && readb(rom_base + 1) == 0xaa)
402 break;
403 iounmap(rom_base);
404 rom_base = NULL;
405 }
406 if (rom_base == NULL)
407 return -ENXIO;
408
409 /* Locate the flat panel infos, do some sanity checking !!! */
410 rinfo->bios_seg = rom_base;
411 rinfo->fp_bios_start = BIOS_IN16(0x48);
412
413 return 0;
414 }
415 #endif
416
417 #if defined(CONFIG_PPC_OF) || defined(CONFIG_SPARC)
418 /*
419 * Read XTAL (ref clock), SCLK and MCLK from Open Firmware device
420 * tree. Hopefully, ATI OF driver is kind enough to fill these
421 */
422 static int __devinit radeon_read_xtal_OF (struct radeonfb_info *rinfo)
423 {
424 struct device_node *dp = rinfo->of_node;
425 const u32 *val;
426
427 if (dp == NULL)
428 return -ENODEV;
429 val = of_get_property(dp, "ATY,RefCLK", NULL);
430 if (!val || !*val) {
431 printk(KERN_WARNING "radeonfb: No ATY,RefCLK property !\n");
432 return -EINVAL;
433 }
434
435 rinfo->pll.ref_clk = (*val) / 10;
436
437 val = of_get_property(dp, "ATY,SCLK", NULL);
438 if (val && *val)
439 rinfo->pll.sclk = (*val) / 10;
440
441 val = of_get_property(dp, "ATY,MCLK", NULL);
442 if (val && *val)
443 rinfo->pll.mclk = (*val) / 10;
444
445 return 0;
446 }
447 #endif /* CONFIG_PPC_OF || CONFIG_SPARC */
448
449 /*
450 * Read PLL infos from chip registers
451 */
452 static int __devinit radeon_probe_pll_params(struct radeonfb_info *rinfo)
453 {
454 unsigned char ppll_div_sel;
455 unsigned Ns, Nm, M;
456 unsigned sclk, mclk, tmp, ref_div;
457 int hTotal, vTotal, num, denom, m, n;
458 unsigned long long hz, vclk;
459 long xtal;
460 struct timeval start_tv, stop_tv;
461 long total_secs, total_usecs;
462 int i;
463
464 /* Ugh, we cut interrupts, bad bad bad, but we want some precision
465 * here, so... --BenH
466 */
467
468 /* Flush PCI buffers ? */
469 tmp = INREG16(DEVICE_ID);
470
471 local_irq_disable();
472
473 for(i=0; i<1000000; i++)
474 if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) == 0)
475 break;
476
477 do_gettimeofday(&start_tv);
478
479 for(i=0; i<1000000; i++)
480 if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) != 0)
481 break;
482
483 for(i=0; i<1000000; i++)
484 if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) == 0)
485 break;
486
487 do_gettimeofday(&stop_tv);
488
489 local_irq_enable();
490
491 total_secs = stop_tv.tv_sec - start_tv.tv_sec;
492 if (total_secs > 10)
493 return -1;
494 total_usecs = stop_tv.tv_usec - start_tv.tv_usec;
495 total_usecs += total_secs * 1000000;
496 if (total_usecs < 0)
497 total_usecs = -total_usecs;
498 hz = 1000000/total_usecs;
499
500 hTotal = ((INREG(CRTC_H_TOTAL_DISP) & 0x1ff) + 1) * 8;
501 vTotal = ((INREG(CRTC_V_TOTAL_DISP) & 0x3ff) + 1);
502 vclk = (long long)hTotal * (long long)vTotal * hz;
503
504 switch((INPLL(PPLL_REF_DIV) & 0x30000) >> 16) {
505 case 0:
506 default:
507 num = 1;
508 denom = 1;
509 break;
510 case 1:
511 n = ((INPLL(M_SPLL_REF_FB_DIV) >> 16) & 0xff);
512 m = (INPLL(M_SPLL_REF_FB_DIV) & 0xff);
513 num = 2*n;
514 denom = 2*m;
515 break;
516 case 2:
517 n = ((INPLL(M_SPLL_REF_FB_DIV) >> 8) & 0xff);
518 m = (INPLL(M_SPLL_REF_FB_DIV) & 0xff);
519 num = 2*n;
520 denom = 2*m;
521 break;
522 }
523
524 ppll_div_sel = INREG8(CLOCK_CNTL_INDEX + 1) & 0x3;
525 radeon_pll_errata_after_index(rinfo);
526
527 n = (INPLL(PPLL_DIV_0 + ppll_div_sel) & 0x7ff);
528 m = (INPLL(PPLL_REF_DIV) & 0x3ff);
529
530 num *= n;
531 denom *= m;
532
533 switch ((INPLL(PPLL_DIV_0 + ppll_div_sel) >> 16) & 0x7) {
534 case 1:
535 denom *= 2;
536 break;
537 case 2:
538 denom *= 4;
539 break;
540 case 3:
541 denom *= 8;
542 break;
543 case 4:
544 denom *= 3;
545 break;
546 case 6:
547 denom *= 6;
548 break;
549 case 7:
550 denom *= 12;
551 break;
552 }
553
554 vclk *= denom;
555 do_div(vclk, 1000 * num);
556 xtal = vclk;
557
558 if ((xtal > 26900) && (xtal < 27100))
559 xtal = 2700;
560 else if ((xtal > 14200) && (xtal < 14400))
561 xtal = 1432;
562 else if ((xtal > 29400) && (xtal < 29600))
563 xtal = 2950;
564 else {
565 printk(KERN_WARNING "xtal calculation failed: %ld\n", xtal);
566 return -1;
567 }
568
569 tmp = INPLL(M_SPLL_REF_FB_DIV);
570 ref_div = INPLL(PPLL_REF_DIV) & 0x3ff;
571
572 Ns = (tmp & 0xff0000) >> 16;
573 Nm = (tmp & 0xff00) >> 8;
574 M = (tmp & 0xff);
575 sclk = round_div((2 * Ns * xtal), (2 * M));
576 mclk = round_div((2 * Nm * xtal), (2 * M));
577
578 /* we're done, hopefully these are sane values */
579 rinfo->pll.ref_clk = xtal;
580 rinfo->pll.ref_div = ref_div;
581 rinfo->pll.sclk = sclk;
582 rinfo->pll.mclk = mclk;
583
584 return 0;
585 }
586
587 /*
588 * Retrieve PLL infos by different means (BIOS, Open Firmware, register probing...)
589 */
590 static void __devinit radeon_get_pllinfo(struct radeonfb_info *rinfo)
591 {
592 /*
593 * In the case nothing works, these are defaults; they are mostly
594 * incomplete, however. It does provide ppll_max and _min values
595 * even for most other methods, however.
596 */
597 switch (rinfo->chipset) {
598 case PCI_DEVICE_ID_ATI_RADEON_QW:
599 case PCI_DEVICE_ID_ATI_RADEON_QX:
600 rinfo->pll.ppll_max = 35000;
601 rinfo->pll.ppll_min = 12000;
602 rinfo->pll.mclk = 23000;
603 rinfo->pll.sclk = 23000;
604 rinfo->pll.ref_clk = 2700;
605 break;
606 case PCI_DEVICE_ID_ATI_RADEON_QL:
607 case PCI_DEVICE_ID_ATI_RADEON_QN:
608 case PCI_DEVICE_ID_ATI_RADEON_QO:
609 case PCI_DEVICE_ID_ATI_RADEON_Ql:
610 case PCI_DEVICE_ID_ATI_RADEON_BB:
611 rinfo->pll.ppll_max = 35000;
612 rinfo->pll.ppll_min = 12000;
613 rinfo->pll.mclk = 27500;
614 rinfo->pll.sclk = 27500;
615 rinfo->pll.ref_clk = 2700;
616 break;
617 case PCI_DEVICE_ID_ATI_RADEON_Id:
618 case PCI_DEVICE_ID_ATI_RADEON_Ie:
619 case PCI_DEVICE_ID_ATI_RADEON_If:
620 case PCI_DEVICE_ID_ATI_RADEON_Ig:
621 rinfo->pll.ppll_max = 35000;
622 rinfo->pll.ppll_min = 12000;
623 rinfo->pll.mclk = 25000;
624 rinfo->pll.sclk = 25000;
625 rinfo->pll.ref_clk = 2700;
626 break;
627 case PCI_DEVICE_ID_ATI_RADEON_ND:
628 case PCI_DEVICE_ID_ATI_RADEON_NE:
629 case PCI_DEVICE_ID_ATI_RADEON_NF:
630 case PCI_DEVICE_ID_ATI_RADEON_NG:
631 rinfo->pll.ppll_max = 40000;
632 rinfo->pll.ppll_min = 20000;
633 rinfo->pll.mclk = 27000;
634 rinfo->pll.sclk = 27000;
635 rinfo->pll.ref_clk = 2700;
636 break;
637 case PCI_DEVICE_ID_ATI_RADEON_QD:
638 case PCI_DEVICE_ID_ATI_RADEON_QE:
639 case PCI_DEVICE_ID_ATI_RADEON_QF:
640 case PCI_DEVICE_ID_ATI_RADEON_QG:
641 default:
642 rinfo->pll.ppll_max = 35000;
643 rinfo->pll.ppll_min = 12000;
644 rinfo->pll.mclk = 16600;
645 rinfo->pll.sclk = 16600;
646 rinfo->pll.ref_clk = 2700;
647 break;
648 }
649 rinfo->pll.ref_div = INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK;
650
651
652 #if defined(CONFIG_PPC_OF) || defined(CONFIG_SPARC)
653 /*
654 * Retrieve PLL infos from Open Firmware first
655 */
656 if (!force_measure_pll && radeon_read_xtal_OF(rinfo) == 0) {
657 printk(KERN_INFO "radeonfb: Retrieved PLL infos from Open Firmware\n");
658 goto found;
659 }
660 #endif /* CONFIG_PPC_OF || CONFIG_SPARC */
661
662 /*
663 * Check out if we have an X86 which gave us some PLL informations
664 * and if yes, retrieve them
665 */
666 if (!force_measure_pll && rinfo->bios_seg) {
667 u16 pll_info_block = BIOS_IN16(rinfo->fp_bios_start + 0x30);
668
669 rinfo->pll.sclk = BIOS_IN16(pll_info_block + 0x08);
670 rinfo->pll.mclk = BIOS_IN16(pll_info_block + 0x0a);
671 rinfo->pll.ref_clk = BIOS_IN16(pll_info_block + 0x0e);
672 rinfo->pll.ref_div = BIOS_IN16(pll_info_block + 0x10);
673 rinfo->pll.ppll_min = BIOS_IN32(pll_info_block + 0x12);
674 rinfo->pll.ppll_max = BIOS_IN32(pll_info_block + 0x16);
675
676 printk(KERN_INFO "radeonfb: Retrieved PLL infos from BIOS\n");
677 goto found;
678 }
679
680 /*
681 * We didn't get PLL parameters from either OF or BIOS, we try to
682 * probe them
683 */
684 if (radeon_probe_pll_params(rinfo) == 0) {
685 printk(KERN_INFO "radeonfb: Retrieved PLL infos from registers\n");
686 goto found;
687 }
688
689 /*
690 * Fall back to already-set defaults...
691 */
692 printk(KERN_INFO "radeonfb: Used default PLL infos\n");
693
694 found:
695 /*
696 * Some methods fail to retrieve SCLK and MCLK values, we apply default
697 * settings in this case (200Mhz). If that really happne often, we could
698 * fetch from registers instead...
699 */
700 if (rinfo->pll.mclk == 0)
701 rinfo->pll.mclk = 20000;
702 if (rinfo->pll.sclk == 0)
703 rinfo->pll.sclk = 20000;
704
705 printk("radeonfb: Reference=%d.%02d MHz (RefDiv=%d) Memory=%d.%02d Mhz, System=%d.%02d MHz\n",
706 rinfo->pll.ref_clk / 100, rinfo->pll.ref_clk % 100,
707 rinfo->pll.ref_div,
708 rinfo->pll.mclk / 100, rinfo->pll.mclk % 100,
709 rinfo->pll.sclk / 100, rinfo->pll.sclk % 100);
710 printk("radeonfb: PLL min %d max %d\n", rinfo->pll.ppll_min, rinfo->pll.ppll_max);
711 }
712
713 static int radeonfb_check_var (struct fb_var_screeninfo *var, struct fb_info *info)
714 {
715 struct radeonfb_info *rinfo = info->par;
716 struct fb_var_screeninfo v;
717 int nom, den;
718 unsigned int pitch;
719
720 if (radeon_match_mode(rinfo, &v, var))
721 return -EINVAL;
722
723 switch (v.bits_per_pixel) {
724 case 0 ... 8:
725 v.bits_per_pixel = 8;
726 break;
727 case 9 ... 16:
728 v.bits_per_pixel = 16;
729 break;
730 case 17 ... 24:
731 #if 0 /* Doesn't seem to work */
732 v.bits_per_pixel = 24;
733 break;
734 #endif
735 return -EINVAL;
736 case 25 ... 32:
737 v.bits_per_pixel = 32;
738 break;
739 default:
740 return -EINVAL;
741 }
742
743 switch (var_to_depth(&v)) {
744 case 8:
745 nom = den = 1;
746 v.red.offset = v.green.offset = v.blue.offset = 0;
747 v.red.length = v.green.length = v.blue.length = 8;
748 v.transp.offset = v.transp.length = 0;
749 break;
750 case 15:
751 nom = 2;
752 den = 1;
753 v.red.offset = 10;
754 v.green.offset = 5;
755 v.blue.offset = 0;
756 v.red.length = v.green.length = v.blue.length = 5;
757 v.transp.offset = v.transp.length = 0;
758 break;
759 case 16:
760 nom = 2;
761 den = 1;
762 v.red.offset = 11;
763 v.green.offset = 5;
764 v.blue.offset = 0;
765 v.red.length = 5;
766 v.green.length = 6;
767 v.blue.length = 5;
768 v.transp.offset = v.transp.length = 0;
769 break;
770 case 24:
771 nom = 4;
772 den = 1;
773 v.red.offset = 16;
774 v.green.offset = 8;
775 v.blue.offset = 0;
776 v.red.length = v.blue.length = v.green.length = 8;
777 v.transp.offset = v.transp.length = 0;
778 break;
779 case 32:
780 nom = 4;
781 den = 1;
782 v.red.offset = 16;
783 v.green.offset = 8;
784 v.blue.offset = 0;
785 v.red.length = v.blue.length = v.green.length = 8;
786 v.transp.offset = 24;
787 v.transp.length = 8;
788 break;
789 default:
790 printk ("radeonfb: mode %dx%dx%d rejected, color depth invalid\n",
791 var->xres, var->yres, var->bits_per_pixel);
792 return -EINVAL;
793 }
794
795 if (v.yres_virtual < v.yres)
796 v.yres_virtual = v.yres;
797 if (v.xres_virtual < v.xres)
798 v.xres_virtual = v.xres;
799
800
801 /* XXX I'm adjusting xres_virtual to the pitch, that may help XFree
802 * with some panels, though I don't quite like this solution
803 */
804 if (rinfo->info->flags & FBINFO_HWACCEL_DISABLED) {
805 v.xres_virtual = v.xres_virtual & ~7ul;
806 } else {
807 pitch = ((v.xres_virtual * ((v.bits_per_pixel + 1) / 8) + 0x3f)
808 & ~(0x3f)) >> 6;
809 v.xres_virtual = (pitch << 6) / ((v.bits_per_pixel + 1) / 8);
810 }
811
812 if (((v.xres_virtual * v.yres_virtual * nom) / den) > rinfo->mapped_vram)
813 return -EINVAL;
814
815 if (v.xres_virtual < v.xres)
816 v.xres = v.xres_virtual;
817
818 if (v.xoffset < 0)
819 v.xoffset = 0;
820 if (v.yoffset < 0)
821 v.yoffset = 0;
822
823 if (v.xoffset > v.xres_virtual - v.xres)
824 v.xoffset = v.xres_virtual - v.xres - 1;
825
826 if (v.yoffset > v.yres_virtual - v.yres)
827 v.yoffset = v.yres_virtual - v.yres - 1;
828
829 v.red.msb_right = v.green.msb_right = v.blue.msb_right =
830 v.transp.offset = v.transp.length =
831 v.transp.msb_right = 0;
832
833 memcpy(var, &v, sizeof(v));
834
835 return 0;
836 }
837
838
839 static int radeonfb_pan_display (struct fb_var_screeninfo *var,
840 struct fb_info *info)
841 {
842 struct radeonfb_info *rinfo = info->par;
843
844 if ((var->xoffset + var->xres > var->xres_virtual)
845 || (var->yoffset + var->yres > var->yres_virtual))
846 return -EINVAL;
847
848 if (rinfo->asleep)
849 return 0;
850
851 radeon_fifo_wait(2);
852 OUTREG(CRTC_OFFSET, ((var->yoffset * var->xres_virtual + var->xoffset)
853 * var->bits_per_pixel / 8) & ~7);
854 return 0;
855 }
856
857
858 static int radeonfb_ioctl (struct fb_info *info, unsigned int cmd,
859 unsigned long arg)
860 {
861 struct radeonfb_info *rinfo = info->par;
862 unsigned int tmp;
863 u32 value = 0;
864 int rc;
865
866 switch (cmd) {
867 /*
868 * TODO: set mirror accordingly for non-Mobility chipsets with 2 CRTC's
869 * and do something better using 2nd CRTC instead of just hackish
870 * routing to second output
871 */
872 case FBIO_RADEON_SET_MIRROR:
873 if (!rinfo->is_mobility)
874 return -EINVAL;
875
876 rc = get_user(value, (__u32 __user *)arg);
877
878 if (rc)
879 return rc;
880
881 radeon_fifo_wait(2);
882 if (value & 0x01) {
883 tmp = INREG(LVDS_GEN_CNTL);
884
885 tmp |= (LVDS_ON | LVDS_BLON);
886 } else {
887 tmp = INREG(LVDS_GEN_CNTL);
888
889 tmp &= ~(LVDS_ON | LVDS_BLON);
890 }
891
892 OUTREG(LVDS_GEN_CNTL, tmp);
893
894 if (value & 0x02) {
895 tmp = INREG(CRTC_EXT_CNTL);
896 tmp |= CRTC_CRT_ON;
897
898 mirror = 1;
899 } else {
900 tmp = INREG(CRTC_EXT_CNTL);
901 tmp &= ~CRTC_CRT_ON;
902
903 mirror = 0;
904 }
905
906 OUTREG(CRTC_EXT_CNTL, tmp);
907
908 return 0;
909 case FBIO_RADEON_GET_MIRROR:
910 if (!rinfo->is_mobility)
911 return -EINVAL;
912
913 tmp = INREG(LVDS_GEN_CNTL);
914 if ((LVDS_ON | LVDS_BLON) & tmp)
915 value |= 0x01;
916
917 tmp = INREG(CRTC_EXT_CNTL);
918 if (CRTC_CRT_ON & tmp)
919 value |= 0x02;
920
921 return put_user(value, (__u32 __user *)arg);
922 default:
923 return -EINVAL;
924 }
925
926 return -EINVAL;
927 }
928
929
930 int radeon_screen_blank(struct radeonfb_info *rinfo, int blank, int mode_switch)
931 {
932 u32 val;
933 u32 tmp_pix_clks;
934 int unblank = 0;
935
936 if (rinfo->lock_blank)
937 return 0;
938
939 radeon_engine_idle();
940
941 val = INREG(CRTC_EXT_CNTL);
942 val &= ~(CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS |
943 CRTC_VSYNC_DIS);
944 switch (blank) {
945 case FB_BLANK_VSYNC_SUSPEND:
946 val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS);
947 break;
948 case FB_BLANK_HSYNC_SUSPEND:
949 val |= (CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS);
950 break;
951 case FB_BLANK_POWERDOWN:
952 val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS |
953 CRTC_HSYNC_DIS);
954 break;
955 case FB_BLANK_NORMAL:
956 val |= CRTC_DISPLAY_DIS;
957 break;
958 case FB_BLANK_UNBLANK:
959 default:
960 unblank = 1;
961 }
962 OUTREG(CRTC_EXT_CNTL, val);
963
964
965 switch (rinfo->mon1_type) {
966 case MT_DFP:
967 if (unblank)
968 OUTREGP(FP_GEN_CNTL, (FP_FPON | FP_TMDS_EN),
969 ~(FP_FPON | FP_TMDS_EN));
970 else {
971 if (mode_switch || blank == FB_BLANK_NORMAL)
972 break;
973 OUTREGP(FP_GEN_CNTL, 0, ~(FP_FPON | FP_TMDS_EN));
974 }
975 break;
976 case MT_LCD:
977 del_timer_sync(&rinfo->lvds_timer);
978 val = INREG(LVDS_GEN_CNTL);
979 if (unblank) {
980 u32 target_val = (val & ~LVDS_DISPLAY_DIS) | LVDS_BLON | LVDS_ON
981 | LVDS_EN | (rinfo->init_state.lvds_gen_cntl
982 & (LVDS_DIGON | LVDS_BL_MOD_EN));
983 if ((val ^ target_val) == LVDS_DISPLAY_DIS)
984 OUTREG(LVDS_GEN_CNTL, target_val);
985 else if ((val ^ target_val) != 0) {
986 OUTREG(LVDS_GEN_CNTL, target_val
987 & ~(LVDS_ON | LVDS_BL_MOD_EN));
988 rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;
989 rinfo->init_state.lvds_gen_cntl |=
990 target_val & LVDS_STATE_MASK;
991 if (mode_switch) {
992 radeon_msleep(rinfo->panel_info.pwr_delay);
993 OUTREG(LVDS_GEN_CNTL, target_val);
994 }
995 else {
996 rinfo->pending_lvds_gen_cntl = target_val;
997 mod_timer(&rinfo->lvds_timer,
998 jiffies +
999 msecs_to_jiffies(rinfo->panel_info.pwr_delay));
1000 }
1001 }
1002 } else {
1003 val |= LVDS_DISPLAY_DIS;
1004 OUTREG(LVDS_GEN_CNTL, val);
1005
1006 /* We don't do a full switch-off on a simple mode switch */
1007 if (mode_switch || blank == FB_BLANK_NORMAL)
1008 break;
1009
1010 /* Asic bug, when turning off LVDS_ON, we have to make sure
1011 * RADEON_PIXCLK_LVDS_ALWAYS_ON bit is off
1012 */
1013 tmp_pix_clks = INPLL(PIXCLKS_CNTL);
1014 if (rinfo->is_mobility || rinfo->is_IGP)
1015 OUTPLLP(PIXCLKS_CNTL, 0, ~PIXCLK_LVDS_ALWAYS_ONb);
1016 val &= ~(LVDS_BL_MOD_EN);
1017 OUTREG(LVDS_GEN_CNTL, val);
1018 udelay(100);
1019 val &= ~(LVDS_ON | LVDS_EN);
1020 OUTREG(LVDS_GEN_CNTL, val);
1021 val &= ~LVDS_DIGON;
1022 rinfo->pending_lvds_gen_cntl = val;
1023 mod_timer(&rinfo->lvds_timer,
1024 jiffies +
1025 msecs_to_jiffies(rinfo->panel_info.pwr_delay));
1026 rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;
1027 rinfo->init_state.lvds_gen_cntl |= val & LVDS_STATE_MASK;
1028 if (rinfo->is_mobility || rinfo->is_IGP)
1029 OUTPLL(PIXCLKS_CNTL, tmp_pix_clks);
1030 }
1031 break;
1032 case MT_CRT:
1033 // todo: powerdown DAC
1034 default:
1035 break;
1036 }
1037
1038 return 0;
1039 }
1040
1041 static int radeonfb_blank (int blank, struct fb_info *info)
1042 {
1043 struct radeonfb_info *rinfo = info->par;
1044
1045 if (rinfo->asleep)
1046 return 0;
1047
1048 return radeon_screen_blank(rinfo, blank, 0);
1049 }
1050
1051 static int radeon_setcolreg (unsigned regno, unsigned red, unsigned green,
1052 unsigned blue, unsigned transp,
1053 struct radeonfb_info *rinfo)
1054 {
1055 u32 pindex;
1056 unsigned int i;
1057
1058
1059 if (regno > 255)
1060 return -EINVAL;
1061
1062 red >>= 8;
1063 green >>= 8;
1064 blue >>= 8;
1065 rinfo->palette[regno].red = red;
1066 rinfo->palette[regno].green = green;
1067 rinfo->palette[regno].blue = blue;
1068
1069 /* default */
1070 pindex = regno;
1071
1072 if (!rinfo->asleep) {
1073 radeon_fifo_wait(9);
1074
1075 if (rinfo->bpp == 16) {
1076 pindex = regno * 8;
1077
1078 if (rinfo->depth == 16 && regno > 63)
1079 return -EINVAL;
1080 if (rinfo->depth == 15 && regno > 31)
1081 return -EINVAL;
1082
1083 /* For 565, the green component is mixed one order
1084 * below
1085 */
1086 if (rinfo->depth == 16) {
1087 OUTREG(PALETTE_INDEX, pindex>>1);
1088 OUTREG(PALETTE_DATA,
1089 (rinfo->palette[regno>>1].red << 16) |
1090 (green << 8) |
1091 (rinfo->palette[regno>>1].blue));
1092 green = rinfo->palette[regno<<1].green;
1093 }
1094 }
1095
1096 if (rinfo->depth != 16 || regno < 32) {
1097 OUTREG(PALETTE_INDEX, pindex);
1098 OUTREG(PALETTE_DATA, (red << 16) |
1099 (green << 8) | blue);
1100 }
1101 }
1102 if (regno < 16) {
1103 u32 *pal = rinfo->info->pseudo_palette;
1104 switch (rinfo->depth) {
1105 case 15:
1106 pal[regno] = (regno << 10) | (regno << 5) | regno;
1107 break;
1108 case 16:
1109 pal[regno] = (regno << 11) | (regno << 5) | regno;
1110 break;
1111 case 24:
1112 pal[regno] = (regno << 16) | (regno << 8) | regno;
1113 break;
1114 case 32:
1115 i = (regno << 8) | regno;
1116 pal[regno] = (i << 16) | i;
1117 break;
1118 }
1119 }
1120 return 0;
1121 }
1122
1123 static int radeonfb_setcolreg (unsigned regno, unsigned red, unsigned green,
1124 unsigned blue, unsigned transp,
1125 struct fb_info *info)
1126 {
1127 struct radeonfb_info *rinfo = info->par;
1128 u32 dac_cntl2, vclk_cntl = 0;
1129 int rc;
1130
1131 if (!rinfo->asleep) {
1132 if (rinfo->is_mobility) {
1133 vclk_cntl = INPLL(VCLK_ECP_CNTL);
1134 OUTPLL(VCLK_ECP_CNTL,
1135 vclk_cntl & ~PIXCLK_DAC_ALWAYS_ONb);
1136 }
1137
1138 /* Make sure we are on first palette */
1139 if (rinfo->has_CRTC2) {
1140 dac_cntl2 = INREG(DAC_CNTL2);
1141 dac_cntl2 &= ~DAC2_PALETTE_ACCESS_CNTL;
1142 OUTREG(DAC_CNTL2, dac_cntl2);
1143 }
1144 }
1145
1146 rc = radeon_setcolreg (regno, red, green, blue, transp, rinfo);
1147
1148 if (!rinfo->asleep && rinfo->is_mobility)
1149 OUTPLL(VCLK_ECP_CNTL, vclk_cntl);
1150
1151 return rc;
1152 }
1153
1154 static int radeonfb_setcmap(struct fb_cmap *cmap, struct fb_info *info)
1155 {
1156 struct radeonfb_info *rinfo = info->par;
1157 u16 *red, *green, *blue, *transp;
1158 u32 dac_cntl2, vclk_cntl = 0;
1159 int i, start, rc = 0;
1160
1161 if (!rinfo->asleep) {
1162 if (rinfo->is_mobility) {
1163 vclk_cntl = INPLL(VCLK_ECP_CNTL);
1164 OUTPLL(VCLK_ECP_CNTL,
1165 vclk_cntl & ~PIXCLK_DAC_ALWAYS_ONb);
1166 }
1167
1168 /* Make sure we are on first palette */
1169 if (rinfo->has_CRTC2) {
1170 dac_cntl2 = INREG(DAC_CNTL2);
1171 dac_cntl2 &= ~DAC2_PALETTE_ACCESS_CNTL;
1172 OUTREG(DAC_CNTL2, dac_cntl2);
1173 }
1174 }
1175
1176 red = cmap->red;
1177 green = cmap->green;
1178 blue = cmap->blue;
1179 transp = cmap->transp;
1180 start = cmap->start;
1181
1182 for (i = 0; i < cmap->len; i++) {
1183 u_int hred, hgreen, hblue, htransp = 0xffff;
1184
1185 hred = *red++;
1186 hgreen = *green++;
1187 hblue = *blue++;
1188 if (transp)
1189 htransp = *transp++;
1190 rc = radeon_setcolreg (start++, hred, hgreen, hblue, htransp,
1191 rinfo);
1192 if (rc)
1193 break;
1194 }
1195
1196 if (!rinfo->asleep && rinfo->is_mobility)
1197 OUTPLL(VCLK_ECP_CNTL, vclk_cntl);
1198
1199 return rc;
1200 }
1201
1202 static void radeon_save_state (struct radeonfb_info *rinfo,
1203 struct radeon_regs *save)
1204 {
1205 /* CRTC regs */
1206 save->crtc_gen_cntl = INREG(CRTC_GEN_CNTL);
1207 save->crtc_ext_cntl = INREG(CRTC_EXT_CNTL);
1208 save->crtc_more_cntl = INREG(CRTC_MORE_CNTL);
1209 save->dac_cntl = INREG(DAC_CNTL);
1210 save->crtc_h_total_disp = INREG(CRTC_H_TOTAL_DISP);
1211 save->crtc_h_sync_strt_wid = INREG(CRTC_H_SYNC_STRT_WID);
1212 save->crtc_v_total_disp = INREG(CRTC_V_TOTAL_DISP);
1213 save->crtc_v_sync_strt_wid = INREG(CRTC_V_SYNC_STRT_WID);
1214 save->crtc_pitch = INREG(CRTC_PITCH);
1215 save->surface_cntl = INREG(SURFACE_CNTL);
1216
1217 /* FP regs */
1218 save->fp_crtc_h_total_disp = INREG(FP_CRTC_H_TOTAL_DISP);
1219 save->fp_crtc_v_total_disp = INREG(FP_CRTC_V_TOTAL_DISP);
1220 save->fp_gen_cntl = INREG(FP_GEN_CNTL);
1221 save->fp_h_sync_strt_wid = INREG(FP_H_SYNC_STRT_WID);
1222 save->fp_horz_stretch = INREG(FP_HORZ_STRETCH);
1223 save->fp_v_sync_strt_wid = INREG(FP_V_SYNC_STRT_WID);
1224 save->fp_vert_stretch = INREG(FP_VERT_STRETCH);
1225 save->lvds_gen_cntl = INREG(LVDS_GEN_CNTL);
1226 save->lvds_pll_cntl = INREG(LVDS_PLL_CNTL);
1227 save->tmds_crc = INREG(TMDS_CRC);
1228 save->tmds_transmitter_cntl = INREG(TMDS_TRANSMITTER_CNTL);
1229 save->vclk_ecp_cntl = INPLL(VCLK_ECP_CNTL);
1230
1231 /* PLL regs */
1232 save->clk_cntl_index = INREG(CLOCK_CNTL_INDEX) & ~0x3f;
1233 radeon_pll_errata_after_index(rinfo);
1234 save->ppll_div_3 = INPLL(PPLL_DIV_3);
1235 save->ppll_ref_div = INPLL(PPLL_REF_DIV);
1236 }
1237
1238
1239 static void radeon_write_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *mode)
1240 {
1241 int i;
1242
1243 radeon_fifo_wait(20);
1244
1245 /* Workaround from XFree */
1246 if (rinfo->is_mobility) {
1247 /* A temporal workaround for the occational blanking on certain laptop
1248 * panels. This appears to related to the PLL divider registers
1249 * (fail to lock?). It occurs even when all dividers are the same
1250 * with their old settings. In this case we really don't need to
1251 * fiddle with PLL registers. By doing this we can avoid the blanking
1252 * problem with some panels.
1253 */
1254 if ((mode->ppll_ref_div == (INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK)) &&
1255 (mode->ppll_div_3 == (INPLL(PPLL_DIV_3) &
1256 (PPLL_POST3_DIV_MASK | PPLL_FB3_DIV_MASK)))) {
1257 /* We still have to force a switch to selected PPLL div thanks to
1258 * an XFree86 driver bug which will switch it away in some cases
1259 * even when using UseFDev */
1260 OUTREGP(CLOCK_CNTL_INDEX,
1261 mode->clk_cntl_index & PPLL_DIV_SEL_MASK,
1262 ~PPLL_DIV_SEL_MASK);
1263 radeon_pll_errata_after_index(rinfo);
1264 radeon_pll_errata_after_data(rinfo);
1265 return;
1266 }
1267 }
1268
1269 /* Swich VCKL clock input to CPUCLK so it stays fed while PPLL updates*/
1270 OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_CPUCLK, ~VCLK_SRC_SEL_MASK);
1271
1272 /* Reset PPLL & enable atomic update */
1273 OUTPLLP(PPLL_CNTL,
1274 PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN,
1275 ~(PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN));
1276
1277 /* Switch to selected PPLL divider */
1278 OUTREGP(CLOCK_CNTL_INDEX,
1279 mode->clk_cntl_index & PPLL_DIV_SEL_MASK,
1280 ~PPLL_DIV_SEL_MASK);
1281 radeon_pll_errata_after_index(rinfo);
1282 radeon_pll_errata_after_data(rinfo);
1283
1284 /* Set PPLL ref. div */
1285 if (rinfo->family == CHIP_FAMILY_R300 ||
1286 rinfo->family == CHIP_FAMILY_RS300 ||
1287 rinfo->family == CHIP_FAMILY_R350 ||
1288 rinfo->family == CHIP_FAMILY_RV350) {
1289 if (mode->ppll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) {
1290 /* When restoring console mode, use saved PPLL_REF_DIV
1291 * setting.
1292 */
1293 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, 0);
1294 } else {
1295 /* R300 uses ref_div_acc field as real ref divider */
1296 OUTPLLP(PPLL_REF_DIV,
1297 (mode->ppll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT),
1298 ~R300_PPLL_REF_DIV_ACC_MASK);
1299 }
1300 } else
1301 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, ~PPLL_REF_DIV_MASK);
1302
1303 /* Set PPLL divider 3 & post divider*/
1304 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_FB3_DIV_MASK);
1305 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_POST3_DIV_MASK);
1306
1307 /* Write update */
1308 while (INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R)
1309 ;
1310 OUTPLLP(PPLL_REF_DIV, PPLL_ATOMIC_UPDATE_W, ~PPLL_ATOMIC_UPDATE_W);
1311
1312 /* Wait read update complete */
1313 /* FIXME: Certain revisions of R300 can't recover here. Not sure of
1314 the cause yet, but this workaround will mask the problem for now.
1315 Other chips usually will pass at the very first test, so the
1316 workaround shouldn't have any effect on them. */
1317 for (i = 0; (i < 10000 && INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R); i++)
1318 ;
1319
1320 OUTPLL(HTOTAL_CNTL, 0);
1321
1322 /* Clear reset & atomic update */
1323 OUTPLLP(PPLL_CNTL, 0,
1324 ~(PPLL_RESET | PPLL_SLEEP | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN));
1325
1326 /* We may want some locking ... oh well */
1327 radeon_msleep(5);
1328
1329 /* Switch back VCLK source to PPLL */
1330 OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_PPLLCLK, ~VCLK_SRC_SEL_MASK);
1331 }
1332
1333 /*
1334 * Timer function for delayed LVDS panel power up/down
1335 */
1336 static void radeon_lvds_timer_func(unsigned long data)
1337 {
1338 struct radeonfb_info *rinfo = (struct radeonfb_info *)data;
1339
1340 radeon_engine_idle();
1341
1342 OUTREG(LVDS_GEN_CNTL, rinfo->pending_lvds_gen_cntl);
1343 }
1344
1345 /*
1346 * Apply a video mode. This will apply the whole register set, including
1347 * the PLL registers, to the card
1348 */
1349 void radeon_write_mode (struct radeonfb_info *rinfo, struct radeon_regs *mode,
1350 int regs_only)
1351 {
1352 int i;
1353 int primary_mon = PRIMARY_MONITOR(rinfo);
1354
1355 if (nomodeset)
1356 return;
1357
1358 if (!regs_only)
1359 radeon_screen_blank(rinfo, FB_BLANK_NORMAL, 0);
1360
1361 radeon_fifo_wait(31);
1362 for (i=0; i<10; i++)
1363 OUTREG(common_regs[i].reg, common_regs[i].val);
1364
1365 /* Apply surface registers */
1366 for (i=0; i<8; i++) {
1367 OUTREG(SURFACE0_LOWER_BOUND + 0x10*i, mode->surf_lower_bound[i]);
1368 OUTREG(SURFACE0_UPPER_BOUND + 0x10*i, mode->surf_upper_bound[i]);
1369 OUTREG(SURFACE0_INFO + 0x10*i, mode->surf_info[i]);
1370 }
1371
1372 OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl);
1373 OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl,
1374 ~(CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS));
1375 OUTREG(CRTC_MORE_CNTL, mode->crtc_more_cntl);
1376 OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL | DAC_BLANKING);
1377 OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp);
1378 OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid);
1379 OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp);
1380 OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid);
1381 OUTREG(CRTC_OFFSET, 0);
1382 OUTREG(CRTC_OFFSET_CNTL, 0);
1383 OUTREG(CRTC_PITCH, mode->crtc_pitch);
1384 OUTREG(SURFACE_CNTL, mode->surface_cntl);
1385
1386 radeon_write_pll_regs(rinfo, mode);
1387
1388 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1389 radeon_fifo_wait(10);
1390 OUTREG(FP_CRTC_H_TOTAL_DISP, mode->fp_crtc_h_total_disp);
1391 OUTREG(FP_CRTC_V_TOTAL_DISP, mode->fp_crtc_v_total_disp);
1392 OUTREG(FP_H_SYNC_STRT_WID, mode->fp_h_sync_strt_wid);
1393 OUTREG(FP_V_SYNC_STRT_WID, mode->fp_v_sync_strt_wid);
1394 OUTREG(FP_HORZ_STRETCH, mode->fp_horz_stretch);
1395 OUTREG(FP_VERT_STRETCH, mode->fp_vert_stretch);
1396 OUTREG(FP_GEN_CNTL, mode->fp_gen_cntl);
1397 OUTREG(TMDS_CRC, mode->tmds_crc);
1398 OUTREG(TMDS_TRANSMITTER_CNTL, mode->tmds_transmitter_cntl);
1399 }
1400
1401 if (!regs_only)
1402 radeon_screen_blank(rinfo, FB_BLANK_UNBLANK, 0);
1403
1404 radeon_fifo_wait(2);
1405 OUTPLL(VCLK_ECP_CNTL, mode->vclk_ecp_cntl);
1406
1407 return;
1408 }
1409
1410 /*
1411 * Calculate the PLL values for a given mode
1412 */
1413 static void radeon_calc_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *regs,
1414 unsigned long freq)
1415 {
1416 const struct {
1417 int divider;
1418 int bitvalue;
1419 } *post_div,
1420 post_divs[] = {
1421 { 1, 0 },
1422 { 2, 1 },
1423 { 4, 2 },
1424 { 8, 3 },
1425 { 3, 4 },
1426 { 16, 5 },
1427 { 6, 6 },
1428 { 12, 7 },
1429 { 0, 0 },
1430 };
1431 int fb_div, pll_output_freq = 0;
1432 int uses_dvo = 0;
1433
1434 /* Check if the DVO port is enabled and sourced from the primary CRTC. I'm
1435 * not sure which model starts having FP2_GEN_CNTL, I assume anything more
1436 * recent than an r(v)100...
1437 */
1438 #if 1
1439 /* XXX I had reports of flicker happening with the cinema display
1440 * on TMDS1 that seem to be fixed if I also forbit odd dividers in
1441 * this case. This could just be a bandwidth calculation issue, I
1442 * haven't implemented the bandwidth code yet, but in the meantime,
1443 * forcing uses_dvo to 1 fixes it and shouln't have bad side effects,
1444 * I haven't seen a case were were absolutely needed an odd PLL
1445 * divider. I'll find a better fix once I have more infos on the
1446 * real cause of the problem.
1447 */
1448 while (rinfo->has_CRTC2) {
1449 u32 fp2_gen_cntl = INREG(FP2_GEN_CNTL);
1450 u32 disp_output_cntl;
1451 int source;
1452
1453 /* FP2 path not enabled */
1454 if ((fp2_gen_cntl & FP2_ON) == 0)
1455 break;
1456 /* Not all chip revs have the same format for this register,
1457 * extract the source selection
1458 */
1459 if (rinfo->family == CHIP_FAMILY_R200 ||
1460 rinfo->family == CHIP_FAMILY_R300 ||
1461 rinfo->family == CHIP_FAMILY_R350 ||
1462 rinfo->family == CHIP_FAMILY_RV350) {
1463 source = (fp2_gen_cntl >> 10) & 0x3;
1464 /* sourced from transform unit, check for transform unit
1465 * own source
1466 */
1467 if (source == 3) {
1468 disp_output_cntl = INREG(DISP_OUTPUT_CNTL);
1469 source = (disp_output_cntl >> 12) & 0x3;
1470 }
1471 } else
1472 source = (fp2_gen_cntl >> 13) & 0x1;
1473 /* sourced from CRTC2 -> exit */
1474 if (source == 1)
1475 break;
1476
1477 /* so we end up on CRTC1, let's set uses_dvo to 1 now */
1478 uses_dvo = 1;
1479 break;
1480 }
1481 #else
1482 uses_dvo = 1;
1483 #endif
1484 if (freq > rinfo->pll.ppll_max)
1485 freq = rinfo->pll.ppll_max;
1486 if (freq*12 < rinfo->pll.ppll_min)
1487 freq = rinfo->pll.ppll_min / 12;
1488 RTRACE("freq = %lu, PLL min = %u, PLL max = %u\n",
1489 freq, rinfo->pll.ppll_min, rinfo->pll.ppll_max);
1490
1491 for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
1492 pll_output_freq = post_div->divider * freq;
1493 /* If we output to the DVO port (external TMDS), we don't allow an
1494 * odd PLL divider as those aren't supported on this path
1495 */
1496 if (uses_dvo && (post_div->divider & 1))
1497 continue;
1498 if (pll_output_freq >= rinfo->pll.ppll_min &&
1499 pll_output_freq <= rinfo->pll.ppll_max)
1500 break;
1501 }
1502
1503 /* If we fall through the bottom, try the "default value"
1504 given by the terminal post_div->bitvalue */
1505 if ( !post_div->divider ) {
1506 post_div = &post_divs[post_div->bitvalue];
1507 pll_output_freq = post_div->divider * freq;
1508 }
1509 RTRACE("ref_div = %d, ref_clk = %d, output_freq = %d\n",
1510 rinfo->pll.ref_div, rinfo->pll.ref_clk,
1511 pll_output_freq);
1512
1513 /* If we fall through the bottom, try the "default value"
1514 given by the terminal post_div->bitvalue */
1515 if ( !post_div->divider ) {
1516 post_div = &post_divs[post_div->bitvalue];
1517 pll_output_freq = post_div->divider * freq;
1518 }
1519 RTRACE("ref_div = %d, ref_clk = %d, output_freq = %d\n",
1520 rinfo->pll.ref_div, rinfo->pll.ref_clk,
1521 pll_output_freq);
1522
1523 fb_div = round_div(rinfo->pll.ref_div*pll_output_freq,
1524 rinfo->pll.ref_clk);
1525 regs->ppll_ref_div = rinfo->pll.ref_div;
1526 regs->ppll_div_3 = fb_div | (post_div->bitvalue << 16);
1527
1528 RTRACE("post div = 0x%x\n", post_div->bitvalue);
1529 RTRACE("fb_div = 0x%x\n", fb_div);
1530 RTRACE("ppll_div_3 = 0x%x\n", regs->ppll_div_3);
1531 }
1532
1533 static int radeonfb_set_par(struct fb_info *info)
1534 {
1535 struct radeonfb_info *rinfo = info->par;
1536 struct fb_var_screeninfo *mode = &info->var;
1537 struct radeon_regs *newmode;
1538 int hTotal, vTotal, hSyncStart, hSyncEnd,
1539 hSyncPol, vSyncStart, vSyncEnd, vSyncPol, cSync;
1540 u8 hsync_adj_tab[] = {0, 0x12, 9, 9, 6, 5};
1541 u8 hsync_fudge_fp[] = {2, 2, 0, 0, 5, 5};
1542 u32 sync, h_sync_pol, v_sync_pol, dotClock, pixClock;
1543 int i, freq;
1544 int format = 0;
1545 int nopllcalc = 0;
1546 int hsync_start, hsync_fudge, bytpp, hsync_wid, vsync_wid;
1547 int primary_mon = PRIMARY_MONITOR(rinfo);
1548 int depth = var_to_depth(mode);
1549 int use_rmx = 0;
1550
1551 newmode = kmalloc(sizeof(struct radeon_regs), GFP_KERNEL);
1552 if (!newmode)
1553 return -ENOMEM;
1554
1555 /* We always want engine to be idle on a mode switch, even
1556 * if we won't actually change the mode
1557 */
1558 radeon_engine_idle();
1559
1560 hSyncStart = mode->xres + mode->right_margin;
1561 hSyncEnd = hSyncStart + mode->hsync_len;
1562 hTotal = hSyncEnd + mode->left_margin;
1563
1564 vSyncStart = mode->yres + mode->lower_margin;
1565 vSyncEnd = vSyncStart + mode->vsync_len;
1566 vTotal = vSyncEnd + mode->upper_margin;
1567 pixClock = mode->pixclock;
1568
1569 sync = mode->sync;
1570 h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
1571 v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
1572
1573 if (primary_mon == MT_DFP || primary_mon == MT_LCD) {
1574 if (rinfo->panel_info.xres < mode->xres)
1575 mode->xres = rinfo->panel_info.xres;
1576 if (rinfo->panel_info.yres < mode->yres)
1577 mode->yres = rinfo->panel_info.yres;
1578
1579 hTotal = mode->xres + rinfo->panel_info.hblank;
1580 hSyncStart = mode->xres + rinfo->panel_info.hOver_plus;
1581 hSyncEnd = hSyncStart + rinfo->panel_info.hSync_width;
1582
1583 vTotal = mode->yres + rinfo->panel_info.vblank;
1584 vSyncStart = mode->yres + rinfo->panel_info.vOver_plus;
1585 vSyncEnd = vSyncStart + rinfo->panel_info.vSync_width;
1586
1587 h_sync_pol = !rinfo->panel_info.hAct_high;
1588 v_sync_pol = !rinfo->panel_info.vAct_high;
1589
1590 pixClock = 100000000 / rinfo->panel_info.clock;
1591
1592 if (rinfo->panel_info.use_bios_dividers) {
1593 nopllcalc = 1;
1594 newmode->ppll_div_3 = rinfo->panel_info.fbk_divider |
1595 (rinfo->panel_info.post_divider << 16);
1596 newmode->ppll_ref_div = rinfo->panel_info.ref_divider;
1597 }
1598 }
1599 dotClock = 1000000000 / pixClock;
1600 freq = dotClock / 10; /* x100 */
1601
1602 RTRACE("hStart = %d, hEnd = %d, hTotal = %d\n",
1603 hSyncStart, hSyncEnd, hTotal);
1604 RTRACE("vStart = %d, vEnd = %d, vTotal = %d\n",
1605 vSyncStart, vSyncEnd, vTotal);
1606
1607 hsync_wid = (hSyncEnd - hSyncStart) / 8;
1608 vsync_wid = vSyncEnd - vSyncStart;
1609 if (hsync_wid == 0)
1610 hsync_wid = 1;
1611 else if (hsync_wid > 0x3f) /* max */
1612 hsync_wid = 0x3f;
1613
1614 if (vsync_wid == 0)
1615 vsync_wid = 1;
1616 else if (vsync_wid > 0x1f) /* max */
1617 vsync_wid = 0x1f;
1618
1619 hSyncPol = mode->sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
1620 vSyncPol = mode->sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
1621
1622 cSync = mode->sync & FB_SYNC_COMP_HIGH_ACT ? (1 << 4) : 0;
1623
1624 format = radeon_get_dstbpp(depth);
1625 bytpp = mode->bits_per_pixel >> 3;
1626
1627 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD))
1628 hsync_fudge = hsync_fudge_fp[format-1];
1629 else
1630 hsync_fudge = hsync_adj_tab[format-1];
1631
1632 hsync_start = hSyncStart - 8 + hsync_fudge;
1633
1634 newmode->crtc_gen_cntl = CRTC_EXT_DISP_EN | CRTC_EN |
1635 (format << 8);
1636
1637 /* Clear auto-center etc... */
1638 newmode->crtc_more_cntl = rinfo->init_state.crtc_more_cntl;
1639 newmode->crtc_more_cntl &= 0xfffffff0;
1640
1641 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1642 newmode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN;
1643 if (mirror)
1644 newmode->crtc_ext_cntl |= CRTC_CRT_ON;
1645
1646 newmode->crtc_gen_cntl &= ~(CRTC_DBL_SCAN_EN |
1647 CRTC_INTERLACE_EN);
1648 } else {
1649 newmode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN |
1650 CRTC_CRT_ON;
1651 }
1652
1653 newmode->dac_cntl = /* INREG(DAC_CNTL) | */ DAC_MASK_ALL | DAC_VGA_ADR_EN |
1654 DAC_8BIT_EN;
1655
1656 newmode->crtc_h_total_disp = ((((hTotal / 8) - 1) & 0x3ff) |
1657 (((mode->xres / 8) - 1) << 16));
1658
1659 newmode->crtc_h_sync_strt_wid = ((hsync_start & 0x1fff) |
1660 (hsync_wid << 16) | (h_sync_pol << 23));
1661
1662 newmode->crtc_v_total_disp = ((vTotal - 1) & 0xffff) |
1663 ((mode->yres - 1) << 16);
1664
1665 newmode->crtc_v_sync_strt_wid = (((vSyncStart - 1) & 0xfff) |
1666 (vsync_wid << 16) | (v_sync_pol << 23));
1667
1668 if (!(info->flags & FBINFO_HWACCEL_DISABLED)) {
1669 /* We first calculate the engine pitch */
1670 rinfo->pitch = ((mode->xres_virtual * ((mode->bits_per_pixel + 1) / 8) + 0x3f)
1671 & ~(0x3f)) >> 6;
1672
1673 /* Then, re-multiply it to get the CRTC pitch */
1674 newmode->crtc_pitch = (rinfo->pitch << 3) / ((mode->bits_per_pixel + 1) / 8);
1675 } else
1676 newmode->crtc_pitch = (mode->xres_virtual >> 3);
1677
1678 newmode->crtc_pitch |= (newmode->crtc_pitch << 16);
1679
1680 /*
1681 * It looks like recent chips have a problem with SURFACE_CNTL,
1682 * setting SURF_TRANSLATION_DIS completely disables the
1683 * swapper as well, so we leave it unset now.
1684 */
1685 newmode->surface_cntl = 0;
1686
1687 #if defined(__BIG_ENDIAN)
1688
1689 /* Setup swapping on both apertures, though we currently
1690 * only use aperture 0, enabling swapper on aperture 1
1691 * won't harm
1692 */
1693 switch (mode->bits_per_pixel) {
1694 case 16:
1695 newmode->surface_cntl |= NONSURF_AP0_SWP_16BPP;
1696 newmode->surface_cntl |= NONSURF_AP1_SWP_16BPP;
1697 break;
1698 case 24:
1699 case 32:
1700 newmode->surface_cntl |= NONSURF_AP0_SWP_32BPP;
1701 newmode->surface_cntl |= NONSURF_AP1_SWP_32BPP;
1702 break;
1703 }
1704 #endif
1705
1706 /* Clear surface registers */
1707 for (i=0; i<8; i++) {
1708 newmode->surf_lower_bound[i] = 0;
1709 newmode->surf_upper_bound[i] = 0x1f;
1710 newmode->surf_info[i] = 0;
1711 }
1712
1713 RTRACE("h_total_disp = 0x%x\t hsync_strt_wid = 0x%x\n",
1714 newmode->crtc_h_total_disp, newmode->crtc_h_sync_strt_wid);
1715 RTRACE("v_total_disp = 0x%x\t vsync_strt_wid = 0x%x\n",
1716 newmode->crtc_v_total_disp, newmode->crtc_v_sync_strt_wid);
1717
1718 rinfo->bpp = mode->bits_per_pixel;
1719 rinfo->depth = depth;
1720
1721 RTRACE("pixclock = %lu\n", (unsigned long)pixClock);
1722 RTRACE("freq = %lu\n", (unsigned long)freq);
1723
1724 /* We use PPLL_DIV_3 */
1725 newmode->clk_cntl_index = 0x300;
1726
1727 /* Calculate PPLL value if necessary */
1728 if (!nopllcalc)
1729 radeon_calc_pll_regs(rinfo, newmode, freq);
1730
1731 newmode->vclk_ecp_cntl = rinfo->init_state.vclk_ecp_cntl;
1732
1733 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1734 unsigned int hRatio, vRatio;
1735
1736 if (mode->xres > rinfo->panel_info.xres)
1737 mode->xres = rinfo->panel_info.xres;
1738 if (mode->yres > rinfo->panel_info.yres)
1739 mode->yres = rinfo->panel_info.yres;
1740
1741 newmode->fp_horz_stretch = (((rinfo->panel_info.xres / 8) - 1)
1742 << HORZ_PANEL_SHIFT);
1743 newmode->fp_vert_stretch = ((rinfo->panel_info.yres - 1)
1744 << VERT_PANEL_SHIFT);
1745
1746 if (mode->xres != rinfo->panel_info.xres) {
1747 hRatio = round_div(mode->xres * HORZ_STRETCH_RATIO_MAX,
1748 rinfo->panel_info.xres);
1749 newmode->fp_horz_stretch = (((((unsigned long)hRatio) & HORZ_STRETCH_RATIO_MASK)) |
1750 (newmode->fp_horz_stretch &
1751 (HORZ_PANEL_SIZE | HORZ_FP_LOOP_STRETCH |
1752 HORZ_AUTO_RATIO_INC)));
1753 newmode->fp_horz_stretch |= (HORZ_STRETCH_BLEND |
1754 HORZ_STRETCH_ENABLE);
1755 use_rmx = 1;
1756 }
1757 newmode->fp_horz_stretch &= ~HORZ_AUTO_RATIO;
1758
1759 if (mode->yres != rinfo->panel_info.yres) {
1760 vRatio = round_div(mode->yres * VERT_STRETCH_RATIO_MAX,
1761 rinfo->panel_info.yres);
1762 newmode->fp_vert_stretch = (((((unsigned long)vRatio) & VERT_STRETCH_RATIO_MASK)) |
1763 (newmode->fp_vert_stretch &
1764 (VERT_PANEL_SIZE | VERT_STRETCH_RESERVED)));
1765 newmode->fp_vert_stretch |= (VERT_STRETCH_BLEND |
1766 VERT_STRETCH_ENABLE);
1767 use_rmx = 1;
1768 }
1769 newmode->fp_vert_stretch &= ~VERT_AUTO_RATIO_EN;
1770
1771 newmode->fp_gen_cntl = (rinfo->init_state.fp_gen_cntl & (u32)
1772 ~(FP_SEL_CRTC2 |
1773 FP_RMX_HVSYNC_CONTROL_EN |
1774 FP_DFP_SYNC_SEL |
1775 FP_CRT_SYNC_SEL |
1776 FP_CRTC_LOCK_8DOT |
1777 FP_USE_SHADOW_EN |
1778 FP_CRTC_USE_SHADOW_VEND |
1779 FP_CRT_SYNC_ALT));
1780
1781 newmode->fp_gen_cntl |= (FP_CRTC_DONT_SHADOW_VPAR |
1782 FP_CRTC_DONT_SHADOW_HEND |
1783 FP_PANEL_FORMAT);
1784
1785 if (IS_R300_VARIANT(rinfo) ||
1786 (rinfo->family == CHIP_FAMILY_R200)) {
1787 newmode->fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
1788 if (use_rmx)
1789 newmode->fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX;
1790 else
1791 newmode->fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1;
1792 } else
1793 newmode->fp_gen_cntl |= FP_SEL_CRTC1;
1794
1795 newmode->lvds_gen_cntl = rinfo->init_state.lvds_gen_cntl;
1796 newmode->lvds_pll_cntl = rinfo->init_state.lvds_pll_cntl;
1797 newmode->tmds_crc = rinfo->init_state.tmds_crc;
1798 newmode->tmds_transmitter_cntl = rinfo->init_state.tmds_transmitter_cntl;
1799
1800 if (primary_mon == MT_LCD) {
1801 newmode->lvds_gen_cntl |= (LVDS_ON | LVDS_BLON);
1802 newmode->fp_gen_cntl &= ~(FP_FPON | FP_TMDS_EN);
1803 } else {
1804 /* DFP */
1805 newmode->fp_gen_cntl |= (FP_FPON | FP_TMDS_EN);
1806 newmode->tmds_transmitter_cntl &= ~(TMDS_PLLRST);
1807 /* TMDS_PLL_EN bit is reversed on RV (and mobility) chips */
1808 if (IS_R300_VARIANT(rinfo) ||
1809 (rinfo->family == CHIP_FAMILY_R200) || !rinfo->has_CRTC2)
1810 newmode->tmds_transmitter_cntl &= ~TMDS_PLL_EN;
1811 else
1812 newmode->tmds_transmitter_cntl |= TMDS_PLL_EN;
1813 newmode->crtc_ext_cntl &= ~CRTC_CRT_ON;
1814 }
1815
1816 newmode->fp_crtc_h_total_disp = (((rinfo->panel_info.hblank / 8) & 0x3ff) |
1817 (((mode->xres / 8) - 1) << 16));
1818 newmode->fp_crtc_v_total_disp = (rinfo->panel_info.vblank & 0xffff) |
1819 ((mode->yres - 1) << 16);
1820 newmode->fp_h_sync_strt_wid = ((rinfo->panel_info.hOver_plus & 0x1fff) |
1821 (hsync_wid << 16) | (h_sync_pol << 23));
1822 newmode->fp_v_sync_strt_wid = ((rinfo->panel_info.vOver_plus & 0xfff) |
1823 (vsync_wid << 16) | (v_sync_pol << 23));
1824 }
1825
1826 /* do it! */
1827 if (!rinfo->asleep) {
1828 memcpy(&rinfo->state, newmode, sizeof(*newmode));
1829 radeon_write_mode (rinfo, newmode, 0);
1830 /* (re)initialize the engine */
1831 if (!(info->flags & FBINFO_HWACCEL_DISABLED))
1832 radeonfb_engine_init (rinfo);
1833 }
1834 /* Update fix */
1835 if (!(info->flags & FBINFO_HWACCEL_DISABLED))
1836 info->fix.line_length = rinfo->pitch*64;
1837 else
1838 info->fix.line_length = mode->xres_virtual
1839 * ((mode->bits_per_pixel + 1) / 8);
1840 info->fix.visual = rinfo->depth == 8 ? FB_VISUAL_PSEUDOCOLOR
1841 : FB_VISUAL_DIRECTCOLOR;
1842
1843 #ifdef CONFIG_BOOTX_TEXT
1844 /* Update debug text engine */
1845 btext_update_display(rinfo->fb_base_phys, mode->xres, mode->yres,
1846 rinfo->depth, info->fix.line_length);
1847 #endif
1848
1849 kfree(newmode);
1850 return 0;
1851 }
1852
1853
1854 static struct fb_ops radeonfb_ops = {
1855 .owner = THIS_MODULE,
1856 .fb_check_var = radeonfb_check_var,
1857 .fb_set_par = radeonfb_set_par,
1858 .fb_setcolreg = radeonfb_setcolreg,
1859 .fb_setcmap = radeonfb_setcmap,
1860 .fb_pan_display = radeonfb_pan_display,
1861 .fb_blank = radeonfb_blank,
1862 .fb_ioctl = radeonfb_ioctl,
1863 .fb_sync = radeonfb_sync,
1864 .fb_fillrect = radeonfb_fillrect,
1865 .fb_copyarea = radeonfb_copyarea,
1866 .fb_imageblit = radeonfb_imageblit,
1867 };
1868
1869
1870 static int __devinit radeon_set_fbinfo (struct radeonfb_info *rinfo)
1871 {
1872 struct fb_info *info = rinfo->info;
1873
1874 info->par = rinfo;
1875 info->pseudo_palette = rinfo->pseudo_palette;
1876 info->flags = FBINFO_DEFAULT
1877 | FBINFO_HWACCEL_COPYAREA
1878 | FBINFO_HWACCEL_FILLRECT
1879 | FBINFO_HWACCEL_XPAN
1880 | FBINFO_HWACCEL_YPAN;
1881 info->fbops = &radeonfb_ops;
1882 info->screen_base = rinfo->fb_base;
1883 info->screen_size = rinfo->mapped_vram;
1884 /* Fill fix common fields */
1885 strlcpy(info->fix.id, rinfo->name, sizeof(info->fix.id));
1886 info->fix.smem_start = rinfo->fb_base_phys;
1887 info->fix.smem_len = rinfo->video_ram;
1888 info->fix.type = FB_TYPE_PACKED_PIXELS;
1889 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
1890 info->fix.xpanstep = 8;
1891 info->fix.ypanstep = 1;
1892 info->fix.ywrapstep = 0;
1893 info->fix.type_aux = 0;
1894 info->fix.mmio_start = rinfo->mmio_base_phys;
1895 info->fix.mmio_len = RADEON_REGSIZE;
1896 info->fix.accel = FB_ACCEL_ATI_RADEON;
1897
1898 fb_alloc_cmap(&info->cmap, 256, 0);
1899
1900 if (noaccel)
1901 info->flags |= FBINFO_HWACCEL_DISABLED;
1902
1903 return 0;
1904 }
1905
1906 /*
1907 * This reconfigure the card's internal memory map. In theory, we'd like
1908 * to setup the card's memory at the same address as it's PCI bus address,
1909 * and the AGP aperture right after that so that system RAM on 32 bits
1910 * machines at least, is directly accessible. However, doing so would
1911 * conflict with the current XFree drivers...
1912 * Ultimately, I hope XFree, GATOS and ATI binary drivers will all agree
1913 * on the proper way to set this up and duplicate this here. In the meantime,
1914 * I put the card's memory at 0 in card space and AGP at some random high
1915 * local (0xe0000000 for now) that will be changed by XFree/DRI anyway
1916 */
1917 #ifdef CONFIG_PPC_OF
1918 #undef SET_MC_FB_FROM_APERTURE
1919 static void fixup_memory_mappings(struct radeonfb_info *rinfo)
1920 {
1921 u32 save_crtc_gen_cntl, save_crtc2_gen_cntl = 0;
1922 u32 save_crtc_ext_cntl;
1923 u32 aper_base, aper_size;
1924 u32 agp_base;
1925
1926 /* First, we disable display to avoid interfering */
1927 if (rinfo->has_CRTC2) {
1928 save_crtc2_gen_cntl = INREG(CRTC2_GEN_CNTL);
1929 OUTREG(CRTC2_GEN_CNTL, save_crtc2_gen_cntl | CRTC2_DISP_REQ_EN_B);
1930 }
1931 save_crtc_gen_cntl = INREG(CRTC_GEN_CNTL);
1932 save_crtc_ext_cntl = INREG(CRTC_EXT_CNTL);
1933
1934 OUTREG(CRTC_EXT_CNTL, save_crtc_ext_cntl | CRTC_DISPLAY_DIS);
1935 OUTREG(CRTC_GEN_CNTL, save_crtc_gen_cntl | CRTC_DISP_REQ_EN_B);
1936 mdelay(100);
1937
1938 aper_base = INREG(CONFIG_APER_0_BASE);
1939 aper_size = INREG(CONFIG_APER_SIZE);
1940
1941 #ifdef SET_MC_FB_FROM_APERTURE
1942 /* Set framebuffer to be at the same address as set in PCI BAR */
1943 OUTREG(MC_FB_LOCATION,
1944 ((aper_base + aper_size - 1) & 0xffff0000) | (aper_base >> 16));
1945 rinfo->fb_local_base = aper_base;
1946 #else
1947 OUTREG(MC_FB_LOCATION, 0x7fff0000);
1948 rinfo->fb_local_base = 0;
1949 #endif
1950 agp_base = aper_base + aper_size;
1951 if (agp_base & 0xf0000000)
1952 agp_base = (aper_base | 0x0fffffff) + 1;
1953
1954 /* Set AGP to be just after the framebuffer on a 256Mb boundary. This
1955 * assumes the FB isn't mapped to 0xf0000000 or above, but this is
1956 * always the case on PPCs afaik.
1957 */
1958 #ifdef SET_MC_FB_FROM_APERTURE
1959 OUTREG(MC_AGP_LOCATION, 0xffff0000 | (agp_base >> 16));
1960 #else
1961 OUTREG(MC_AGP_LOCATION, 0xffffe000);
1962 #endif
1963
1964 /* Fixup the display base addresses & engine offsets while we
1965 * are at it as well
1966 */
1967 #ifdef SET_MC_FB_FROM_APERTURE
1968 OUTREG(DISPLAY_BASE_ADDR, aper_base);
1969 if (rinfo->has_CRTC2)
1970 OUTREG(CRTC2_DISPLAY_BASE_ADDR, aper_base);
1971 OUTREG(OV0_BASE_ADDR, aper_base);
1972 #else
1973 OUTREG(DISPLAY_BASE_ADDR, 0);
1974 if (rinfo->has_CRTC2)
1975 OUTREG(CRTC2_DISPLAY_BASE_ADDR, 0);
1976 OUTREG(OV0_BASE_ADDR, 0);
1977 #endif
1978 mdelay(100);
1979
1980 /* Restore display settings */
1981 OUTREG(CRTC_GEN_CNTL, save_crtc_gen_cntl);
1982 OUTREG(CRTC_EXT_CNTL, save_crtc_ext_cntl);
1983 if (rinfo->has_CRTC2)
1984 OUTREG(CRTC2_GEN_CNTL, save_crtc2_gen_cntl);
1985
1986 RTRACE("aper_base: %08x MC_FB_LOC to: %08x, MC_AGP_LOC to: %08x\n",
1987 aper_base,
1988 ((aper_base + aper_size - 1) & 0xffff0000) | (aper_base >> 16),
1989 0xffff0000 | (agp_base >> 16));
1990 }
1991 #endif /* CONFIG_PPC_OF */
1992
1993
1994 static void radeon_identify_vram(struct radeonfb_info *rinfo)
1995 {
1996 u32 tmp;
1997
1998 /* framebuffer size */
1999 if ((rinfo->family == CHIP_FAMILY_RS100) ||
2000 (rinfo->family == CHIP_FAMILY_RS200) ||
2001 (rinfo->family == CHIP_FAMILY_RS300) ||
2002 (rinfo->family == CHIP_FAMILY_RS480) ) {
2003 u32 tom = INREG(NB_TOM);
2004 tmp = ((((tom >> 16) - (tom & 0xffff) + 1) << 6) * 1024);
2005
2006 radeon_fifo_wait(6);
2007 OUTREG(MC_FB_LOCATION, tom);
2008 OUTREG(DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);
2009 OUTREG(CRTC2_DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);
2010 OUTREG(OV0_BASE_ADDR, (tom & 0xffff) << 16);
2011
2012 /* This is supposed to fix the crtc2 noise problem. */
2013 OUTREG(GRPH2_BUFFER_CNTL, INREG(GRPH2_BUFFER_CNTL) & ~0x7f0000);
2014
2015 if ((rinfo->family == CHIP_FAMILY_RS100) ||
2016 (rinfo->family == CHIP_FAMILY_RS200)) {
2017 /* This is to workaround the asic bug for RMX, some versions
2018 of BIOS dosen't have this register initialized correctly.
2019 */
2020 OUTREGP(CRTC_MORE_CNTL, CRTC_H_CUTOFF_ACTIVE_EN,
2021 ~CRTC_H_CUTOFF_ACTIVE_EN);
2022 }
2023 } else {
2024 tmp = INREG(CONFIG_MEMSIZE);
2025 }
2026
2027 /* mem size is bits [28:0], mask off the rest */
2028 rinfo->video_ram = tmp & CONFIG_MEMSIZE_MASK;
2029
2030 /*
2031 * Hack to get around some busted production M6's
2032 * reporting no ram
2033 */
2034 if (rinfo->video_ram == 0) {
2035 switch (rinfo->pdev->device) {
2036 case PCI_CHIP_RADEON_LY:
2037 case PCI_CHIP_RADEON_LZ:
2038 rinfo->video_ram = 8192 * 1024;
2039 break;
2040 default:
2041 break;
2042 }
2043 }
2044
2045
2046 /*
2047 * Now try to identify VRAM type
2048 */
2049 if (rinfo->is_IGP || (rinfo->family >= CHIP_FAMILY_R300) ||
2050 (INREG(MEM_SDRAM_MODE_REG) & (1<<30)))
2051 rinfo->vram_ddr = 1;
2052 else
2053 rinfo->vram_ddr = 0;
2054
2055 tmp = INREG(MEM_CNTL);
2056 if (IS_R300_VARIANT(rinfo)) {
2057 tmp &= R300_MEM_NUM_CHANNELS_MASK;
2058 switch (tmp) {
2059 case 0: rinfo->vram_width = 64; break;
2060 case 1: rinfo->vram_width = 128; break;
2061 case 2: rinfo->vram_width = 256; break;
2062 default: rinfo->vram_width = 128; break;
2063 }
2064 } else if ((rinfo->family == CHIP_FAMILY_RV100) ||
2065 (rinfo->family == CHIP_FAMILY_RS100) ||
2066 (rinfo->family == CHIP_FAMILY_RS200)){
2067 if (tmp & RV100_MEM_HALF_MODE)
2068 rinfo->vram_width = 32;
2069 else
2070 rinfo->vram_width = 64;
2071 } else {
2072 if (tmp & MEM_NUM_CHANNELS_MASK)
2073 rinfo->vram_width = 128;
2074 else
2075 rinfo->vram_width = 64;
2076 }
2077
2078 /* This may not be correct, as some cards can have half of channel disabled
2079 * ToDo: identify these cases
2080 */
2081
2082 RTRACE("radeonfb (%s): Found %ldk of %s %d bits wide videoram\n",
2083 pci_name(rinfo->pdev),
2084 rinfo->video_ram / 1024,
2085 rinfo->vram_ddr ? "DDR" : "SDRAM",
2086 rinfo->vram_width);
2087 }
2088
2089 /*
2090 * Sysfs
2091 */
2092
2093 static ssize_t radeon_show_one_edid(char *buf, loff_t off, size_t count, const u8 *edid)
2094 {
2095 if (off > EDID_LENGTH)
2096 return 0;
2097
2098 if (off + count > EDID_LENGTH)
2099 count = EDID_LENGTH - off;
2100
2101 memcpy(buf, edid + off, count);
2102
2103 return count;
2104 }
2105
2106
2107 static ssize_t radeon_show_edid1(struct kobject *kobj,
2108 struct bin_attribute *bin_attr,
2109 char *buf, loff_t off, size_t count)
2110 {
2111 struct device *dev = container_of(kobj, struct device, kobj);
2112 struct pci_dev *pdev = to_pci_dev(dev);
2113 struct fb_info *info = pci_get_drvdata(pdev);
2114 struct radeonfb_info *rinfo = info->par;
2115
2116 return radeon_show_one_edid(buf, off, count, rinfo->mon1_EDID);
2117 }
2118
2119
2120 static ssize_t radeon_show_edid2(struct kobject *kobj,
2121 struct bin_attribute *bin_attr,
2122 char *buf, loff_t off, size_t count)
2123 {
2124 struct device *dev = container_of(kobj, struct device, kobj);
2125 struct pci_dev *pdev = to_pci_dev(dev);
2126 struct fb_info *info = pci_get_drvdata(pdev);
2127 struct radeonfb_info *rinfo = info->par;
2128
2129 return radeon_show_one_edid(buf, off, count, rinfo->mon2_EDID);
2130 }
2131
2132 static struct bin_attribute edid1_attr = {
2133 .attr = {
2134 .name = "edid1",
2135 .mode = 0444,
2136 },
2137 .size = EDID_LENGTH,
2138 .read = radeon_show_edid1,
2139 };
2140
2141 static struct bin_attribute edid2_attr = {
2142 .attr = {
2143 .name = "edid2",
2144 .mode = 0444,
2145 },
2146 .size = EDID_LENGTH,
2147 .read = radeon_show_edid2,
2148 };
2149
2150
2151 static int __devinit radeonfb_pci_register (struct pci_dev *pdev,
2152 const struct pci_device_id *ent)
2153 {
2154 struct fb_info *info;
2155 struct radeonfb_info *rinfo;
2156 int ret;
2157
2158 RTRACE("radeonfb_pci_register BEGIN\n");
2159
2160 /* Enable device in PCI config */
2161 ret = pci_enable_device(pdev);
2162 if (ret < 0) {
2163 printk(KERN_ERR "radeonfb (%s): Cannot enable PCI device\n",
2164 pci_name(pdev));
2165 goto err_out;
2166 }
2167
2168 info = framebuffer_alloc(sizeof(struct radeonfb_info), &pdev->dev);
2169 if (!info) {
2170 printk (KERN_ERR "radeonfb (%s): could not allocate memory\n",
2171 pci_name(pdev));
2172 ret = -ENOMEM;
2173 goto err_disable;
2174 }
2175 rinfo = info->par;
2176 rinfo->info = info;
2177 rinfo->pdev = pdev;
2178
2179 spin_lock_init(&rinfo->reg_lock);
2180 init_timer(&rinfo->lvds_timer);
2181 rinfo->lvds_timer.function = radeon_lvds_timer_func;
2182 rinfo->lvds_timer.data = (unsigned long)rinfo;
2183
2184 strcpy(rinfo->name, "ATI Radeon XX ");
2185 rinfo->name[11] = ent->device >> 8;
2186 rinfo->name[12] = ent->device & 0xFF;
2187 rinfo->family = ent->driver_data & CHIP_FAMILY_MASK;
2188 rinfo->chipset = pdev->device;
2189 rinfo->has_CRTC2 = (ent->driver_data & CHIP_HAS_CRTC2) != 0;
2190 rinfo->is_mobility = (ent->driver_data & CHIP_IS_MOBILITY) != 0;
2191 rinfo->is_IGP = (ent->driver_data & CHIP_IS_IGP) != 0;
2192
2193 /* Set base addrs */
2194 rinfo->fb_base_phys = pci_resource_start (pdev, 0);
2195 rinfo->mmio_base_phys = pci_resource_start (pdev, 2);
2196
2197 /* request the mem regions */
2198 ret = pci_request_region(pdev, 0, "radeonfb framebuffer");
2199 if (ret < 0) {
2200 printk( KERN_ERR "radeonfb (%s): cannot request region 0.\n",
2201 pci_name(rinfo->pdev));
2202 goto err_release_fb;
2203 }
2204
2205 ret = pci_request_region(pdev, 2, "radeonfb mmio");
2206 if (ret < 0) {
2207 printk( KERN_ERR "radeonfb (%s): cannot request region 2.\n",
2208 pci_name(rinfo->pdev));
2209 goto err_release_pci0;
2210 }
2211
2212 /* map the regions */
2213 rinfo->mmio_base = ioremap(rinfo->mmio_base_phys, RADEON_REGSIZE);
2214 if (!rinfo->mmio_base) {
2215 printk(KERN_ERR "radeonfb (%s): cannot map MMIO\n",
2216 pci_name(rinfo->pdev));
2217 ret = -EIO;
2218 goto err_release_pci2;
2219 }
2220
2221 rinfo->fb_local_base = INREG(MC_FB_LOCATION) << 16;
2222
2223 /*
2224 * Check for errata
2225 */
2226 rinfo->errata = 0;
2227 if (rinfo->family == CHIP_FAMILY_R300 &&
2228 (INREG(CONFIG_CNTL) & CFG_ATI_REV_ID_MASK)
2229 == CFG_ATI_REV_A11)
2230 rinfo->errata |= CHIP_ERRATA_R300_CG;
2231
2232 if (rinfo->family == CHIP_FAMILY_RV200 ||
2233 rinfo->family == CHIP_FAMILY_RS200)
2234 rinfo->errata |= CHIP_ERRATA_PLL_DUMMYREADS;
2235
2236 if (rinfo->family == CHIP_FAMILY_RV100 ||
2237 rinfo->family == CHIP_FAMILY_RS100 ||
2238 rinfo->family == CHIP_FAMILY_RS200)
2239 rinfo->errata |= CHIP_ERRATA_PLL_DELAY;
2240
2241 #if defined(CONFIG_PPC_OF) || defined(CONFIG_SPARC)
2242 /* On PPC, we obtain the OF device-node pointer to the firmware
2243 * data for this chip
2244 */
2245 rinfo->of_node = pci_device_to_OF_node(pdev);
2246 if (rinfo->of_node == NULL)
2247 printk(KERN_WARNING "radeonfb (%s): Cannot match card to OF node !\n",
2248 pci_name(rinfo->pdev));
2249
2250 #endif /* CONFIG_PPC_OF || CONFIG_SPARC */
2251 #ifdef CONFIG_PPC_OF
2252 /* On PPC, the firmware sets up a memory mapping that tends
2253 * to cause lockups when enabling the engine. We reconfigure
2254 * the card internal memory mappings properly
2255 */
2256 fixup_memory_mappings(rinfo);
2257 #endif /* CONFIG_PPC_OF */
2258
2259 /* Get VRAM size and type */
2260 radeon_identify_vram(rinfo);
2261
2262 rinfo->mapped_vram = min_t(unsigned long, MAX_MAPPED_VRAM, rinfo->video_ram);
2263
2264 do {
2265 rinfo->fb_base = ioremap (rinfo->fb_base_phys,
2266 rinfo->mapped_vram);
2267 } while ( rinfo->fb_base == 0 &&
2268 ((rinfo->mapped_vram /=2) >= MIN_MAPPED_VRAM) );
2269
2270 if (rinfo->fb_base == NULL) {
2271 printk (KERN_ERR "radeonfb (%s): cannot map FB\n",
2272 pci_name(rinfo->pdev));
2273 ret = -EIO;
2274 goto err_unmap_rom;
2275 }
2276
2277 RTRACE("radeonfb (%s): mapped %ldk videoram\n", pci_name(rinfo->pdev),
2278 rinfo->mapped_vram/1024);
2279
2280 /*
2281 * Map the BIOS ROM if any and retrieve PLL parameters from
2282 * the BIOS. We skip that on mobility chips as the real panel
2283 * values we need aren't in the ROM but in the BIOS image in
2284 * memory. This is definitely not the best meacnism though,
2285 * we really need the arch code to tell us which is the "primary"
2286 * video adapter to use the memory image (or better, the arch
2287 * should provide us a copy of the BIOS image to shield us from
2288 * archs who would store that elsewhere and/or could initialize
2289 * more than one adapter during boot).
2290 */
2291 if (!rinfo->is_mobility)
2292 radeon_map_ROM(rinfo, pdev);
2293
2294 /*
2295 * On x86, the primary display on laptop may have it's BIOS
2296 * ROM elsewhere, try to locate it at the legacy memory hole.
2297 * We probably need to make sure this is the primary display,
2298 * but that is difficult without some arch support.
2299 */
2300 #ifdef CONFIG_X86
2301 if (rinfo->bios_seg == NULL)
2302 radeon_find_mem_vbios(rinfo);
2303 #endif
2304
2305 /* If both above failed, try the BIOS ROM again for mobility
2306 * chips
2307 */
2308 if (rinfo->bios_seg == NULL && rinfo->is_mobility)
2309 radeon_map_ROM(rinfo, pdev);
2310
2311 /* Get informations about the board's PLL */
2312 radeon_get_pllinfo(rinfo);
2313
2314 #ifdef CONFIG_FB_RADEON_I2C
2315 /* Register I2C bus */
2316 radeon_create_i2c_busses(rinfo);
2317 #endif
2318
2319 /* set all the vital stuff */
2320 radeon_set_fbinfo (rinfo);
2321
2322 /* Probe screen types */
2323 radeon_probe_screens(rinfo, monitor_layout, ignore_edid);
2324
2325 /* Build mode list, check out panel native model */
2326 radeon_check_modes(rinfo, mode_option);
2327
2328 /* Register some sysfs stuff (should be done better) */
2329 if (rinfo->mon1_EDID)
2330 sysfs_create_bin_file(&rinfo->pdev->dev.kobj, &edid1_attr);
2331 if (rinfo->mon2_EDID)
2332 sysfs_create_bin_file(&rinfo->pdev->dev.kobj, &edid2_attr);
2333
2334 /* save current mode regs before we switch into the new one
2335 * so we can restore this upon __exit
2336 */
2337 radeon_save_state (rinfo, &rinfo->init_state);
2338 memcpy(&rinfo->state, &rinfo->init_state, sizeof(struct radeon_regs));
2339
2340 /* Setup Power Management capabilities */
2341 if (default_dynclk < -1) {
2342 /* -2 is special: means ON on mobility chips and do not
2343 * change on others
2344 */
2345 radeonfb_pm_init(rinfo, rinfo->is_mobility ? 1 : -1, ignore_devlist, force_sleep);
2346 } else
2347 radeonfb_pm_init(rinfo, default_dynclk, ignore_devlist, force_sleep);
2348
2349 pci_set_drvdata(pdev, info);
2350
2351 /* Register with fbdev layer */
2352 ret = register_framebuffer(info);
2353 if (ret < 0) {
2354 printk (KERN_ERR "radeonfb (%s): could not register framebuffer\n",
2355 pci_name(rinfo->pdev));
2356 goto err_unmap_fb;
2357 }
2358
2359 #ifdef CONFIG_MTRR
2360 rinfo->mtrr_hdl = nomtrr ? -1 : mtrr_add(rinfo->fb_base_phys,
2361 rinfo->video_ram,
2362 MTRR_TYPE_WRCOMB, 1);
2363 #endif
2364
2365 if (backlight)
2366 radeonfb_bl_init(rinfo);
2367
2368 printk ("radeonfb (%s): %s\n", pci_name(rinfo->pdev), rinfo->name);
2369
2370 if (rinfo->bios_seg)
2371 radeon_unmap_ROM(rinfo, pdev);
2372 RTRACE("radeonfb_pci_register END\n");
2373
2374 return 0;
2375 err_unmap_fb:
2376 iounmap(rinfo->fb_base);
2377 err_unmap_rom:
2378 kfree(rinfo->mon1_EDID);
2379 kfree(rinfo->mon2_EDID);
2380 if (rinfo->mon1_modedb)
2381 fb_destroy_modedb(rinfo->mon1_modedb);
2382 fb_dealloc_cmap(&info->cmap);
2383 #ifdef CONFIG_FB_RADEON_I2C
2384 radeon_delete_i2c_busses(rinfo);
2385 #endif
2386 if (rinfo->bios_seg)
2387 radeon_unmap_ROM(rinfo, pdev);
2388 iounmap(rinfo->mmio_base);
2389 err_release_pci2:
2390 pci_release_region(pdev, 2);
2391 err_release_pci0:
2392 pci_release_region(pdev, 0);
2393 err_release_fb:
2394 framebuffer_release(info);
2395 err_disable:
2396 err_out:
2397 return ret;
2398 }
2399
2400
2401
2402 static void __devexit radeonfb_pci_unregister (struct pci_dev *pdev)
2403 {
2404 struct fb_info *info = pci_get_drvdata(pdev);
2405 struct radeonfb_info *rinfo = info->par;
2406
2407 if (!rinfo)
2408 return;
2409
2410 radeonfb_pm_exit(rinfo);
2411
2412 if (rinfo->mon1_EDID)
2413 sysfs_remove_bin_file(&rinfo->pdev->dev.kobj, &edid1_attr);
2414 if (rinfo->mon2_EDID)
2415 sysfs_remove_bin_file(&rinfo->pdev->dev.kobj, &edid2_attr);
2416
2417 #if 0
2418 /* restore original state
2419 *
2420 * Doesn't quite work yet, I suspect if we come from a legacy
2421 * VGA mode (or worse, text mode), we need to do some VGA black
2422 * magic here that I know nothing about. --BenH
2423 */
2424 radeon_write_mode (rinfo, &rinfo->init_state, 1);
2425 #endif
2426
2427 del_timer_sync(&rinfo->lvds_timer);
2428
2429 #ifdef CONFIG_MTRR
2430 if (rinfo->mtrr_hdl >= 0)
2431 mtrr_del(rinfo->mtrr_hdl, 0, 0);
2432 #endif
2433
2434 unregister_framebuffer(info);
2435
2436 radeonfb_bl_exit(rinfo);
2437
2438 iounmap(rinfo->mmio_base);
2439 iounmap(rinfo->fb_base);
2440
2441 pci_release_region(pdev, 2);
2442 pci_release_region(pdev, 0);
2443
2444 kfree(rinfo->mon1_EDID);
2445 kfree(rinfo->mon2_EDID);
2446 if (rinfo->mon1_modedb)
2447 fb_destroy_modedb(rinfo->mon1_modedb);
2448 #ifdef CONFIG_FB_RADEON_I2C
2449 radeon_delete_i2c_busses(rinfo);
2450 #endif
2451 fb_dealloc_cmap(&info->cmap);
2452 framebuffer_release(info);
2453 }
2454
2455
2456 static struct pci_driver radeonfb_driver = {
2457 .name = "radeonfb",
2458 .id_table = radeonfb_pci_table,
2459 .probe = radeonfb_pci_register,
2460 .remove = __devexit_p(radeonfb_pci_unregister),
2461 #ifdef CONFIG_PM
2462 .suspend = radeonfb_pci_suspend,
2463 .resume = radeonfb_pci_resume,
2464 #endif /* CONFIG_PM */
2465 };
2466
2467 #ifndef MODULE
2468 static int __init radeonfb_setup (char *options)
2469 {
2470 char *this_opt;
2471
2472 if (!options || !*options)
2473 return 0;
2474
2475 while ((this_opt = strsep (&options, ",")) != NULL) {
2476 if (!*this_opt)
2477 continue;
2478
2479 if (!strncmp(this_opt, "noaccel", 7)) {
2480 noaccel = 1;
2481 } else if (!strncmp(this_opt, "mirror", 6)) {
2482 mirror = 1;
2483 } else if (!strncmp(this_opt, "force_dfp", 9)) {
2484 force_dfp = 1;
2485 } else if (!strncmp(this_opt, "panel_yres:", 11)) {
2486 panel_yres = simple_strtoul((this_opt+11), NULL, 0);
2487 } else if (!strncmp(this_opt, "backlight:", 10)) {
2488 backlight = simple_strtoul(this_opt+10, NULL, 0);
2489 #ifdef CONFIG_MTRR
2490 } else if (!strncmp(this_opt, "nomtrr", 6)) {
2491 nomtrr = 1;
2492 #endif
2493 } else if (!strncmp(this_opt, "nomodeset", 9)) {
2494 nomodeset = 1;
2495 } else if (!strncmp(this_opt, "force_measure_pll", 17)) {
2496 force_measure_pll = 1;
2497 } else if (!strncmp(this_opt, "ignore_edid", 11)) {
2498 ignore_edid = 1;
2499 #if defined(CONFIG_PM) && defined(CONFIG_X86)
2500 } else if (!strncmp(this_opt, "force_sleep", 11)) {
2501 force_sleep = 1;
2502 } else if (!strncmp(this_opt, "ignore_devlist", 14)) {
2503 ignore_devlist = 1;
2504 #endif
2505 } else
2506 mode_option = this_opt;
2507 }
2508 return 0;
2509 }
2510 #endif /* MODULE */
2511
2512 static int __init radeonfb_init (void)
2513 {
2514 #ifndef MODULE
2515 char *option = NULL;
2516
2517 if (fb_get_options("radeonfb", &option))
2518 return -ENODEV;
2519 radeonfb_setup(option);
2520 #endif
2521 return pci_register_driver (&radeonfb_driver);
2522 }
2523
2524
2525 static void __exit radeonfb_exit (void)
2526 {
2527 pci_unregister_driver (&radeonfb_driver);
2528 }
2529
2530 module_init(radeonfb_init);
2531 module_exit(radeonfb_exit);
2532
2533 MODULE_AUTHOR("Ani Joshi");
2534 MODULE_DESCRIPTION("framebuffer driver for ATI Radeon chipset");
2535 MODULE_LICENSE("GPL");
2536 module_param(noaccel, bool, 0);
2537 module_param(default_dynclk, int, 0);
2538 MODULE_PARM_DESC(default_dynclk, "int: -2=enable on mobility only,-1=do not change,0=off,1=on");
2539 MODULE_PARM_DESC(noaccel, "bool: disable acceleration");
2540 module_param(nomodeset, bool, 0);
2541 MODULE_PARM_DESC(nomodeset, "bool: disable actual setting of video mode");
2542 module_param(mirror, bool, 0);
2543 MODULE_PARM_DESC(mirror, "bool: mirror the display to both monitors");
2544 module_param(force_dfp, bool, 0);
2545 MODULE_PARM_DESC(force_dfp, "bool: force display to dfp");
2546 module_param(ignore_edid, bool, 0);
2547 MODULE_PARM_DESC(ignore_edid, "bool: Ignore EDID data when doing DDC probe");
2548 module_param(monitor_layout, charp, 0);
2549 MODULE_PARM_DESC(monitor_layout, "Specify monitor mapping (like XFree86)");
2550 module_param(force_measure_pll, bool, 0);
2551 MODULE_PARM_DESC(force_measure_pll, "Force measurement of PLL (debug)");
2552 #ifdef CONFIG_MTRR
2553 module_param(nomtrr, bool, 0);
2554 MODULE_PARM_DESC(nomtrr, "bool: disable use of MTRR registers");
2555 #endif
2556 module_param(panel_yres, int, 0);
2557 MODULE_PARM_DESC(panel_yres, "int: set panel yres");
2558 module_param(mode_option, charp, 0);
2559 MODULE_PARM_DESC(mode_option, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");
2560 #if defined(CONFIG_PM) && defined(CONFIG_X86)
2561 module_param(force_sleep, bool, 0);
2562 MODULE_PARM_DESC(force_sleep, "bool: force D2 sleep mode on all hardware");
2563 module_param(ignore_devlist, bool, 0);
2564 MODULE_PARM_DESC(ignore_devlist, "bool: ignore workarounds for bugs in specific laptops");
2565 #endif
USB Experimental Work