2 * linux/drivers/video/s3c2410fb.c
3 * Copyright (c) Arnaud Patard, Ben Dooks
5 * This file is subject to the terms and conditions of the GNU General Public
6 * License. See the file COPYING in the main directory of this archive for
9 * S3C2410 LCD Controller Frame Buffer Driver
10 * based on skeletonfb.c, sa1100fb.c and others
13 * 2005-04-07: Arnaud Patard <arnaud.patard@rtp-net.org>
14 * - u32 state -> pm_message_t state
15 * - S3C2410_{VA,SZ}_LCD -> S3C24XX
17 * 2005-03-15: Arnaud Patard <arnaud.patard@rtp-net.org>
19 * - use readl/writel instead of __raw_writel/__raw_readl
21 * 2004-12-04: Arnaud Patard <arnaud.patard@rtp-net.org>
22 * - Added the possibility to set on or off the
24 * - Replaced 0 and 1 by on or off when reading the
27 * 2005-03-23: Ben Dooks <ben-linux@fluff.org>
28 * - added non 16bpp modes
29 * - updated platform information for range of x/y/bpp
30 * - add code to ensure palette is written correctly
31 * - add pixel clock divisor control
33 * 2004-11-11: Arnaud Patard <arnaud.patard@rtp-net.org>
34 * - Removed the use of currcon as it no more exist
35 * - Added LCD power sysfs interface
37 * 2004-11-03: Ben Dooks <ben-linux@fluff.org>
39 * - add suspend/resume support
40 * - s3c2410fb_setcolreg() not valid in >8bpp modes
41 * - removed last CONFIG_FB_S3C2410_FIXED
42 * - ensure lcd controller stopped before cleanup
43 * - added sysfs interface for backlight power
44 * - added mask for gpio configuration
45 * - ensured IRQs disabled during GPIO configuration
46 * - disable TPAL before enabling video
48 * 2004-09-20: Arnaud Patard <arnaud.patard@rtp-net.org>
49 * - Suppress command line options
51 * 2004-09-15: Arnaud Patard <arnaud.patard@rtp-net.org>
54 * 2004-09-07: Arnaud Patard <arnaud.patard@rtp-net.org>
55 * - Renamed from h1940fb.c to s3c2410fb.c
56 * - Add support for different devices
59 * 2004-09-05: Herbert Pötzl <herbert@13thfloor.at>
60 * - added clock (de-)allocation code
61 * - added fixem fbmem option
63 * 2004-07-27: Arnaud Patard <arnaud.patard@rtp-net.org>
65 * - added a forgotten return in h1940fb_init
67 * 2004-07-19: Herbert Pötzl <herbert@13thfloor.at>
68 * - code cleanup and extended debugging
70 * 2004-07-15: Arnaud Patard <arnaud.patard@rtp-net.org>
74 #include <linux/module.h>
75 #include <linux/kernel.h>
76 #include <linux/errno.h>
77 #include <linux/string.h>
79 #include <linux/slab.h>
80 #include <linux/delay.h>
82 #include <linux/init.h>
83 #include <linux/dma-mapping.h>
84 #include <linux/interrupt.h>
85 #include <linux/workqueue.h>
86 #include <linux/wait.h>
87 #include <linux/platform_device.h>
88 #include <linux/clk.h>
91 #include <asm/uaccess.h>
92 #include <asm/div64.h>
94 #include <asm/mach/map.h>
95 #include <asm/arch/regs-lcd.h>
96 #include <asm/arch/regs-gpio.h>
97 #include <asm/arch/fb.h>
100 #include <linux/pm.h>
103 #include "s3c2410fb.h"
106 static struct s3c2410fb_mach_info
*mach_info
;
108 /* Debugging stuff */
109 #ifdef CONFIG_FB_S3C2410_DEBUG
110 static int debug
= 1;
112 static int debug
= 0;
115 #define dprintk(msg...) if (debug) { printk(KERN_DEBUG "s3c2410fb: " msg); }
117 /* useful functions */
119 /* s3c2410fb_set_lcdaddr
121 * initialise lcd controller address pointers
124 static void s3c2410fb_set_lcdaddr(struct s3c2410fb_info
*fbi
)
126 struct fb_var_screeninfo
*var
= &fbi
->fb
->var
;
127 unsigned long saddr1
, saddr2
, saddr3
;
129 saddr1
= fbi
->fb
->fix
.smem_start
>> 1;
130 saddr2
= fbi
->fb
->fix
.smem_start
;
131 saddr2
+= (var
->xres
* var
->yres
* var
->bits_per_pixel
)/8;
134 saddr3
= S3C2410_OFFSIZE(0) | S3C2410_PAGEWIDTH((var
->xres
* var
->bits_per_pixel
/ 16) & 0x3ff);
136 dprintk("LCDSADDR1 = 0x%08lx\n", saddr1
);
137 dprintk("LCDSADDR2 = 0x%08lx\n", saddr2
);
138 dprintk("LCDSADDR3 = 0x%08lx\n", saddr3
);
140 writel(saddr1
, S3C2410_LCDSADDR1
);
141 writel(saddr2
, S3C2410_LCDSADDR2
);
142 writel(saddr3
, S3C2410_LCDSADDR3
);
145 /* s3c2410fb_calc_pixclk()
147 * calculate divisor for clk->pixclk
150 static unsigned int s3c2410fb_calc_pixclk(struct s3c2410fb_info
*fbi
,
151 unsigned long pixclk
)
153 unsigned long clk
= clk_get_rate(fbi
->clk
);
154 unsigned long long div
;
156 /* pixclk is in picoseoncds, our clock is in Hz
158 * Hz -> picoseconds is / 10^-12
161 div
= (unsigned long long)clk
* pixclk
;
162 do_div(div
,1000000UL);
163 do_div(div
,1000000UL);
165 dprintk("pixclk %ld, divisor is %ld\n", pixclk
, (long)div
);
170 * s3c2410fb_check_var():
171 * Get the video params out of 'var'. If a value doesn't fit, round it up,
172 * if it's too big, return -EINVAL.
175 static int s3c2410fb_check_var(struct fb_var_screeninfo
*var
,
176 struct fb_info
*info
)
178 struct s3c2410fb_info
*fbi
= info
->par
;
180 dprintk("check_var(var=%p, info=%p)\n", var
, info
);
182 /* validate x/y resolution */
184 if (var
->yres
> fbi
->mach_info
->yres
.max
)
185 var
->yres
= fbi
->mach_info
->yres
.max
;
186 else if (var
->yres
< fbi
->mach_info
->yres
.min
)
187 var
->yres
= fbi
->mach_info
->yres
.min
;
189 if (var
->xres
> fbi
->mach_info
->xres
.max
)
190 var
->yres
= fbi
->mach_info
->xres
.max
;
191 else if (var
->xres
< fbi
->mach_info
->xres
.min
)
192 var
->xres
= fbi
->mach_info
->xres
.min
;
196 if (var
->bits_per_pixel
> fbi
->mach_info
->bpp
.max
)
197 var
->bits_per_pixel
= fbi
->mach_info
->bpp
.max
;
198 else if (var
->bits_per_pixel
< fbi
->mach_info
->bpp
.min
)
199 var
->bits_per_pixel
= fbi
->mach_info
->bpp
.min
;
201 /* set r/g/b positions */
202 switch (var
->bits_per_pixel
) {
207 var
->red
.length
= var
->bits_per_pixel
;
208 var
->green
= var
->red
;
209 var
->blue
= var
->red
;
210 var
->transp
.offset
= 0;
211 var
->transp
.length
= 0;
214 if ( fbi
->mach_info
->type
!= S3C2410_LCDCON1_TFT
) {
218 var
->green
.length
= 3;
219 var
->green
.offset
= 2;
220 var
->blue
.length
= 2;
221 var
->blue
.offset
= 0;
222 var
->transp
.length
= 0;
225 var
->red
.length
= var
->bits_per_pixel
;
226 var
->green
= var
->red
;
227 var
->blue
= var
->red
;
228 var
->transp
.offset
= 0;
229 var
->transp
.length
= 0;
236 var
->green
.length
= 4;
237 var
->green
.offset
= 4;
238 var
->blue
.length
= 4;
239 var
->blue
.offset
= 0;
240 var
->transp
.length
= 0;
245 if (fbi
->regs
.lcdcon5
& S3C2410_LCDCON5_FRM565
) {
246 /* 16 bpp, 565 format */
247 var
->red
.offset
= 11;
248 var
->green
.offset
= 5;
249 var
->blue
.offset
= 0;
251 var
->green
.length
= 6;
252 var
->blue
.length
= 5;
253 var
->transp
.length
= 0;
255 /* 16 bpp, 5551 format */
256 var
->red
.offset
= 11;
257 var
->green
.offset
= 6;
258 var
->blue
.offset
= 1;
260 var
->green
.length
= 5;
261 var
->blue
.length
= 5;
262 var
->transp
.length
= 0;
268 var
->red
.offset
= 16;
269 var
->green
.length
= 8;
270 var
->green
.offset
= 8;
271 var
->blue
.length
= 8;
272 var
->blue
.offset
= 0;
273 var
->transp
.length
= 0;
282 /* s3c2410fb_activate_var
284 * activate (set) the controller from the given framebuffer
288 static void s3c2410fb_activate_var(struct s3c2410fb_info
*fbi
,
289 struct fb_var_screeninfo
*var
)
293 fbi
->regs
.lcdcon1
&= ~S3C2410_LCDCON1_MODEMASK
;
294 fbi
->regs
.lcdcon1
&= ~S3C2410_LCDCON1_TFT
;
296 dprintk("%s: var->xres = %d\n", __FUNCTION__
, var
->xres
);
297 dprintk("%s: var->yres = %d\n", __FUNCTION__
, var
->yres
);
298 dprintk("%s: var->bpp = %d\n", __FUNCTION__
, var
->bits_per_pixel
);
300 fbi
->regs
.lcdcon1
|= fbi
->mach_info
->type
;
302 if (fbi
->mach_info
->type
== S3C2410_LCDCON1_TFT
)
303 switch (var
->bits_per_pixel
) {
305 fbi
->regs
.lcdcon1
|= S3C2410_LCDCON1_TFT1BPP
;
308 fbi
->regs
.lcdcon1
|= S3C2410_LCDCON1_TFT2BPP
;
311 fbi
->regs
.lcdcon1
|= S3C2410_LCDCON1_TFT4BPP
;
314 fbi
->regs
.lcdcon1
|= S3C2410_LCDCON1_TFT8BPP
;
317 fbi
->regs
.lcdcon1
|= S3C2410_LCDCON1_TFT16BPP
;
321 /* invalid pixel depth */
322 dev_err(fbi
->dev
, "invalid bpp %d\n", var
->bits_per_pixel
);
325 switch (var
->bits_per_pixel
) {
327 fbi
->regs
.lcdcon1
|= S3C2410_LCDCON1_STN1BPP
;
330 fbi
->regs
.lcdcon1
|= S3C2410_LCDCON1_STN2GREY
;
333 fbi
->regs
.lcdcon1
|= S3C2410_LCDCON1_STN4GREY
;
336 fbi
->regs
.lcdcon1
|= S3C2410_LCDCON1_STN8BPP
;
339 fbi
->regs
.lcdcon1
|= S3C2410_LCDCON1_STN12BPP
;
343 /* invalid pixel depth */
344 dev_err(fbi
->dev
, "invalid bpp %d\n", var
->bits_per_pixel
);
347 /* check to see if we need to update sync/borders */
349 if (!fbi
->mach_info
->fixed_syncs
) {
350 dprintk("setting vert: up=%d, low=%d, sync=%d\n",
351 var
->upper_margin
, var
->lower_margin
,
354 dprintk("setting horz: lft=%d, rt=%d, sync=%d\n",
355 var
->left_margin
, var
->right_margin
,
359 S3C2410_LCDCON2_VBPD(var
->upper_margin
- 1) |
360 S3C2410_LCDCON2_VFPD(var
->lower_margin
- 1) |
361 S3C2410_LCDCON2_VSPW(var
->vsync_len
- 1);
364 S3C2410_LCDCON3_HBPD(var
->right_margin
- 1) |
365 S3C2410_LCDCON3_HFPD(var
->left_margin
- 1);
367 fbi
->regs
.lcdcon4
&= ~S3C2410_LCDCON4_HSPW(0xff);
368 fbi
->regs
.lcdcon4
|= S3C2410_LCDCON4_HSPW(var
->hsync_len
- 1);
371 /* update X/Y info */
373 fbi
->regs
.lcdcon2
&= ~S3C2410_LCDCON2_LINEVAL(0x3ff);
374 fbi
->regs
.lcdcon2
|= S3C2410_LCDCON2_LINEVAL(var
->yres
- 1);
376 switch(fbi
->mach_info
->type
) {
377 case S3C2410_LCDCON1_DSCAN4
:
378 case S3C2410_LCDCON1_STN8
:
381 case S3C2410_LCDCON1_STN4
:
385 case S3C2410_LCDCON1_TFT
:
391 /* Special cases : STN color displays */
392 if ( ((fbi
->regs
.lcdcon1
& S3C2410_LCDCON1_MODEMASK
) == S3C2410_LCDCON1_STN8BPP
) \
393 || ((fbi
->regs
.lcdcon1
& S3C2410_LCDCON1_MODEMASK
) == S3C2410_LCDCON1_STN12BPP
) ) {
398 fbi
->regs
.lcdcon3
&= ~S3C2410_LCDCON3_HOZVAL(0x7ff);
399 fbi
->regs
.lcdcon3
|= S3C2410_LCDCON3_HOZVAL(hs
- 1);
401 if (var
->pixclock
> 0) {
402 int clkdiv
= s3c2410fb_calc_pixclk(fbi
, var
->pixclock
);
404 if (fbi
->mach_info
->type
== S3C2410_LCDCON1_TFT
) {
405 clkdiv
= (clkdiv
/ 2) -1;
410 clkdiv
= (clkdiv
/ 2);
415 fbi
->regs
.lcdcon1
&= ~S3C2410_LCDCON1_CLKVAL(0x3ff);
416 fbi
->regs
.lcdcon1
|= S3C2410_LCDCON1_CLKVAL(clkdiv
);
419 /* write new registers */
421 dprintk("new register set:\n");
422 dprintk("lcdcon[1] = 0x%08lx\n", fbi
->regs
.lcdcon1
);
423 dprintk("lcdcon[2] = 0x%08lx\n", fbi
->regs
.lcdcon2
);
424 dprintk("lcdcon[3] = 0x%08lx\n", fbi
->regs
.lcdcon3
);
425 dprintk("lcdcon[4] = 0x%08lx\n", fbi
->regs
.lcdcon4
);
426 dprintk("lcdcon[5] = 0x%08lx\n", fbi
->regs
.lcdcon5
);
428 writel(fbi
->regs
.lcdcon1
& ~S3C2410_LCDCON1_ENVID
, S3C2410_LCDCON1
);
429 writel(fbi
->regs
.lcdcon2
, S3C2410_LCDCON2
);
430 writel(fbi
->regs
.lcdcon3
, S3C2410_LCDCON3
);
431 writel(fbi
->regs
.lcdcon4
, S3C2410_LCDCON4
);
432 writel(fbi
->regs
.lcdcon5
, S3C2410_LCDCON5
);
434 /* set lcd address pointers */
435 s3c2410fb_set_lcdaddr(fbi
);
437 writel(fbi
->regs
.lcdcon1
, S3C2410_LCDCON1
);
442 * s3c2410fb_set_par - Optional function. Alters the hardware state.
443 * @info: frame buffer structure that represents a single frame buffer
446 static int s3c2410fb_set_par(struct fb_info
*info
)
448 struct s3c2410fb_info
*fbi
= info
->par
;
449 struct fb_var_screeninfo
*var
= &info
->var
;
451 switch (var
->bits_per_pixel
)
454 fbi
->fb
->fix
.visual
= FB_VISUAL_TRUECOLOR
;
457 fbi
->fb
->fix
.visual
= FB_VISUAL_MONO01
;
460 fbi
->fb
->fix
.visual
= FB_VISUAL_PSEUDOCOLOR
;
464 fbi
->fb
->fix
.line_length
= (var
->width
*var
->bits_per_pixel
)/8;
466 /* activate this new configuration */
468 s3c2410fb_activate_var(fbi
, var
);
472 static void schedule_palette_update(struct s3c2410fb_info
*fbi
,
473 unsigned int regno
, unsigned int val
)
477 void __iomem
*regs
= fbi
->io
;
479 local_irq_save(flags
);
481 fbi
->palette_buffer
[regno
] = val
;
483 if (!fbi
->palette_ready
) {
484 fbi
->palette_ready
= 1;
487 irqen
= readl(regs
+ S3C2410_LCDINTMSK
);
488 irqen
&= ~S3C2410_LCDINT_FRSYNC
;
489 writel(irqen
, regs
+ S3C2410_LCDINTMSK
);
492 local_irq_restore(flags
);
496 static inline unsigned int chan_to_field(unsigned int chan
, struct fb_bitfield
*bf
)
499 chan
>>= 16 - bf
->length
;
500 return chan
<< bf
->offset
;
503 static int s3c2410fb_setcolreg(unsigned regno
,
504 unsigned red
, unsigned green
, unsigned blue
,
505 unsigned transp
, struct fb_info
*info
)
507 struct s3c2410fb_info
*fbi
= info
->par
;
510 /* dprintk("setcol: regno=%d, rgb=%d,%d,%d\n", regno, red, green, blue); */
512 switch (fbi
->fb
->fix
.visual
) {
513 case FB_VISUAL_TRUECOLOR
:
514 /* true-colour, use pseuo-palette */
517 u32
*pal
= fbi
->fb
->pseudo_palette
;
519 val
= chan_to_field(red
, &fbi
->fb
->var
.red
);
520 val
|= chan_to_field(green
, &fbi
->fb
->var
.green
);
521 val
|= chan_to_field(blue
, &fbi
->fb
->var
.blue
);
527 case FB_VISUAL_PSEUDOCOLOR
:
529 /* currently assume RGB 5-6-5 mode */
531 val
= ((red
>> 0) & 0xf800);
532 val
|= ((green
>> 5) & 0x07e0);
533 val
|= ((blue
>> 11) & 0x001f);
535 writel(val
, S3C2410_TFTPAL(regno
));
536 schedule_palette_update(fbi
, regno
, val
);
542 return 1; /* unknown type */
551 * @blank_mode: the blank mode we want.
552 * @info: frame buffer structure that represents a single frame buffer
554 * Blank the screen if blank_mode != 0, else unblank. Return 0 if
555 * blanking succeeded, != 0 if un-/blanking failed due to e.g. a
556 * video mode which doesn't support it. Implements VESA suspend
557 * and powerdown modes on hardware that supports disabling hsync/vsync:
558 * blank_mode == 2: suspend vsync
559 * blank_mode == 3: suspend hsync
560 * blank_mode == 4: powerdown
562 * Returns negative errno on error, or zero on success.
565 static int s3c2410fb_blank(int blank_mode
, struct fb_info
*info
)
567 dprintk("blank(mode=%d, info=%p)\n", blank_mode
, info
);
569 if (mach_info
== NULL
)
572 if (blank_mode
== FB_BLANK_UNBLANK
)
573 writel(0x0, S3C2410_TPAL
);
575 dprintk("setting TPAL to output 0x000000\n");
576 writel(S3C2410_TPAL_EN
, S3C2410_TPAL
);
582 static int s3c2410fb_debug_show(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
584 return snprintf(buf
, PAGE_SIZE
, "%s\n", debug
? "on" : "off");
586 static int s3c2410fb_debug_store(struct device
*dev
, struct device_attribute
*attr
,
587 const char *buf
, size_t len
)
589 if (mach_info
== NULL
)
595 if (strnicmp(buf
, "on", 2) == 0 ||
596 strnicmp(buf
, "1", 1) == 0) {
598 printk(KERN_DEBUG
"s3c2410fb: Debug On");
599 } else if (strnicmp(buf
, "off", 3) == 0 ||
600 strnicmp(buf
, "0", 1) == 0) {
602 printk(KERN_DEBUG
"s3c2410fb: Debug Off");
611 static DEVICE_ATTR(debug
, 0666,
612 s3c2410fb_debug_show
,
613 s3c2410fb_debug_store
);
615 static struct fb_ops s3c2410fb_ops
= {
616 .owner
= THIS_MODULE
,
617 .fb_check_var
= s3c2410fb_check_var
,
618 .fb_set_par
= s3c2410fb_set_par
,
619 .fb_blank
= s3c2410fb_blank
,
620 .fb_setcolreg
= s3c2410fb_setcolreg
,
621 .fb_fillrect
= cfb_fillrect
,
622 .fb_copyarea
= cfb_copyarea
,
623 .fb_imageblit
= cfb_imageblit
,
628 * s3c2410fb_map_video_memory():
629 * Allocates the DRAM memory for the frame buffer. This buffer is
630 * remapped into a non-cached, non-buffered, memory region to
631 * allow palette and pixel writes to occur without flushing the
632 * cache. Once this area is remapped, all virtual memory
633 * access to the video memory should occur at the new region.
635 static int __init
s3c2410fb_map_video_memory(struct s3c2410fb_info
*fbi
)
637 dprintk("map_video_memory(fbi=%p)\n", fbi
);
639 fbi
->map_size
= PAGE_ALIGN(fbi
->fb
->fix
.smem_len
+ PAGE_SIZE
);
640 fbi
->map_cpu
= dma_alloc_writecombine(fbi
->dev
, fbi
->map_size
,
641 &fbi
->map_dma
, GFP_KERNEL
);
643 fbi
->map_size
= fbi
->fb
->fix
.smem_len
;
646 /* prevent initial garbage on screen */
647 dprintk("map_video_memory: clear %p:%08x\n",
648 fbi
->map_cpu
, fbi
->map_size
);
649 memset(fbi
->map_cpu
, 0xf0, fbi
->map_size
);
651 fbi
->screen_dma
= fbi
->map_dma
;
652 fbi
->fb
->screen_base
= fbi
->map_cpu
;
653 fbi
->fb
->fix
.smem_start
= fbi
->screen_dma
;
655 dprintk("map_video_memory: dma=%08x cpu=%p size=%08x\n",
656 fbi
->map_dma
, fbi
->map_cpu
, fbi
->fb
->fix
.smem_len
);
659 return fbi
->map_cpu
? 0 : -ENOMEM
;
662 static inline void s3c2410fb_unmap_video_memory(struct s3c2410fb_info
*fbi
)
664 dma_free_writecombine(fbi
->dev
,fbi
->map_size
,fbi
->map_cpu
, fbi
->map_dma
);
667 static inline void modify_gpio(void __iomem
*reg
,
668 unsigned long set
, unsigned long mask
)
672 tmp
= readl(reg
) & ~mask
;
673 writel(tmp
| set
, reg
);
678 * s3c2410fb_init_registers - Initialise all LCD-related registers
681 static int s3c2410fb_init_registers(struct s3c2410fb_info
*fbi
)
684 void __iomem
*regs
= fbi
->io
;
686 /* Initialise LCD with values from haret */
688 local_irq_save(flags
);
690 /* modify the gpio(s) with interrupts set (bjd) */
692 modify_gpio(S3C2410_GPCUP
, mach_info
->gpcup
, mach_info
->gpcup_mask
);
693 modify_gpio(S3C2410_GPCCON
, mach_info
->gpccon
, mach_info
->gpccon_mask
);
694 modify_gpio(S3C2410_GPDUP
, mach_info
->gpdup
, mach_info
->gpdup_mask
);
695 modify_gpio(S3C2410_GPDCON
, mach_info
->gpdcon
, mach_info
->gpdcon_mask
);
697 local_irq_restore(flags
);
699 writel(fbi
->regs
.lcdcon1
, regs
+ S3C2410_LCDCON1
);
700 writel(fbi
->regs
.lcdcon2
, regs
+ S3C2410_LCDCON2
);
701 writel(fbi
->regs
.lcdcon3
, regs
+ S3C2410_LCDCON3
);
702 writel(fbi
->regs
.lcdcon4
, regs
+ S3C2410_LCDCON4
);
703 writel(fbi
->regs
.lcdcon5
, regs
+ S3C2410_LCDCON5
);
705 s3c2410fb_set_lcdaddr(fbi
);
707 dprintk("LPCSEL = 0x%08lx\n", mach_info
->lpcsel
);
708 writel(mach_info
->lpcsel
, regs
+ S3C2410_LPCSEL
);
710 dprintk("replacing TPAL %08x\n", readl(regs
+ S3C2410_TPAL
));
712 /* ensure temporary palette disabled */
713 writel(0x00, regs
+ S3C2410_TPAL
);
715 /* Enable video by setting the ENVID bit to 1 */
716 fbi
->regs
.lcdcon1
|= S3C2410_LCDCON1_ENVID
;
717 writel(fbi
->regs
.lcdcon1
, regs
+ S3C2410_LCDCON1
);
721 static void s3c2410fb_write_palette(struct s3c2410fb_info
*fbi
)
725 void __iomem
*regs
= fbi
->io
;
727 fbi
->palette_ready
= 0;
729 for (i
= 0; i
< 256; i
++) {
730 if ((ent
= fbi
->palette_buffer
[i
]) == PALETTE_BUFF_CLEAR
)
733 writel(ent
, regs
+ S3C2410_TFTPAL(i
));
735 /* it seems the only way to know exactly
736 * if the palette wrote ok, is to check
737 * to see if the value verifies ok
740 if (readw(regs
+ S3C2410_TFTPAL(i
)) == ent
)
741 fbi
->palette_buffer
[i
] = PALETTE_BUFF_CLEAR
;
743 fbi
->palette_ready
= 1; /* retry */
747 static irqreturn_t
s3c2410fb_irq(int irq
, void *dev_id
)
749 struct s3c2410fb_info
*fbi
= dev_id
;
750 void __iomem
*regs
= fbi
->io
;
751 unsigned long lcdirq
= readl(regs
+ S3C2410_LCDINTPND
);
753 if (lcdirq
& S3C2410_LCDINT_FRSYNC
) {
754 if (fbi
->palette_ready
)
755 s3c2410fb_write_palette(fbi
);
757 writel(S3C2410_LCDINT_FRSYNC
, regs
+ S3C2410_LCDINTPND
);
758 writel(S3C2410_LCDINT_FRSYNC
, regs
+ S3C2410_LCDSRCPND
);
764 static char driver_name
[]="s3c2410fb";
766 static int __init
s3c2410fb_probe(struct platform_device
*pdev
)
768 struct s3c2410fb_info
*info
;
769 struct fb_info
*fbinfo
;
770 struct s3c2410fb_hw
*mregs
;
771 struct resource
*res
;
778 mach_info
= pdev
->dev
.platform_data
;
779 if (mach_info
== NULL
) {
780 dev_err(&pdev
->dev
,"no platform data for lcd, cannot attach\n");
784 mregs
= &mach_info
->regs
;
786 irq
= platform_get_irq(pdev
, 0);
788 dev_err(&pdev
->dev
, "no irq for device\n");
792 fbinfo
= framebuffer_alloc(sizeof(struct s3c2410fb_info
), &pdev
->dev
);
799 info
->dev
= &pdev
->dev
;
801 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
803 dev_err(&pdev
->dev
, "failed to get memory registersn");
808 size
= (res
->end
- res
->start
)+1;
809 info
->mem
= request_mem_region(res
->start
, size
, pdev
->name
);
810 if (info
->mem
== NULL
) {
811 dev_err(&pdev
->dev
, "failed to get memory region\n");
816 info
->io
= ioremap(res
->start
, size
);
817 if (info
->io
== NULL
) {
818 dev_err(&pdev
->dev
, "ioremap() of registers failed\n");
823 platform_set_drvdata(pdev
, fbinfo
);
825 dprintk("devinit\n");
827 strcpy(fbinfo
->fix
.id
, driver_name
);
829 memcpy(&info
->regs
, &mach_info
->regs
, sizeof(info
->regs
));
831 /* Stop the video and unset ENVID if set */
832 info
->regs
.lcdcon1
&= ~S3C2410_LCDCON1_ENVID
;
833 lcdcon1
= readl(info
->io
+ S3C2410_LCDCON1
);
834 writel(lcdcon1
& ~S3C2410_LCDCON1_ENVID
, info
->io
+ S3C2410_LCDCON1
);
836 info
->mach_info
= pdev
->dev
.platform_data
;
838 fbinfo
->fix
.type
= FB_TYPE_PACKED_PIXELS
;
839 fbinfo
->fix
.type_aux
= 0;
840 fbinfo
->fix
.xpanstep
= 0;
841 fbinfo
->fix
.ypanstep
= 0;
842 fbinfo
->fix
.ywrapstep
= 0;
843 fbinfo
->fix
.accel
= FB_ACCEL_NONE
;
845 fbinfo
->var
.nonstd
= 0;
846 fbinfo
->var
.activate
= FB_ACTIVATE_NOW
;
847 fbinfo
->var
.height
= mach_info
->height
;
848 fbinfo
->var
.width
= mach_info
->width
;
849 fbinfo
->var
.accel_flags
= 0;
850 fbinfo
->var
.vmode
= FB_VMODE_NONINTERLACED
;
852 fbinfo
->fbops
= &s3c2410fb_ops
;
853 fbinfo
->flags
= FBINFO_FLAG_DEFAULT
;
854 fbinfo
->pseudo_palette
= &info
->pseudo_pal
;
856 fbinfo
->var
.xres
= mach_info
->xres
.defval
;
857 fbinfo
->var
.xres_virtual
= mach_info
->xres
.defval
;
858 fbinfo
->var
.yres
= mach_info
->yres
.defval
;
859 fbinfo
->var
.yres_virtual
= mach_info
->yres
.defval
;
860 fbinfo
->var
.bits_per_pixel
= mach_info
->bpp
.defval
;
862 fbinfo
->var
.upper_margin
= S3C2410_LCDCON2_GET_VBPD(mregs
->lcdcon2
) + 1;
863 fbinfo
->var
.lower_margin
= S3C2410_LCDCON2_GET_VFPD(mregs
->lcdcon2
) + 1;
864 fbinfo
->var
.vsync_len
= S3C2410_LCDCON2_GET_VSPW(mregs
->lcdcon2
) + 1;
866 fbinfo
->var
.left_margin
= S3C2410_LCDCON3_GET_HFPD(mregs
->lcdcon3
) + 1;
867 fbinfo
->var
.right_margin
= S3C2410_LCDCON3_GET_HBPD(mregs
->lcdcon3
) + 1;
868 fbinfo
->var
.hsync_len
= S3C2410_LCDCON4_GET_HSPW(mregs
->lcdcon4
) + 1;
870 fbinfo
->var
.red
.offset
= 11;
871 fbinfo
->var
.green
.offset
= 5;
872 fbinfo
->var
.blue
.offset
= 0;
873 fbinfo
->var
.transp
.offset
= 0;
874 fbinfo
->var
.red
.length
= 5;
875 fbinfo
->var
.green
.length
= 6;
876 fbinfo
->var
.blue
.length
= 5;
877 fbinfo
->var
.transp
.length
= 0;
878 fbinfo
->fix
.smem_len
= mach_info
->xres
.max
*
879 mach_info
->yres
.max
*
880 mach_info
->bpp
.max
/ 8;
882 for (i
= 0; i
< 256; i
++)
883 info
->palette_buffer
[i
] = PALETTE_BUFF_CLEAR
;
885 ret
= request_irq(irq
, s3c2410fb_irq
, IRQF_DISABLED
, pdev
->name
, info
);
887 dev_err(&pdev
->dev
, "cannot get irq %d - err %d\n", irq
, ret
);
892 info
->clk
= clk_get(NULL
, "lcd");
893 if (!info
->clk
|| IS_ERR(info
->clk
)) {
894 printk(KERN_ERR
"failed to get lcd clock source\n");
899 clk_enable(info
->clk
);
900 dprintk("got and enabled clock\n");
904 /* Initialize video memory */
905 ret
= s3c2410fb_map_video_memory(info
);
907 printk( KERN_ERR
"Failed to allocate video RAM: %d\n", ret
);
912 dprintk("got video memory\n");
914 ret
= s3c2410fb_init_registers(info
);
916 ret
= s3c2410fb_check_var(&fbinfo
->var
, fbinfo
);
918 ret
= register_framebuffer(fbinfo
);
920 printk(KERN_ERR
"Failed to register framebuffer device: %d\n", ret
);
921 goto free_video_memory
;
924 /* create device files */
925 device_create_file(&pdev
->dev
, &dev_attr_debug
);
927 printk(KERN_INFO
"fb%d: %s frame buffer device\n",
928 fbinfo
->node
, fbinfo
->fix
.id
);
933 s3c2410fb_unmap_video_memory(info
);
935 clk_disable(info
->clk
);
942 release_resource(info
->mem
);
945 framebuffer_release(fbinfo
);
949 /* s3c2410fb_stop_lcd
951 * shutdown the lcd controller
954 static void s3c2410fb_stop_lcd(struct s3c2410fb_info
*fbi
)
958 local_irq_save(flags
);
960 fbi
->regs
.lcdcon1
&= ~S3C2410_LCDCON1_ENVID
;
961 writel(fbi
->regs
.lcdcon1
, fbi
->io
+ S3C2410_LCDCON1
);
963 local_irq_restore(flags
);
969 static int s3c2410fb_remove(struct platform_device
*pdev
)
971 struct fb_info
*fbinfo
= platform_get_drvdata(pdev
);
972 struct s3c2410fb_info
*info
= fbinfo
->par
;
975 s3c2410fb_stop_lcd(info
);
978 s3c2410fb_unmap_video_memory(info
);
981 clk_disable(info
->clk
);
986 irq
= platform_get_irq(pdev
, 0);
989 release_resource(info
->mem
);
992 unregister_framebuffer(fbinfo
);
999 /* suspend and resume support for the lcd controller */
1001 static int s3c2410fb_suspend(struct platform_device
*dev
, pm_message_t state
)
1003 struct fb_info
*fbinfo
= platform_get_drvdata(dev
);
1004 struct s3c2410fb_info
*info
= fbinfo
->par
;
1006 s3c2410fb_stop_lcd(info
);
1008 /* sleep before disabling the clock, we need to ensure
1009 * the LCD DMA engine is not going to get back on the bus
1010 * before the clock goes off again (bjd) */
1013 clk_disable(info
->clk
);
1018 static int s3c2410fb_resume(struct platform_device
*dev
)
1020 struct fb_info
*fbinfo
= platform_get_drvdata(dev
);
1021 struct s3c2410fb_info
*info
= fbinfo
->par
;
1023 clk_enable(info
->clk
);
1026 s3c2410fb_init_registers(info
);
1032 #define s3c2410fb_suspend NULL
1033 #define s3c2410fb_resume NULL
1036 static struct platform_driver s3c2410fb_driver
= {
1037 .probe
= s3c2410fb_probe
,
1038 .remove
= s3c2410fb_remove
,
1039 .suspend
= s3c2410fb_suspend
,
1040 .resume
= s3c2410fb_resume
,
1042 .name
= "s3c2410-lcd",
1043 .owner
= THIS_MODULE
,
1047 int __devinit
s3c2410fb_init(void)
1049 return platform_driver_register(&s3c2410fb_driver
);
1052 static void __exit
s3c2410fb_cleanup(void)
1054 platform_driver_unregister(&s3c2410fb_driver
);
1058 module_init(s3c2410fb_init
);
1059 module_exit(s3c2410fb_cleanup
);
1061 MODULE_AUTHOR("Arnaud Patard <arnaud.patard@rtp-net.org>, Ben Dooks <ben-linux@fluff.org>");
1062 MODULE_DESCRIPTION("Framebuffer driver for the s3c2410");
1063 MODULE_LICENSE("GPL");