include/asm-mips/mips-boards/atlasint.h

   1 /*
   2  * Copyright (C) 1999, 2006  MIPS Technologies, Inc.  All rights reserved.
   3  *      Authors: Carsten Langgaard <carstenl@mips.com>
   4  *               Maciej W. Rozycki <macro@mips.com>
   5  *
   6  * ########################################################################
   7  *
   8  *  This program is free software; you can distribute it and/or modify it
   9  *  under the terms of the GNU General Public License (Version 2) as
  10  *  published by the Free Software Foundation.
  11  *
  12  *  This program is distributed in the hope it will be useful, but WITHOUT
  13  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  15  *  for more details.
  16  *
  17  *  You should have received a copy of the GNU General Public License along
  18  *  with this program; if not, write to the Free Software Foundation, Inc.,
  19  *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  20  *
  21  * ########################################################################
  22  *
  23  * Defines for the Atlas interrupt controller.
  24  *
  25  */
  26 #ifndef _MIPS_ATLASINT_H
  27 #define _MIPS_ATLASINT_H
  28
  29 #include <irq.h>
  30
  31 /* CPU interrupt offsets */
  32 #define MIPSCPU_INT_SW0         0
  33 #define MIPSCPU_INT_SW1         1
  34 #define MIPSCPU_INT_MB0         2
  35 #define MIPSCPU_INT_ATLAS       MIPSCPU_INT_MB0
  36 #define MIPSCPU_INT_MB1         3
  37 #define MIPSCPU_INT_MB2         4
  38 #define MIPSCPU_INT_MB3         5
  39 #define MIPSCPU_INT_MB4         6
  40
  41 /*
  42  * Interrupts 8..39 are used for Atlas interrupt controller interrupts
  43  */
  44 #define ATLAS_INT_BASE          8
  45 #define ATLAS_INT_UART          (ATLAS_INT_BASE + 0)
  46 #define ATLAS_INT_TIM0          (ATLAS_INT_BASE + 1)
  47 #define ATLAS_INT_RES2          (ATLAS_INT_BASE + 2)
  48 #define ATLAS_INT_RES3          (ATLAS_INT_BASE + 3)
  49 #define ATLAS_INT_RTC           (ATLAS_INT_BASE + 4)
  50 #define ATLAS_INT_COREHI        (ATLAS_INT_BASE + 5)
  51 #define ATLAS_INT_CORELO        (ATLAS_INT_BASE + 6)
  52 #define ATLAS_INT_RES7          (ATLAS_INT_BASE + 7)
  53 #define ATLAS_INT_PCIA          (ATLAS_INT_BASE + 8)
  54 #define ATLAS_INT_PCIB          (ATLAS_INT_BASE + 9)
  55 #define ATLAS_INT_PCIC          (ATLAS_INT_BASE + 10)
  56 #define ATLAS_INT_PCID          (ATLAS_INT_BASE + 11)
  57 #define ATLAS_INT_ENUM          (ATLAS_INT_BASE + 12)
  58 #define ATLAS_INT_DEG           (ATLAS_INT_BASE + 13)
  59 #define ATLAS_INT_ATXFAIL       (ATLAS_INT_BASE + 14)
  60 #define ATLAS_INT_INTA          (ATLAS_INT_BASE + 15)
  61 #define ATLAS_INT_INTB          (ATLAS_INT_BASE + 16)
  62 #define ATLAS_INT_ETH           ATLAS_INT_INTB
  63 #define ATLAS_INT_INTC          (ATLAS_INT_BASE + 17)
  64 #define ATLAS_INT_SCSI          ATLAS_INT_INTC
  65 #define ATLAS_INT_INTD          (ATLAS_INT_BASE + 18)
  66 #define ATLAS_INT_SERR          (ATLAS_INT_BASE + 19)
  67 #define ATLAS_INT_RES20         (ATLAS_INT_BASE + 20)
  68 #define ATLAS_INT_RES21         (ATLAS_INT_BASE + 21)
  69 #define ATLAS_INT_RES22         (ATLAS_INT_BASE + 22)
  70 #define ATLAS_INT_RES23         (ATLAS_INT_BASE + 23)
  71 #define ATLAS_INT_RES24         (ATLAS_INT_BASE + 24)
  72 #define ATLAS_INT_RES25         (ATLAS_INT_BASE + 25)
  73 #define ATLAS_INT_RES26         (ATLAS_INT_BASE + 26)
  74 #define ATLAS_INT_RES27         (ATLAS_INT_BASE + 27)
  75 #define ATLAS_INT_RES28         (ATLAS_INT_BASE + 28)
  76 #define ATLAS_INT_RES29         (ATLAS_INT_BASE + 29)
  77 #define ATLAS_INT_RES30         (ATLAS_INT_BASE + 30)
  78 #define ATLAS_INT_RES31         (ATLAS_INT_BASE + 31)
  79 #define ATLAS_INT_END           (ATLAS_INT_BASE + 31)
  80
  81 /*
  82  * Interrupts 64..127 are used for Soc-it Classic interrupts
  83  */
  84 #define MSC01C_INT_BASE         64
  85
  86 /* SOC-it Classic interrupt offsets */
  87 #define MSC01C_INT_TMR          0
  88 #define MSC01C_INT_PCI          1
  89
  90 /*
  91  * Interrupts 64..127 are used for Soc-it EIC interrupts
  92  */
  93 #define MSC01E_INT_BASE         64
  94
  95 /* SOC-it EIC interrupt offsets */
  96 #define MSC01E_INT_SW0          1
  97 #define MSC01E_INT_SW1          2
  98 #define MSC01E_INT_MB0          3
  99 #define MSC01E_INT_ATLAS        MSC01E_INT_MB0
 100 #define MSC01E_INT_MB1          4
 101 #define MSC01E_INT_MB2          5
 102 #define MSC01E_INT_MB3          6
 103 #define MSC01E_INT_MB4          7
 104 #define MSC01E_INT_TMR          8
 105 #define MSC01E_INT_PCI          9
 106 #define MSC01E_INT_PERFCTR      10
 107 #define MSC01E_INT_CPUCTR       11
 108
 109 #endif /* !(_MIPS_ATLASINT_H) */