2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Synthesize TLB refill handlers at runtime.
8 * Copyright (C) 2004,2005 by Thiemo Seufer
13 #include <linux/config.h>
15 #include <linux/kernel.h>
16 #include <linux/types.h>
17 #include <linux/string.h>
18 #include <linux/init.h>
20 #include <asm/pgtable.h>
21 #include <asm/cacheflush.h>
22 #include <asm/mmu_context.h>
28 /* #define DEBUG_TLB */
30 static __init
int __attribute__((unused
)) r45k_bvahwbug(void)
32 /* XXX: We should probe for the presence of this bug, but we don't. */
36 static __init
int __attribute__((unused
)) r4k_250MHZhwbug(void)
38 /* XXX: We should probe for the presence of this bug, but we don't. */
42 static __init
int __attribute__((unused
)) bcm1250_m3_war(void)
44 return BCM1250_M3_WAR
;
47 static __init
int __attribute__((unused
)) r10000_llsc_war(void)
49 return R10000_LLSC_WAR
;
53 * A little micro-assembler, intended for TLB refill handler
54 * synthesizing. It is intentionally kept simple, does only support
55 * a subset of instructions, and does not try to hide pipeline effects
56 * like branch delay slots.
82 #define IMM_MASK 0xffff
84 #define JIMM_MASK 0x3ffffff
86 #define FUNC_MASK 0x2f
91 insn_addu
, insn_addiu
, insn_and
, insn_andi
, insn_beq
,
92 insn_beql
, insn_bgez
, insn_bgezl
, insn_bltz
, insn_bltzl
,
93 insn_bne
, insn_daddu
, insn_daddiu
, insn_dmfc0
, insn_dmtc0
,
94 insn_dsll
, insn_dsll32
, insn_dsra
, insn_dsrl
,
95 insn_dsubu
, insn_eret
, insn_j
, insn_jal
, insn_jr
, insn_ld
,
96 insn_ll
, insn_lld
, insn_lui
, insn_lw
, insn_mfc0
, insn_mtc0
,
97 insn_ori
, insn_rfe
, insn_sc
, insn_scd
, insn_sd
, insn_sll
,
98 insn_sra
, insn_srl
, insn_subu
, insn_sw
, insn_tlbp
, insn_tlbwi
,
99 insn_tlbwr
, insn_xor
, insn_xori
108 /* This macro sets the non-variable bits of an instruction. */
109 #define M(a, b, c, d, e, f) \
117 static __initdata
struct insn insn_table
[] = {
118 { insn_addiu
, M(addiu_op
,0,0,0,0,0), RS
| RT
| SIMM
},
119 { insn_addu
, M(spec_op
,0,0,0,0,addu_op
), RS
| RT
| RD
},
120 { insn_and
, M(spec_op
,0,0,0,0,and_op
), RS
| RT
| RD
},
121 { insn_andi
, M(andi_op
,0,0,0,0,0), RS
| RT
| UIMM
},
122 { insn_beq
, M(beq_op
,0,0,0,0,0), RS
| RT
| BIMM
},
123 { insn_beql
, M(beql_op
,0,0,0,0,0), RS
| RT
| BIMM
},
124 { insn_bgez
, M(bcond_op
,0,bgez_op
,0,0,0), RS
| BIMM
},
125 { insn_bgezl
, M(bcond_op
,0,bgezl_op
,0,0,0), RS
| BIMM
},
126 { insn_bltz
, M(bcond_op
,0,bltz_op
,0,0,0), RS
| BIMM
},
127 { insn_bltzl
, M(bcond_op
,0,bltzl_op
,0,0,0), RS
| BIMM
},
128 { insn_bne
, M(bne_op
,0,0,0,0,0), RS
| RT
| BIMM
},
129 { insn_daddiu
, M(daddiu_op
,0,0,0,0,0), RS
| RT
| SIMM
},
130 { insn_daddu
, M(spec_op
,0,0,0,0,daddu_op
), RS
| RT
| RD
},
131 { insn_dmfc0
, M(cop0_op
,dmfc_op
,0,0,0,0), RT
| RD
},
132 { insn_dmtc0
, M(cop0_op
,dmtc_op
,0,0,0,0), RT
| RD
},
133 { insn_dsll
, M(spec_op
,0,0,0,0,dsll_op
), RT
| RD
| RE
},
134 { insn_dsll32
, M(spec_op
,0,0,0,0,dsll32_op
), RT
| RD
| RE
},
135 { insn_dsra
, M(spec_op
,0,0,0,0,dsra_op
), RT
| RD
| RE
},
136 { insn_dsrl
, M(spec_op
,0,0,0,0,dsrl_op
), RT
| RD
| RE
},
137 { insn_dsubu
, M(spec_op
,0,0,0,0,dsubu_op
), RS
| RT
| RD
},
138 { insn_eret
, M(cop0_op
,cop_op
,0,0,0,eret_op
), 0 },
139 { insn_j
, M(j_op
,0,0,0,0,0), JIMM
},
140 { insn_jal
, M(jal_op
,0,0,0,0,0), JIMM
},
141 { insn_jr
, M(spec_op
,0,0,0,0,jr_op
), RS
},
142 { insn_ld
, M(ld_op
,0,0,0,0,0), RS
| RT
| SIMM
},
143 { insn_ll
, M(ll_op
,0,0,0,0,0), RS
| RT
| SIMM
},
144 { insn_lld
, M(lld_op
,0,0,0,0,0), RS
| RT
| SIMM
},
145 { insn_lui
, M(lui_op
,0,0,0,0,0), RT
| SIMM
},
146 { insn_lw
, M(lw_op
,0,0,0,0,0), RS
| RT
| SIMM
},
147 { insn_mfc0
, M(cop0_op
,mfc_op
,0,0,0,0), RT
| RD
},
148 { insn_mtc0
, M(cop0_op
,mtc_op
,0,0,0,0), RT
| RD
},
149 { insn_ori
, M(ori_op
,0,0,0,0,0), RS
| RT
| UIMM
},
150 { insn_rfe
, M(cop0_op
,cop_op
,0,0,0,rfe_op
), 0 },
151 { insn_sc
, M(sc_op
,0,0,0,0,0), RS
| RT
| SIMM
},
152 { insn_scd
, M(scd_op
,0,0,0,0,0), RS
| RT
| SIMM
},
153 { insn_sd
, M(sd_op
,0,0,0,0,0), RS
| RT
| SIMM
},
154 { insn_sll
, M(spec_op
,0,0,0,0,sll_op
), RT
| RD
| RE
},
155 { insn_sra
, M(spec_op
,0,0,0,0,sra_op
), RT
| RD
| RE
},
156 { insn_srl
, M(spec_op
,0,0,0,0,srl_op
), RT
| RD
| RE
},
157 { insn_subu
, M(spec_op
,0,0,0,0,subu_op
), RS
| RT
| RD
},
158 { insn_sw
, M(sw_op
,0,0,0,0,0), RS
| RT
| SIMM
},
159 { insn_tlbp
, M(cop0_op
,cop_op
,0,0,0,tlbp_op
), 0 },
160 { insn_tlbwi
, M(cop0_op
,cop_op
,0,0,0,tlbwi_op
), 0 },
161 { insn_tlbwr
, M(cop0_op
,cop_op
,0,0,0,tlbwr_op
), 0 },
162 { insn_xor
, M(spec_op
,0,0,0,0,xor_op
), RS
| RT
| RD
},
163 { insn_xori
, M(xori_op
,0,0,0,0,0), RS
| RT
| UIMM
},
164 { insn_invalid
, 0, 0 }
169 static __init u32
build_rs(u32 arg
)
172 printk(KERN_WARNING
"TLB synthesizer field overflow\n");
174 return (arg
& RS_MASK
) << RS_SH
;
177 static __init u32
build_rt(u32 arg
)
180 printk(KERN_WARNING
"TLB synthesizer field overflow\n");
182 return (arg
& RT_MASK
) << RT_SH
;
185 static __init u32
build_rd(u32 arg
)
188 printk(KERN_WARNING
"TLB synthesizer field overflow\n");
190 return (arg
& RD_MASK
) << RD_SH
;
193 static __init u32
build_re(u32 arg
)
196 printk(KERN_WARNING
"TLB synthesizer field overflow\n");
198 return (arg
& RE_MASK
) << RE_SH
;
201 static __init u32
build_simm(s32 arg
)
203 if (arg
> 0x7fff || arg
< -0x8000)
204 printk(KERN_WARNING
"TLB synthesizer field overflow\n");
209 static __init u32
build_uimm(u32 arg
)
212 printk(KERN_WARNING
"TLB synthesizer field overflow\n");
214 return arg
& IMM_MASK
;
217 static __init u32
build_bimm(s32 arg
)
219 if (arg
> 0x1ffff || arg
< -0x20000)
220 printk(KERN_WARNING
"TLB synthesizer field overflow\n");
223 printk(KERN_WARNING
"Invalid TLB synthesizer branch target\n");
225 return ((arg
< 0) ? (1 << 15) : 0) | ((arg
>> 2) & 0x7fff);
228 static __init u32
build_jimm(u32 arg
)
230 if (arg
& ~((JIMM_MASK
) << 2))
231 printk(KERN_WARNING
"TLB synthesizer field overflow\n");
233 return (arg
>> 2) & JIMM_MASK
;
236 static __init u32
build_func(u32 arg
)
238 if (arg
& ~FUNC_MASK
)
239 printk(KERN_WARNING
"TLB synthesizer field overflow\n");
241 return arg
& FUNC_MASK
;
245 * The order of opcode arguments is implicitly left to right,
246 * starting with RS and ending with FUNC or IMM.
248 static void __init
build_insn(u32
**buf
, enum opcode opc
, ...)
250 struct insn
*ip
= NULL
;
255 for (i
= 0; insn_table
[i
].opcode
!= insn_invalid
; i
++)
256 if (insn_table
[i
].opcode
== opc
) {
262 panic("Unsupported TLB synthesizer instruction %d", opc
);
266 if (ip
->fields
& RS
) op
|= build_rs(va_arg(ap
, u32
));
267 if (ip
->fields
& RT
) op
|= build_rt(va_arg(ap
, u32
));
268 if (ip
->fields
& RD
) op
|= build_rd(va_arg(ap
, u32
));
269 if (ip
->fields
& RE
) op
|= build_re(va_arg(ap
, u32
));
270 if (ip
->fields
& SIMM
) op
|= build_simm(va_arg(ap
, s32
));
271 if (ip
->fields
& UIMM
) op
|= build_uimm(va_arg(ap
, u32
));
272 if (ip
->fields
& BIMM
) op
|= build_bimm(va_arg(ap
, s32
));
273 if (ip
->fields
& JIMM
) op
|= build_jimm(va_arg(ap
, u32
));
274 if (ip
->fields
& FUNC
) op
|= build_func(va_arg(ap
, u32
));
281 #define I_u1u2u3(op) \
282 static inline void i##op(u32 **buf, unsigned int a, \
283 unsigned int b, unsigned int c) \
285 build_insn(buf, insn##op, a, b, c); \
288 #define I_u2u1u3(op) \
289 static inline void i##op(u32 **buf, unsigned int a, \
290 unsigned int b, unsigned int c) \
292 build_insn(buf, insn##op, b, a, c); \
295 #define I_u3u1u2(op) \
296 static inline void i##op(u32 **buf, unsigned int a, \
297 unsigned int b, unsigned int c) \
299 build_insn(buf, insn##op, b, c, a); \
302 #define I_u1u2s3(op) \
303 static inline void i##op(u32 **buf, unsigned int a, \
304 unsigned int b, signed int c) \
306 build_insn(buf, insn##op, a, b, c); \
309 #define I_u2s3u1(op) \
310 static inline void i##op(u32 **buf, unsigned int a, \
311 signed int b, unsigned int c) \
313 build_insn(buf, insn##op, c, a, b); \
316 #define I_u2u1s3(op) \
317 static inline void i##op(u32 **buf, unsigned int a, \
318 unsigned int b, signed int c) \
320 build_insn(buf, insn##op, b, a, c); \
324 static inline void i##op(u32 **buf, unsigned int a, \
327 build_insn(buf, insn##op, a, b); \
331 static inline void i##op(u32 **buf, unsigned int a, \
334 build_insn(buf, insn##op, a, b); \
338 static inline void i##op(u32 **buf, unsigned int a) \
340 build_insn(buf, insn##op, a); \
344 static inline void i##op(u32 **buf) \
346 build_insn(buf, insn##op); \
411 label_smp_pgtable_change
,
412 label_r3000_write_probe_fail
,
413 label_r3000_write_probe_ok
421 static __init
void build_label(struct label
**lab
, u32
*addr
,
430 static inline void l##lb(struct label **lab, u32 *addr) \
432 build_label(lab, addr, label##lb); \
444 L_LA(_smp_pgtable_change
)
445 L_LA(_r3000_write_probe_fail
)
446 L_LA(_r3000_write_probe_ok
)
448 /* convenience macros for instructions */
450 # define i_LW(buf, rs, rt, off) i_ld(buf, rs, rt, off)
451 # define i_SW(buf, rs, rt, off) i_sd(buf, rs, rt, off)
452 # define i_SLL(buf, rs, rt, sh) i_dsll(buf, rs, rt, sh)
453 # define i_SRA(buf, rs, rt, sh) i_dsra(buf, rs, rt, sh)
454 # define i_SRL(buf, rs, rt, sh) i_dsrl(buf, rs, rt, sh)
455 # define i_MFC0(buf, rt, rd) i_dmfc0(buf, rt, rd)
456 # define i_MTC0(buf, rt, rd) i_dmtc0(buf, rt, rd)
457 # define i_ADDIU(buf, rs, rt, val) i_daddiu(buf, rs, rt, val)
458 # define i_ADDU(buf, rs, rt, rd) i_daddu(buf, rs, rt, rd)
459 # define i_SUBU(buf, rs, rt, rd) i_dsubu(buf, rs, rt, rd)
460 # define i_LL(buf, rs, rt, off) i_lld(buf, rs, rt, off)
461 # define i_SC(buf, rs, rt, off) i_scd(buf, rs, rt, off)
463 # define i_LW(buf, rs, rt, off) i_lw(buf, rs, rt, off)
464 # define i_SW(buf, rs, rt, off) i_sw(buf, rs, rt, off)
465 # define i_SLL(buf, rs, rt, sh) i_sll(buf, rs, rt, sh)
466 # define i_SRA(buf, rs, rt, sh) i_sra(buf, rs, rt, sh)
467 # define i_SRL(buf, rs, rt, sh) i_srl(buf, rs, rt, sh)
468 # define i_MFC0(buf, rt, rd) i_mfc0(buf, rt, rd)
469 # define i_MTC0(buf, rt, rd) i_mtc0(buf, rt, rd)
470 # define i_ADDIU(buf, rs, rt, val) i_addiu(buf, rs, rt, val)
471 # define i_ADDU(buf, rs, rt, rd) i_addu(buf, rs, rt, rd)
472 # define i_SUBU(buf, rs, rt, rd) i_subu(buf, rs, rt, rd)
473 # define i_LL(buf, rs, rt, off) i_ll(buf, rs, rt, off)
474 # define i_SC(buf, rs, rt, off) i_sc(buf, rs, rt, off)
477 #define i_b(buf, off) i_beq(buf, 0, 0, off)
478 #define i_beqz(buf, rs, off) i_beq(buf, rs, 0, off)
479 #define i_beqzl(buf, rs, off) i_beql(buf, rs, 0, off)
480 #define i_bnez(buf, rs, off) i_bne(buf, rs, 0, off)
481 #define i_bnezl(buf, rs, off) i_bnel(buf, rs, 0, off)
482 #define i_move(buf, a, b) i_ADDU(buf, a, 0, b)
483 #define i_nop(buf) i_sll(buf, 0, 0, 0)
484 #define i_ssnop(buf) i_sll(buf, 0, 0, 1)
485 #define i_ehb(buf) i_sll(buf, 0, 0, 3)
488 static __init
int __attribute__((unused
)) in_compat_space_p(long addr
)
490 /* Is this address in 32bit compat space? */
491 return (((addr
) & 0xffffffff00000000) == 0xffffffff00000000);
494 static __init
int __attribute__((unused
)) rel_highest(long val
)
496 return ((((val
+ 0x800080008000L
) >> 48) & 0xffff) ^ 0x8000) - 0x8000;
499 static __init
int __attribute__((unused
)) rel_higher(long val
)
501 return ((((val
+ 0x80008000L
) >> 32) & 0xffff) ^ 0x8000) - 0x8000;
505 static __init
int rel_hi(long val
)
507 return ((((val
+ 0x8000L
) >> 16) & 0xffff) ^ 0x8000) - 0x8000;
510 static __init
int rel_lo(long val
)
512 return ((val
& 0xffff) ^ 0x8000) - 0x8000;
515 static __init
void i_LA_mostly(u32
**buf
, unsigned int rs
, long addr
)
518 if (!in_compat_space_p(addr
)) {
519 i_lui(buf
, rs
, rel_highest(addr
));
520 if (rel_higher(addr
))
521 i_daddiu(buf
, rs
, rs
, rel_higher(addr
));
523 i_dsll(buf
, rs
, rs
, 16);
524 i_daddiu(buf
, rs
, rs
, rel_hi(addr
));
525 i_dsll(buf
, rs
, rs
, 16);
527 i_dsll32(buf
, rs
, rs
, 0);
530 i_lui(buf
, rs
, rel_hi(addr
));
533 static __init
void __attribute__((unused
)) i_LA(u32
**buf
, unsigned int rs
,
536 i_LA_mostly(buf
, rs
, addr
);
538 i_ADDIU(buf
, rs
, rs
, rel_lo(addr
));
551 static __init
void r_mips_pc16(struct reloc
**rel
, u32
*addr
,
555 (*rel
)->type
= R_MIPS_PC16
;
560 static inline void __resolve_relocs(struct reloc
*rel
, struct label
*lab
)
562 long laddr
= (long)lab
->addr
;
563 long raddr
= (long)rel
->addr
;
567 *rel
->addr
|= build_bimm(laddr
- (raddr
+ 4));
571 panic("Unsupported TLB synthesizer relocation %d",
576 static __init
void resolve_relocs(struct reloc
*rel
, struct label
*lab
)
580 for (; rel
->lab
!= label_invalid
; rel
++)
581 for (l
= lab
; l
->lab
!= label_invalid
; l
++)
582 if (rel
->lab
== l
->lab
)
583 __resolve_relocs(rel
, l
);
586 static __init
void move_relocs(struct reloc
*rel
, u32
*first
, u32
*end
,
589 for (; rel
->lab
!= label_invalid
; rel
++)
590 if (rel
->addr
>= first
&& rel
->addr
< end
)
594 static __init
void move_labels(struct label
*lab
, u32
*first
, u32
*end
,
597 for (; lab
->lab
!= label_invalid
; lab
++)
598 if (lab
->addr
>= first
&& lab
->addr
< end
)
602 static __init
void copy_handler(struct reloc
*rel
, struct label
*lab
,
603 u32
*first
, u32
*end
, u32
*target
)
605 long off
= (long)(target
- first
);
607 memcpy(target
, first
, (end
- first
) * sizeof(u32
));
609 move_relocs(rel
, first
, end
, off
);
610 move_labels(lab
, first
, end
, off
);
613 static __init
int __attribute__((unused
)) insn_has_bdelay(struct reloc
*rel
,
616 for (; rel
->lab
!= label_invalid
; rel
++) {
617 if (rel
->addr
== addr
618 && (rel
->type
== R_MIPS_PC16
619 || rel
->type
== R_MIPS_26
))
626 /* convenience functions for labeled branches */
627 static void __attribute__((unused
)) il_bltz(u32
**p
, struct reloc
**r
,
628 unsigned int reg
, enum label_id l
)
630 r_mips_pc16(r
, *p
, l
);
634 static void __attribute__((unused
)) il_b(u32
**p
, struct reloc
**r
,
637 r_mips_pc16(r
, *p
, l
);
641 static void il_beqz(u32
**p
, struct reloc
**r
, unsigned int reg
,
644 r_mips_pc16(r
, *p
, l
);
648 static void __attribute__((unused
))
649 il_beqzl(u32
**p
, struct reloc
**r
, unsigned int reg
, enum label_id l
)
651 r_mips_pc16(r
, *p
, l
);
655 static void il_bnez(u32
**p
, struct reloc
**r
, unsigned int reg
,
658 r_mips_pc16(r
, *p
, l
);
662 static void il_bgezl(u32
**p
, struct reloc
**r
, unsigned int reg
,
665 r_mips_pc16(r
, *p
, l
);
669 /* The only general purpose registers allowed in TLB handlers. */
673 /* Some CP0 registers */
675 #define C0_ENTRYLO0 2
676 #define C0_ENTRYLO1 3
678 #define C0_BADVADDR 8
679 #define C0_ENTRYHI 10
681 #define C0_XCONTEXT 20
684 # define GET_CONTEXT(buf, reg) i_MFC0(buf, reg, C0_XCONTEXT)
686 # define GET_CONTEXT(buf, reg) i_MFC0(buf, reg, C0_CONTEXT)
689 /* The worst case length of the handler is around 18 instructions for
690 * R3000-style TLBs and up to 63 instructions for R4000-style TLBs.
691 * Maximum space available is 32 instructions for R3000 and 64
692 * instructions for R4000.
694 * We deliberately chose a buffer size of 128, so we won't scribble
695 * over anything important on overflow before we panic.
697 static __initdata u32 tlb_handler
[128];
699 /* simply assume worst case size for labels and relocs */
700 static __initdata
struct label labels
[128];
701 static __initdata
struct reloc relocs
[128];
704 * The R3000 TLB handler is simple.
706 static void __init
build_r3000_tlb_refill_handler(void)
708 long pgdc
= (long)pgd_current
;
711 memset(tlb_handler
, 0, sizeof(tlb_handler
));
714 i_mfc0(&p
, K0
, C0_BADVADDR
);
715 i_lui(&p
, K1
, rel_hi(pgdc
)); /* cp0 delay */
716 i_lw(&p
, K1
, rel_lo(pgdc
), K1
);
717 i_srl(&p
, K0
, K0
, 22); /* load delay */
718 i_sll(&p
, K0
, K0
, 2);
719 i_addu(&p
, K1
, K1
, K0
);
720 i_mfc0(&p
, K0
, C0_CONTEXT
);
721 i_lw(&p
, K1
, 0, K1
); /* cp0 delay */
722 i_andi(&p
, K0
, K0
, 0xffc); /* load delay */
723 i_addu(&p
, K1
, K1
, K0
);
725 i_nop(&p
); /* load delay */
726 i_mtc0(&p
, K0
, C0_ENTRYLO0
);
727 i_mfc0(&p
, K1
, C0_EPC
); /* cp0 delay */
728 i_tlbwr(&p
); /* cp0 delay */
730 i_rfe(&p
); /* branch delay */
732 if (p
> tlb_handler
+ 32)
733 panic("TLB refill handler space exceeded");
735 printk("Synthesized TLB handler (%u instructions).\n",
736 (unsigned int)(p
- tlb_handler
));
741 for (i
= 0; i
< (p
- tlb_handler
); i
++)
742 printk("%08x\n", tlb_handler
[i
]);
746 memcpy((void *)CAC_BASE
, tlb_handler
, 0x80);
747 flush_icache_range(CAC_BASE
, CAC_BASE
+ 0x80);
751 * The R4000 TLB handler is much more complicated. We have two
752 * consecutive handler areas with 32 instructions space each.
753 * Since they aren't used at the same time, we can overflow in the
754 * other one.To keep things simple, we first assume linear space,
755 * then we relocate it to the final handler layout as needed.
757 static __initdata u32 final_handler
[64];
762 * From the IDT errata for the QED RM5230 (Nevada), processor revision 1.0:
763 * 2. A timing hazard exists for the TLBP instruction.
765 * stalling_instruction
768 * The JTLB is being read for the TLBP throughout the stall generated by the
769 * previous instruction. This is not really correct as the stalling instruction
770 * can modify the address used to access the JTLB. The failure symptom is that
771 * the TLBP instruction will use an address created for the stalling instruction
772 * and not the address held in C0_ENHI and thus report the wrong results.
774 * The software work-around is to not allow the instruction preceding the TLBP
775 * to stall - make it an NOP or some other instruction guaranteed not to stall.
777 * Errata 2 will not be fixed. This errata is also on the R5000.
779 * As if we MIPS hackers wouldn't know how to nop pipelines happy ...
781 static __init
void __attribute__((unused
)) build_tlb_probe_entry(u32
**p
)
783 switch (current_cpu_data
.cputype
) {
798 * Write random or indexed TLB entry, and care about the hazards from
799 * the preceeding mtc0 and for the following eret.
801 enum tlb_write_entry
{ tlb_random
, tlb_indexed
};
803 static __init
void build_tlb_write_entry(u32
**p
, struct label
**l
,
805 enum tlb_write_entry wmode
)
807 void(*tlbw
)(u32
**) = NULL
;
810 case tlb_random
: tlbw
= i_tlbwr
; break;
811 case tlb_indexed
: tlbw
= i_tlbwi
; break;
814 switch (current_cpu_data
.cputype
) {
822 * This branch uses up a mtc0 hazard nop slot and saves
823 * two nops after the tlbw instruction.
825 il_bgezl(p
, r
, 0, label_tlbw_hazard
);
827 l_tlbw_hazard(l
, *p
);
858 i_nop(p
); /* QED specifies 2 nops hazard */
860 * This branch uses up a mtc0 hazard nop slot and saves
861 * a nop after the tlbw instruction.
863 il_bgezl(p
, r
, 0, label_tlbw_hazard
);
865 l_tlbw_hazard(l
, *p
);
884 * When the JTLB is updated by tlbwi or tlbwr, a subsequent
885 * use of the JTLB for instructions should not occur for 4
886 * cpu cycles and use for data translations should not occur
920 panic("No TLB refill handler yet (CPU type: %d)",
921 current_cpu_data
.cputype
);
928 * TMP and PTR are scratch.
929 * TMP will be clobbered, PTR will hold the pmd entry.
932 build_get_pmde64(u32
**p
, struct label
**l
, struct reloc
**r
,
933 unsigned int tmp
, unsigned int ptr
)
935 long pgdc
= (long)pgd_current
;
938 * The vmalloc handling is not in the hotpath.
940 i_dmfc0(p
, tmp
, C0_BADVADDR
);
941 il_bltz(p
, r
, tmp
, label_vmalloc
);
942 /* No i_nop needed here, since the next insn doesn't touch TMP. */
945 # ifdef CONFIG_BUILD_ELF64
947 * 64 bit SMP running in XKPHYS has smp_processor_id() << 3
950 i_dmfc0(p
, ptr
, C0_CONTEXT
);
951 i_dsrl(p
, ptr
, ptr
, 23);
952 i_LA_mostly(p
, tmp
, pgdc
);
953 i_daddu(p
, ptr
, ptr
, tmp
);
954 i_dmfc0(p
, tmp
, C0_BADVADDR
);
955 i_ld(p
, ptr
, rel_lo(pgdc
), ptr
);
958 * 64 bit SMP running in compat space has the lower part of
959 * &pgd_current[smp_processor_id()] stored in CONTEXT.
961 if (!in_compat_space_p(pgdc
))
962 panic("Invalid page directory address!");
964 i_dmfc0(p
, ptr
, C0_CONTEXT
);
965 i_dsra(p
, ptr
, ptr
, 23);
966 i_ld(p
, ptr
, 0, ptr
);
969 i_LA_mostly(p
, ptr
, pgdc
);
970 i_ld(p
, ptr
, rel_lo(pgdc
), ptr
);
973 l_vmalloc_done(l
, *p
);
974 i_dsrl(p
, tmp
, tmp
, PGDIR_SHIFT
-3); /* get pgd offset in bytes */
975 i_andi(p
, tmp
, tmp
, (PTRS_PER_PGD
- 1)<<3);
976 i_daddu(p
, ptr
, ptr
, tmp
); /* add in pgd offset */
977 i_dmfc0(p
, tmp
, C0_BADVADDR
); /* get faulting address */
978 i_ld(p
, ptr
, 0, ptr
); /* get pmd pointer */
979 i_dsrl(p
, tmp
, tmp
, PMD_SHIFT
-3); /* get pmd offset in bytes */
980 i_andi(p
, tmp
, tmp
, (PTRS_PER_PMD
- 1)<<3);
981 i_daddu(p
, ptr
, ptr
, tmp
); /* add in pmd offset */
985 * BVADDR is the faulting address, PTR is scratch.
986 * PTR will hold the pgd for vmalloc.
989 build_get_pgd_vmalloc64(u32
**p
, struct label
**l
, struct reloc
**r
,
990 unsigned int bvaddr
, unsigned int ptr
)
992 long swpd
= (long)swapper_pg_dir
;
995 i_LA(p
, ptr
, VMALLOC_START
);
996 i_dsubu(p
, bvaddr
, bvaddr
, ptr
);
998 if (in_compat_space_p(swpd
) && !rel_lo(swpd
)) {
999 il_b(p
, r
, label_vmalloc_done
);
1000 i_lui(p
, ptr
, rel_hi(swpd
));
1002 i_LA_mostly(p
, ptr
, swpd
);
1003 il_b(p
, r
, label_vmalloc_done
);
1004 i_daddiu(p
, ptr
, ptr
, rel_lo(swpd
));
1008 #else /* !CONFIG_64BIT */
1011 * TMP and PTR are scratch.
1012 * TMP will be clobbered, PTR will hold the pgd entry.
1014 static __init
void __attribute__((unused
))
1015 build_get_pgde32(u32
**p
, unsigned int tmp
, unsigned int ptr
)
1017 long pgdc
= (long)pgd_current
;
1019 /* 32 bit SMP has smp_processor_id() stored in CONTEXT. */
1021 i_mfc0(p
, ptr
, C0_CONTEXT
);
1022 i_LA_mostly(p
, tmp
, pgdc
);
1023 i_srl(p
, ptr
, ptr
, 23);
1024 i_addu(p
, ptr
, tmp
, ptr
);
1026 i_LA_mostly(p
, ptr
, pgdc
);
1028 i_mfc0(p
, tmp
, C0_BADVADDR
); /* get faulting address */
1029 i_lw(p
, ptr
, rel_lo(pgdc
), ptr
);
1030 i_srl(p
, tmp
, tmp
, PGDIR_SHIFT
); /* get pgd only bits */
1031 i_sll(p
, tmp
, tmp
, PGD_T_LOG2
);
1032 i_addu(p
, ptr
, ptr
, tmp
); /* add in pgd offset */
1035 #endif /* !CONFIG_64BIT */
1037 static __init
void build_adjust_context(u32
**p
, unsigned int ctx
)
1039 unsigned int shift
= 4 - (PTE_T_LOG2
+ 1);
1040 unsigned int mask
= (PTRS_PER_PTE
/ 2 - 1) << (PTE_T_LOG2
+ 1);
1042 switch (current_cpu_data
.cputype
) {
1059 i_SRL(p
, ctx
, ctx
, shift
);
1060 i_andi(p
, ctx
, ctx
, mask
);
1063 static __init
void build_get_ptep(u32
**p
, unsigned int tmp
, unsigned int ptr
)
1066 * Bug workaround for the Nevada. It seems as if under certain
1067 * circumstances the move from cp0_context might produce a
1068 * bogus result when the mfc0 instruction and its consumer are
1069 * in a different cacheline or a load instruction, probably any
1070 * memory reference, is between them.
1072 switch (current_cpu_data
.cputype
) {
1074 i_LW(p
, ptr
, 0, ptr
);
1075 GET_CONTEXT(p
, tmp
); /* get context reg */
1079 GET_CONTEXT(p
, tmp
); /* get context reg */
1080 i_LW(p
, ptr
, 0, ptr
);
1084 build_adjust_context(p
, tmp
);
1085 i_ADDU(p
, ptr
, ptr
, tmp
); /* add in offset */
1088 static __init
void build_update_entries(u32
**p
, unsigned int tmp
,
1092 * 64bit address support (36bit on a 32bit CPU) in a 32bit
1093 * Kernel is a special case. Only a few CPUs use it.
1095 #ifdef CONFIG_64BIT_PHYS_ADDR
1096 if (cpu_has_64bits
) {
1097 i_ld(p
, tmp
, 0, ptep
); /* get even pte */
1098 i_ld(p
, ptep
, sizeof(pte_t
), ptep
); /* get odd pte */
1099 i_dsrl(p
, tmp
, tmp
, 6); /* convert to entrylo0 */
1100 i_mtc0(p
, tmp
, C0_ENTRYLO0
); /* load it */
1101 i_dsrl(p
, ptep
, ptep
, 6); /* convert to entrylo1 */
1102 i_mtc0(p
, ptep
, C0_ENTRYLO1
); /* load it */
1104 int pte_off_even
= sizeof(pte_t
) / 2;
1105 int pte_off_odd
= pte_off_even
+ sizeof(pte_t
);
1107 /* The pte entries are pre-shifted */
1108 i_lw(p
, tmp
, pte_off_even
, ptep
); /* get even pte */
1109 i_mtc0(p
, tmp
, C0_ENTRYLO0
); /* load it */
1110 i_lw(p
, ptep
, pte_off_odd
, ptep
); /* get odd pte */
1111 i_mtc0(p
, ptep
, C0_ENTRYLO1
); /* load it */
1114 i_LW(p
, tmp
, 0, ptep
); /* get even pte */
1115 i_LW(p
, ptep
, sizeof(pte_t
), ptep
); /* get odd pte */
1116 if (r45k_bvahwbug())
1117 build_tlb_probe_entry(p
);
1118 i_SRL(p
, tmp
, tmp
, 6); /* convert to entrylo0 */
1119 if (r4k_250MHZhwbug())
1120 i_mtc0(p
, 0, C0_ENTRYLO0
);
1121 i_mtc0(p
, tmp
, C0_ENTRYLO0
); /* load it */
1122 i_SRL(p
, ptep
, ptep
, 6); /* convert to entrylo1 */
1123 if (r45k_bvahwbug())
1124 i_mfc0(p
, tmp
, C0_INDEX
);
1125 if (r4k_250MHZhwbug())
1126 i_mtc0(p
, 0, C0_ENTRYLO1
);
1127 i_mtc0(p
, ptep
, C0_ENTRYLO1
); /* load it */
1131 static void __init
build_r4000_tlb_refill_handler(void)
1133 u32
*p
= tlb_handler
;
1134 struct label
*l
= labels
;
1135 struct reloc
*r
= relocs
;
1137 unsigned int final_len
;
1139 memset(tlb_handler
, 0, sizeof(tlb_handler
));
1140 memset(labels
, 0, sizeof(labels
));
1141 memset(relocs
, 0, sizeof(relocs
));
1142 memset(final_handler
, 0, sizeof(final_handler
));
1145 * create the plain linear handler
1147 if (bcm1250_m3_war()) {
1148 i_MFC0(&p
, K0
, C0_BADVADDR
);
1149 i_MFC0(&p
, K1
, C0_ENTRYHI
);
1150 i_xor(&p
, K0
, K0
, K1
);
1151 i_SRL(&p
, K0
, K0
, PAGE_SHIFT
+ 1);
1152 il_bnez(&p
, &r
, K0
, label_leave
);
1153 /* No need for i_nop */
1157 build_get_pmde64(&p
, &l
, &r
, K0
, K1
); /* get pmd in K1 */
1159 build_get_pgde32(&p
, K0
, K1
); /* get pgd in K1 */
1162 build_get_ptep(&p
, K0
, K1
);
1163 build_update_entries(&p
, K0
, K1
);
1164 build_tlb_write_entry(&p
, &l
, &r
, tlb_random
);
1166 i_eret(&p
); /* return from trap */
1169 build_get_pgd_vmalloc64(&p
, &l
, &r
, K0
, K1
);
1173 * Overflow check: For the 64bit handler, we need at least one
1174 * free instruction slot for the wrap-around branch. In worst
1175 * case, if the intended insertion point is a delay slot, we
1176 * need three, with the the second nop'ed and the third being
1180 if ((p
- tlb_handler
) > 64)
1181 panic("TLB refill handler space exceeded");
1183 if (((p
- tlb_handler
) > 63)
1184 || (((p
- tlb_handler
) > 61)
1185 && insn_has_bdelay(relocs
, tlb_handler
+ 29)))
1186 panic("TLB refill handler space exceeded");
1190 * Now fold the handler in the TLB refill handler space.
1194 /* Simplest case, just copy the handler. */
1195 copy_handler(relocs
, labels
, tlb_handler
, p
, f
);
1196 final_len
= p
- tlb_handler
;
1197 #else /* CONFIG_64BIT */
1198 f
= final_handler
+ 32;
1199 if ((p
- tlb_handler
) <= 32) {
1200 /* Just copy the handler. */
1201 copy_handler(relocs
, labels
, tlb_handler
, p
, f
);
1202 final_len
= p
- tlb_handler
;
1204 u32
*split
= tlb_handler
+ 30;
1207 * Find the split point.
1209 if (insn_has_bdelay(relocs
, split
- 1))
1212 /* Copy first part of the handler. */
1213 copy_handler(relocs
, labels
, tlb_handler
, split
, f
);
1214 f
+= split
- tlb_handler
;
1216 /* Insert branch. */
1217 l_split(&l
, final_handler
);
1218 il_b(&f
, &r
, label_split
);
1219 if (insn_has_bdelay(relocs
, split
))
1222 copy_handler(relocs
, labels
, split
, split
+ 1, f
);
1223 move_labels(labels
, f
, f
+ 1, -1);
1228 /* Copy the rest of the handler. */
1229 copy_handler(relocs
, labels
, split
, p
, final_handler
);
1230 final_len
= (f
- (final_handler
+ 32)) + (p
- split
);
1232 #endif /* CONFIG_64BIT */
1234 resolve_relocs(relocs
, labels
);
1235 printk("Synthesized TLB refill handler (%u instructions).\n",
1242 for (i
= 0; i
< final_len
; i
++)
1243 printk("%08x\n", final_handler
[i
]);
1247 memcpy((void *)CAC_BASE
, final_handler
, 0x100);
1248 flush_icache_range(CAC_BASE
, CAC_BASE
+ 0x100);
1252 * TLB load/store/modify handlers.
1254 * Only the fastpath gets synthesized at runtime, the slowpath for
1255 * do_page_fault remains normal asm.
1257 extern void tlb_do_page_fault_0(void);
1258 extern void tlb_do_page_fault_1(void);
1260 #define __tlb_handler_align \
1261 __attribute__((__aligned__(1 << CONFIG_MIPS_L1_CACHE_SHIFT)))
1264 * 128 instructions for the fastpath handler is generous and should
1265 * never be exceeded.
1267 #define FASTPATH_SIZE 128
1269 u32 __tlb_handler_align handle_tlbl
[FASTPATH_SIZE
];
1270 u32 __tlb_handler_align handle_tlbs
[FASTPATH_SIZE
];
1271 u32 __tlb_handler_align handle_tlbm
[FASTPATH_SIZE
];
1274 iPTE_LW(u32
**p
, struct label
**l
, unsigned int pte
, unsigned int ptr
)
1277 # ifdef CONFIG_64BIT_PHYS_ADDR
1279 i_lld(p
, pte
, 0, ptr
);
1282 i_LL(p
, pte
, 0, ptr
);
1284 # ifdef CONFIG_64BIT_PHYS_ADDR
1286 i_ld(p
, pte
, 0, ptr
);
1289 i_LW(p
, pte
, 0, ptr
);
1294 iPTE_SW(u32
**p
, struct reloc
**r
, unsigned int pte
, unsigned int ptr
,
1297 #ifdef CONFIG_64BIT_PHYS_ADDR
1298 unsigned int hwmode
= mode
& (_PAGE_VALID
| _PAGE_DIRTY
);
1301 i_ori(p
, pte
, pte
, mode
);
1303 # ifdef CONFIG_64BIT_PHYS_ADDR
1305 i_scd(p
, pte
, 0, ptr
);
1308 i_SC(p
, pte
, 0, ptr
);
1310 if (r10000_llsc_war())
1311 il_beqzl(p
, r
, pte
, label_smp_pgtable_change
);
1313 il_beqz(p
, r
, pte
, label_smp_pgtable_change
);
1315 # ifdef CONFIG_64BIT_PHYS_ADDR
1316 if (!cpu_has_64bits
) {
1317 /* no i_nop needed */
1318 i_ll(p
, pte
, sizeof(pte_t
) / 2, ptr
);
1319 i_ori(p
, pte
, pte
, hwmode
);
1320 i_sc(p
, pte
, sizeof(pte_t
) / 2, ptr
);
1321 il_beqz(p
, r
, pte
, label_smp_pgtable_change
);
1322 /* no i_nop needed */
1323 i_lw(p
, pte
, 0, ptr
);
1330 # ifdef CONFIG_64BIT_PHYS_ADDR
1332 i_sd(p
, pte
, 0, ptr
);
1335 i_SW(p
, pte
, 0, ptr
);
1337 # ifdef CONFIG_64BIT_PHYS_ADDR
1338 if (!cpu_has_64bits
) {
1339 i_lw(p
, pte
, sizeof(pte_t
) / 2, ptr
);
1340 i_ori(p
, pte
, pte
, hwmode
);
1341 i_sw(p
, pte
, sizeof(pte_t
) / 2, ptr
);
1342 i_lw(p
, pte
, 0, ptr
);
1349 * Check if PTE is present, if not then jump to LABEL. PTR points to
1350 * the page table where this PTE is located, PTE will be re-loaded
1351 * with it's original value.
1354 build_pte_present(u32
**p
, struct label
**l
, struct reloc
**r
,
1355 unsigned int pte
, unsigned int ptr
, enum label_id lid
)
1357 i_andi(p
, pte
, pte
, _PAGE_PRESENT
| _PAGE_READ
);
1358 i_xori(p
, pte
, pte
, _PAGE_PRESENT
| _PAGE_READ
);
1359 il_bnez(p
, r
, pte
, lid
);
1360 iPTE_LW(p
, l
, pte
, ptr
);
1363 /* Make PTE valid, store result in PTR. */
1365 build_make_valid(u32
**p
, struct reloc
**r
, unsigned int pte
,
1368 unsigned int mode
= _PAGE_VALID
| _PAGE_ACCESSED
;
1370 iPTE_SW(p
, r
, pte
, ptr
, mode
);
1374 * Check if PTE can be written to, if not branch to LABEL. Regardless
1375 * restore PTE with value from PTR when done.
1378 build_pte_writable(u32
**p
, struct label
**l
, struct reloc
**r
,
1379 unsigned int pte
, unsigned int ptr
, enum label_id lid
)
1381 i_andi(p
, pte
, pte
, _PAGE_PRESENT
| _PAGE_WRITE
);
1382 i_xori(p
, pte
, pte
, _PAGE_PRESENT
| _PAGE_WRITE
);
1383 il_bnez(p
, r
, pte
, lid
);
1384 iPTE_LW(p
, l
, pte
, ptr
);
1387 /* Make PTE writable, update software status bits as well, then store
1391 build_make_write(u32
**p
, struct reloc
**r
, unsigned int pte
,
1394 unsigned int mode
= (_PAGE_ACCESSED
| _PAGE_MODIFIED
| _PAGE_VALID
1397 iPTE_SW(p
, r
, pte
, ptr
, mode
);
1401 * Check if PTE can be modified, if not branch to LABEL. Regardless
1402 * restore PTE with value from PTR when done.
1405 build_pte_modifiable(u32
**p
, struct label
**l
, struct reloc
**r
,
1406 unsigned int pte
, unsigned int ptr
, enum label_id lid
)
1408 i_andi(p
, pte
, pte
, _PAGE_WRITE
);
1409 il_beqz(p
, r
, pte
, lid
);
1410 iPTE_LW(p
, l
, pte
, ptr
);
1414 * R3000 style TLB load/store/modify handlers.
1417 /* This places the pte in the page table at PTR into ENTRYLO0. */
1419 build_r3000_pte_reload(u32
**p
, unsigned int ptr
)
1421 i_lw(p
, ptr
, 0, ptr
);
1422 i_nop(p
); /* load delay */
1423 i_mtc0(p
, ptr
, C0_ENTRYLO0
);
1424 i_nop(p
); /* cp0 delay */
1428 * The index register may have the probe fail bit set,
1429 * because we would trap on access kseg2, i.e. without refill.
1432 build_r3000_tlb_write(u32
**p
, struct label
**l
, struct reloc
**r
,
1435 i_mfc0(p
, tmp
, C0_INDEX
);
1436 i_nop(p
); /* cp0 delay */
1437 il_bltz(p
, r
, tmp
, label_r3000_write_probe_fail
);
1438 i_nop(p
); /* branch delay */
1440 il_b(p
, r
, label_r3000_write_probe_ok
);
1441 i_nop(p
); /* branch delay */
1442 l_r3000_write_probe_fail(l
, *p
);
1444 l_r3000_write_probe_ok(l
, *p
);
1448 build_r3000_tlbchange_handler_head(u32
**p
, unsigned int pte
,
1451 long pgdc
= (long)pgd_current
;
1453 i_mfc0(p
, pte
, C0_BADVADDR
);
1454 i_lui(p
, ptr
, rel_hi(pgdc
)); /* cp0 delay */
1455 i_lw(p
, ptr
, rel_lo(pgdc
), ptr
);
1456 i_srl(p
, pte
, pte
, 22); /* load delay */
1457 i_sll(p
, pte
, pte
, 2);
1458 i_addu(p
, ptr
, ptr
, pte
);
1459 i_mfc0(p
, pte
, C0_CONTEXT
);
1460 i_lw(p
, ptr
, 0, ptr
); /* cp0 delay */
1461 i_andi(p
, pte
, pte
, 0xffc); /* load delay */
1462 i_addu(p
, ptr
, ptr
, pte
);
1463 i_lw(p
, pte
, 0, ptr
);
1464 i_nop(p
); /* load delay */
1469 build_r3000_tlbchange_handler_tail(u32
**p
, unsigned int tmp
)
1471 i_mfc0(p
, tmp
, C0_EPC
);
1472 i_nop(p
); /* cp0 delay */
1474 i_rfe(p
); /* branch delay */
1477 static void __init
build_r3000_tlb_load_handler(void)
1479 u32
*p
= handle_tlbl
;
1480 struct label
*l
= labels
;
1481 struct reloc
*r
= relocs
;
1483 memset(handle_tlbl
, 0, sizeof(handle_tlbl
));
1484 memset(labels
, 0, sizeof(labels
));
1485 memset(relocs
, 0, sizeof(relocs
));
1487 build_r3000_tlbchange_handler_head(&p
, K0
, K1
);
1488 build_pte_present(&p
, &l
, &r
, K0
, K1
, label_nopage_tlbl
);
1489 build_make_valid(&p
, &r
, K0
, K1
);
1490 build_r3000_pte_reload(&p
, K1
);
1491 build_r3000_tlb_write(&p
, &l
, &r
, K0
);
1492 build_r3000_tlbchange_handler_tail(&p
, K0
);
1494 l_nopage_tlbl(&l
, p
);
1495 i_j(&p
, (unsigned long)tlb_do_page_fault_0
& 0x0fffffff);
1498 if ((p
- handle_tlbl
) > FASTPATH_SIZE
)
1499 panic("TLB load handler fastpath space exceeded");
1501 resolve_relocs(relocs
, labels
);
1502 printk("Synthesized TLB load handler fastpath (%u instructions).\n",
1503 (unsigned int)(p
- handle_tlbl
));
1509 for (i
= 0; i
< (p
- handle_tlbl
); i
++)
1510 printk("%08x\n", handle_tlbl
[i
]);
1514 flush_icache_range((unsigned long)handle_tlbl
,
1515 (unsigned long)handle_tlbl
+ FASTPATH_SIZE
* sizeof(u32
));
1518 static void __init
build_r3000_tlb_store_handler(void)
1520 u32
*p
= handle_tlbs
;
1521 struct label
*l
= labels
;
1522 struct reloc
*r
= relocs
;
1524 memset(handle_tlbs
, 0, sizeof(handle_tlbs
));
1525 memset(labels
, 0, sizeof(labels
));
1526 memset(relocs
, 0, sizeof(relocs
));
1528 build_r3000_tlbchange_handler_head(&p
, K0
, K1
);
1529 build_pte_writable(&p
, &l
, &r
, K0
, K1
, label_nopage_tlbs
);
1530 build_make_write(&p
, &r
, K0
, K1
);
1531 build_r3000_pte_reload(&p
, K1
);
1532 build_r3000_tlb_write(&p
, &l
, &r
, K0
);
1533 build_r3000_tlbchange_handler_tail(&p
, K0
);
1535 l_nopage_tlbs(&l
, p
);
1536 i_j(&p
, (unsigned long)tlb_do_page_fault_1
& 0x0fffffff);
1539 if ((p
- handle_tlbs
) > FASTPATH_SIZE
)
1540 panic("TLB store handler fastpath space exceeded");
1542 resolve_relocs(relocs
, labels
);
1543 printk("Synthesized TLB store handler fastpath (%u instructions).\n",
1544 (unsigned int)(p
- handle_tlbs
));
1550 for (i
= 0; i
< (p
- handle_tlbs
); i
++)
1551 printk("%08x\n", handle_tlbs
[i
]);
1555 flush_icache_range((unsigned long)handle_tlbs
,
1556 (unsigned long)handle_tlbs
+ FASTPATH_SIZE
* sizeof(u32
));
1559 static void __init
build_r3000_tlb_modify_handler(void)
1561 u32
*p
= handle_tlbm
;
1562 struct label
*l
= labels
;
1563 struct reloc
*r
= relocs
;
1565 memset(handle_tlbm
, 0, sizeof(handle_tlbm
));
1566 memset(labels
, 0, sizeof(labels
));
1567 memset(relocs
, 0, sizeof(relocs
));
1569 build_r3000_tlbchange_handler_head(&p
, K0
, K1
);
1570 build_pte_modifiable(&p
, &l
, &r
, K0
, K1
, label_nopage_tlbm
);
1571 build_make_write(&p
, &r
, K0
, K1
);
1572 build_r3000_pte_reload(&p
, K1
);
1574 build_r3000_tlbchange_handler_tail(&p
, K0
);
1576 l_nopage_tlbm(&l
, p
);
1577 i_j(&p
, (unsigned long)tlb_do_page_fault_1
& 0x0fffffff);
1580 if ((p
- handle_tlbm
) > FASTPATH_SIZE
)
1581 panic("TLB modify handler fastpath space exceeded");
1583 resolve_relocs(relocs
, labels
);
1584 printk("Synthesized TLB modify handler fastpath (%u instructions).\n",
1585 (unsigned int)(p
- handle_tlbm
));
1591 for (i
= 0; i
< (p
- handle_tlbm
); i
++)
1592 printk("%08x\n", handle_tlbm
[i
]);
1596 flush_icache_range((unsigned long)handle_tlbm
,
1597 (unsigned long)handle_tlbm
+ FASTPATH_SIZE
* sizeof(u32
));
1601 * R4000 style TLB load/store/modify handlers.
1604 build_r4000_tlbchange_handler_head(u32
**p
, struct label
**l
,
1605 struct reloc
**r
, unsigned int pte
,
1609 build_get_pmde64(p
, l
, r
, pte
, ptr
); /* get pmd in ptr */
1611 build_get_pgde32(p
, pte
, ptr
); /* get pgd in ptr */
1614 i_MFC0(p
, pte
, C0_BADVADDR
);
1615 i_LW(p
, ptr
, 0, ptr
);
1616 i_SRL(p
, pte
, pte
, PAGE_SHIFT
+ PTE_ORDER
- PTE_T_LOG2
);
1617 i_andi(p
, pte
, pte
, (PTRS_PER_PTE
- 1) << PTE_T_LOG2
);
1618 i_ADDU(p
, ptr
, ptr
, pte
);
1621 l_smp_pgtable_change(l
, *p
);
1623 iPTE_LW(p
, l
, pte
, ptr
); /* get even pte */
1624 build_tlb_probe_entry(p
);
1628 build_r4000_tlbchange_handler_tail(u32
**p
, struct label
**l
,
1629 struct reloc
**r
, unsigned int tmp
,
1632 i_ori(p
, ptr
, ptr
, sizeof(pte_t
));
1633 i_xori(p
, ptr
, ptr
, sizeof(pte_t
));
1634 build_update_entries(p
, tmp
, ptr
);
1635 build_tlb_write_entry(p
, l
, r
, tlb_indexed
);
1637 i_eret(p
); /* return from trap */
1640 build_get_pgd_vmalloc64(p
, l
, r
, tmp
, ptr
);
1644 static void __init
build_r4000_tlb_load_handler(void)
1646 u32
*p
= handle_tlbl
;
1647 struct label
*l
= labels
;
1648 struct reloc
*r
= relocs
;
1650 memset(handle_tlbl
, 0, sizeof(handle_tlbl
));
1651 memset(labels
, 0, sizeof(labels
));
1652 memset(relocs
, 0, sizeof(relocs
));
1654 if (bcm1250_m3_war()) {
1655 i_MFC0(&p
, K0
, C0_BADVADDR
);
1656 i_MFC0(&p
, K1
, C0_ENTRYHI
);
1657 i_xor(&p
, K0
, K0
, K1
);
1658 i_SRL(&p
, K0
, K0
, PAGE_SHIFT
+ 1);
1659 il_bnez(&p
, &r
, K0
, label_leave
);
1660 /* No need for i_nop */
1663 build_r4000_tlbchange_handler_head(&p
, &l
, &r
, K0
, K1
);
1664 build_pte_present(&p
, &l
, &r
, K0
, K1
, label_nopage_tlbl
);
1665 build_make_valid(&p
, &r
, K0
, K1
);
1666 build_r4000_tlbchange_handler_tail(&p
, &l
, &r
, K0
, K1
);
1668 l_nopage_tlbl(&l
, p
);
1669 i_j(&p
, (unsigned long)tlb_do_page_fault_0
& 0x0fffffff);
1672 if ((p
- handle_tlbl
) > FASTPATH_SIZE
)
1673 panic("TLB load handler fastpath space exceeded");
1675 resolve_relocs(relocs
, labels
);
1676 printk("Synthesized TLB load handler fastpath (%u instructions).\n",
1677 (unsigned int)(p
- handle_tlbl
));
1683 for (i
= 0; i
< (p
- handle_tlbl
); i
++)
1684 printk("%08x\n", handle_tlbl
[i
]);
1688 flush_icache_range((unsigned long)handle_tlbl
,
1689 (unsigned long)handle_tlbl
+ FASTPATH_SIZE
* sizeof(u32
));
1692 static void __init
build_r4000_tlb_store_handler(void)
1694 u32
*p
= handle_tlbs
;
1695 struct label
*l
= labels
;
1696 struct reloc
*r
= relocs
;
1698 memset(handle_tlbs
, 0, sizeof(handle_tlbs
));
1699 memset(labels
, 0, sizeof(labels
));
1700 memset(relocs
, 0, sizeof(relocs
));
1702 build_r4000_tlbchange_handler_head(&p
, &l
, &r
, K0
, K1
);
1703 build_pte_writable(&p
, &l
, &r
, K0
, K1
, label_nopage_tlbs
);
1704 build_make_write(&p
, &r
, K0
, K1
);
1705 build_r4000_tlbchange_handler_tail(&p
, &l
, &r
, K0
, K1
);
1707 l_nopage_tlbs(&l
, p
);
1708 i_j(&p
, (unsigned long)tlb_do_page_fault_1
& 0x0fffffff);
1711 if ((p
- handle_tlbs
) > FASTPATH_SIZE
)
1712 panic("TLB store handler fastpath space exceeded");
1714 resolve_relocs(relocs
, labels
);
1715 printk("Synthesized TLB store handler fastpath (%u instructions).\n",
1716 (unsigned int)(p
- handle_tlbs
));
1722 for (i
= 0; i
< (p
- handle_tlbs
); i
++)
1723 printk("%08x\n", handle_tlbs
[i
]);
1727 flush_icache_range((unsigned long)handle_tlbs
,
1728 (unsigned long)handle_tlbs
+ FASTPATH_SIZE
* sizeof(u32
));
1731 static void __init
build_r4000_tlb_modify_handler(void)
1733 u32
*p
= handle_tlbm
;
1734 struct label
*l
= labels
;
1735 struct reloc
*r
= relocs
;
1737 memset(handle_tlbm
, 0, sizeof(handle_tlbm
));
1738 memset(labels
, 0, sizeof(labels
));
1739 memset(relocs
, 0, sizeof(relocs
));
1741 build_r4000_tlbchange_handler_head(&p
, &l
, &r
, K0
, K1
);
1742 build_pte_modifiable(&p
, &l
, &r
, K0
, K1
, label_nopage_tlbm
);
1743 /* Present and writable bits set, set accessed and dirty bits. */
1744 build_make_write(&p
, &r
, K0
, K1
);
1745 build_r4000_tlbchange_handler_tail(&p
, &l
, &r
, K0
, K1
);
1747 l_nopage_tlbm(&l
, p
);
1748 i_j(&p
, (unsigned long)tlb_do_page_fault_1
& 0x0fffffff);
1751 if ((p
- handle_tlbm
) > FASTPATH_SIZE
)
1752 panic("TLB modify handler fastpath space exceeded");
1754 resolve_relocs(relocs
, labels
);
1755 printk("Synthesized TLB modify handler fastpath (%u instructions).\n",
1756 (unsigned int)(p
- handle_tlbm
));
1762 for (i
= 0; i
< (p
- handle_tlbm
); i
++)
1763 printk("%08x\n", handle_tlbm
[i
]);
1767 flush_icache_range((unsigned long)handle_tlbm
,
1768 (unsigned long)handle_tlbm
+ FASTPATH_SIZE
* sizeof(u32
));
1771 void __init
build_tlb_refill_handler(void)
1774 * The refill handler is generated per-CPU, multi-node systems
1775 * may have local storage for it. The other handlers are only
1778 static int run_once
= 0;
1780 switch (current_cpu_data
.cputype
) {
1788 build_r3000_tlb_refill_handler();
1790 build_r3000_tlb_load_handler();
1791 build_r3000_tlb_store_handler();
1792 build_r3000_tlb_modify_handler();
1799 panic("No R6000 TLB refill handler yet");
1803 panic("No R8000 TLB refill handler yet");
1807 build_r4000_tlb_refill_handler();
1809 build_r4000_tlb_load_handler();
1810 build_r4000_tlb_store_handler();
1811 build_r4000_tlb_modify_handler();