2 * Copyright (C) 2000,2001,2002,2003,2004 Broadcom Corporation
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
18 #include <linux/kernel.h>
19 #include <linux/init.h>
20 #include <linux/linkage.h>
21 #include <linux/interrupt.h>
22 #include <linux/spinlock.h>
24 #include <linux/slab.h>
25 #include <linux/kernel_stat.h>
27 #include <asm/errno.h>
28 #include <asm/irq_regs.h>
29 #include <asm/signal.h>
30 #include <asm/system.h>
31 #include <asm/ptrace.h>
34 #include <asm/sibyte/bcm1480_regs.h>
35 #include <asm/sibyte/bcm1480_int.h>
36 #include <asm/sibyte/bcm1480_scd.h>
38 #include <asm/sibyte/sb1250_uart.h>
39 #include <asm/sibyte/sb1250.h>
42 * These are the routines that handle all the low level interrupt stuff.
43 * Actions handled here are: initialization of the interrupt map, requesting of
44 * interrupt lines by handlers, dispatching if interrupts to handlers, probing
49 #define shutdown_bcm1480_irq disable_bcm1480_irq
50 static void end_bcm1480_irq(unsigned int irq
);
51 static void enable_bcm1480_irq(unsigned int irq
);
52 static void disable_bcm1480_irq(unsigned int irq
);
53 static unsigned int startup_bcm1480_irq(unsigned int irq
);
54 static void ack_bcm1480_irq(unsigned int irq
);
56 static void bcm1480_set_affinity(unsigned int irq
, cpumask_t mask
);
60 extern unsigned long ht_eoi_space
;
64 #include <asm/gdb-stub.h>
65 extern void breakpoint(void);
67 #ifdef CONFIG_GDB_CONSOLE
68 extern void register_gdb_console(void);
71 /* kgdb is on when configured. Pass "nokgdb" kernel arg to turn it off */
72 static int kgdb_flag
= 1;
73 static int __init
nokgdb(char *str
)
78 __setup("nokgdb", nokgdb
);
80 /* Default to UART1 */
82 #ifdef CONFIG_SIBYTE_SB1250_DUART
83 extern char sb1250_duart_present
[];
87 static struct irq_chip bcm1480_irq_type
= {
88 .typename
= "BCM1480-IMR",
89 .startup
= startup_bcm1480_irq
,
90 .shutdown
= shutdown_bcm1480_irq
,
91 .enable
= enable_bcm1480_irq
,
92 .disable
= disable_bcm1480_irq
,
93 .ack
= ack_bcm1480_irq
,
94 .end
= end_bcm1480_irq
,
96 .set_affinity
= bcm1480_set_affinity
100 /* Store the CPU id (not the logical number) */
101 int bcm1480_irq_owner
[BCM1480_NR_IRQS
];
103 DEFINE_SPINLOCK(bcm1480_imr_lock
);
105 void bcm1480_mask_irq(int cpu
, int irq
)
108 u64 cur_ints
,hl_spacing
;
110 spin_lock_irqsave(&bcm1480_imr_lock
, flags
);
112 if ((irq
>= BCM1480_NR_IRQS_HALF
) && (irq
<= BCM1480_NR_IRQS
)) {
113 hl_spacing
= BCM1480_IMR_HL_SPACING
;
114 irq
-= BCM1480_NR_IRQS_HALF
;
116 cur_ints
= ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(cpu
) + R_BCM1480_IMR_INTERRUPT_MASK_H
+ hl_spacing
));
117 cur_ints
|= (((u64
) 1) << irq
);
118 ____raw_writeq(cur_ints
, IOADDR(A_BCM1480_IMR_MAPPER(cpu
) + R_BCM1480_IMR_INTERRUPT_MASK_H
+ hl_spacing
));
119 spin_unlock_irqrestore(&bcm1480_imr_lock
, flags
);
122 void bcm1480_unmask_irq(int cpu
, int irq
)
125 u64 cur_ints
,hl_spacing
;
127 spin_lock_irqsave(&bcm1480_imr_lock
, flags
);
129 if ((irq
>= BCM1480_NR_IRQS_HALF
) && (irq
<= BCM1480_NR_IRQS
)) {
130 hl_spacing
= BCM1480_IMR_HL_SPACING
;
131 irq
-= BCM1480_NR_IRQS_HALF
;
133 cur_ints
= ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(cpu
) + R_BCM1480_IMR_INTERRUPT_MASK_H
+ hl_spacing
));
134 cur_ints
&= ~(((u64
) 1) << irq
);
135 ____raw_writeq(cur_ints
, IOADDR(A_BCM1480_IMR_MAPPER(cpu
) + R_BCM1480_IMR_INTERRUPT_MASK_H
+ hl_spacing
));
136 spin_unlock_irqrestore(&bcm1480_imr_lock
, flags
);
140 static void bcm1480_set_affinity(unsigned int irq
, cpumask_t mask
)
142 int i
= 0, old_cpu
, cpu
, int_on
, k
;
144 struct irq_desc
*desc
= irq_desc
+ irq
;
146 unsigned int irq_dirty
;
149 if (next_cpu(i
, mask
) <= NR_CPUS
) {
150 printk("attempted to set irq affinity for irq %d to multiple CPUs\n", irq
);
154 /* Convert logical CPU to physical CPU */
155 cpu
= cpu_logical_map(i
);
157 /* Protect against other affinity changers and IMR manipulation */
158 spin_lock_irqsave(&desc
->lock
, flags
);
159 spin_lock(&bcm1480_imr_lock
);
161 /* Swizzle each CPU's IMR (but leave the IP selection alone) */
162 old_cpu
= bcm1480_irq_owner
[irq
];
164 if ((irq_dirty
>= BCM1480_NR_IRQS_HALF
) && (irq_dirty
<= BCM1480_NR_IRQS
)) {
165 irq_dirty
-= BCM1480_NR_IRQS_HALF
;
168 for (k
=0; k
<2; k
++) { /* Loop through high and low interrupt mask register */
169 cur_ints
= ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(old_cpu
) + R_BCM1480_IMR_INTERRUPT_MASK_H
+ (k
*BCM1480_IMR_HL_SPACING
)));
170 int_on
= !(cur_ints
& (((u64
) 1) << irq_dirty
));
172 /* If it was on, mask it */
173 cur_ints
|= (((u64
) 1) << irq_dirty
);
174 ____raw_writeq(cur_ints
, IOADDR(A_BCM1480_IMR_MAPPER(old_cpu
) + R_BCM1480_IMR_INTERRUPT_MASK_H
+ (k
*BCM1480_IMR_HL_SPACING
)));
176 bcm1480_irq_owner
[irq
] = cpu
;
178 /* unmask for the new CPU */
179 cur_ints
= ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(cpu
) + R_BCM1480_IMR_INTERRUPT_MASK_H
+ (k
*BCM1480_IMR_HL_SPACING
)));
180 cur_ints
&= ~(((u64
) 1) << irq_dirty
);
181 ____raw_writeq(cur_ints
, IOADDR(A_BCM1480_IMR_MAPPER(cpu
) + R_BCM1480_IMR_INTERRUPT_MASK_H
+ (k
*BCM1480_IMR_HL_SPACING
)));
184 spin_unlock(&bcm1480_imr_lock
);
185 spin_unlock_irqrestore(&desc
->lock
, flags
);
190 /*****************************************************************************/
192 static unsigned int startup_bcm1480_irq(unsigned int irq
)
194 bcm1480_unmask_irq(bcm1480_irq_owner
[irq
], irq
);
196 return 0; /* never anything pending */
200 static void disable_bcm1480_irq(unsigned int irq
)
202 bcm1480_mask_irq(bcm1480_irq_owner
[irq
], irq
);
205 static void enable_bcm1480_irq(unsigned int irq
)
207 bcm1480_unmask_irq(bcm1480_irq_owner
[irq
], irq
);
211 static void ack_bcm1480_irq(unsigned int irq
)
214 unsigned int irq_dirty
;
218 * If the interrupt was an HT interrupt, now is the time to
219 * clear it. NOTE: we assume the HT bridge was set up to
220 * deliver the interrupts to all CPUs (which makes affinity
221 * changing easier for us)
224 if ((irq_dirty
>= BCM1480_NR_IRQS_HALF
) && (irq_dirty
<= BCM1480_NR_IRQS
)) {
225 irq_dirty
-= BCM1480_NR_IRQS_HALF
;
227 for (k
=0; k
<2; k
++) { /* Loop through high and low LDT interrupts */
228 pending
= __raw_readq(IOADDR(A_BCM1480_IMR_REGISTER(bcm1480_irq_owner
[irq
],
229 R_BCM1480_IMR_LDT_INTERRUPT_H
+ (k
*BCM1480_IMR_HL_SPACING
))));
230 pending
&= ((u64
)1 << (irq_dirty
));
234 for (i
=0; i
<NR_CPUS
; i
++) {
236 * Clear for all CPUs so an affinity switch
237 * doesn't find an old status
239 __raw_writeq(pending
, IOADDR(A_BCM1480_IMR_REGISTER(cpu_logical_map(i
),
240 R_BCM1480_IMR_LDT_INTERRUPT_CLR_H
+ (k
*BCM1480_IMR_HL_SPACING
))));
243 __raw_writeq(pending
, IOADDR(A_BCM1480_IMR_REGISTER(0, R_BCM1480_IMR_LDT_INTERRUPT_CLR_H
+ (k
*BCM1480_IMR_HL_SPACING
))));
247 * Generate EOI. For Pass 1 parts, EOI is a nop. For
248 * Pass 2, the LDT world may be edge-triggered, but
249 * this EOI shouldn't hurt. If they are
250 * level-sensitive, the EOI is required.
254 *(uint32_t *)(ht_eoi_space
+(irq
<<16)+(7<<2)) = 0;
258 bcm1480_mask_irq(bcm1480_irq_owner
[irq
], irq
);
262 static void end_bcm1480_irq(unsigned int irq
)
264 if (!(irq_desc
[irq
].status
& (IRQ_DISABLED
| IRQ_INPROGRESS
))) {
265 bcm1480_unmask_irq(bcm1480_irq_owner
[irq
], irq
);
270 void __init
init_bcm1480_irqs(void)
274 for (i
= 0; i
< NR_IRQS
; i
++) {
275 irq_desc
[i
].status
= IRQ_DISABLED
;
276 irq_desc
[i
].action
= 0;
277 irq_desc
[i
].depth
= 1;
278 if (i
< BCM1480_NR_IRQS
) {
279 irq_desc
[i
].chip
= &bcm1480_irq_type
;
280 bcm1480_irq_owner
[i
] = 0;
282 irq_desc
[i
].chip
= &no_irq_chip
;
288 static irqreturn_t
bcm1480_dummy_handler(int irq
, void *dev_id
)
293 static struct irqaction bcm1480_dummy_action
= {
294 .handler
= bcm1480_dummy_handler
,
296 .mask
= CPU_MASK_NONE
,
297 .name
= "bcm1480-private",
302 int bcm1480_steal_irq(int irq
)
304 struct irq_desc
*desc
= irq_desc
+ irq
;
308 if (irq
>= BCM1480_NR_IRQS
)
311 spin_lock_irqsave(&desc
->lock
,flags
);
312 /* Don't allow sharing at all for these */
313 if (desc
->action
!= NULL
)
316 desc
->action
= &bcm1480_dummy_action
;
319 spin_unlock_irqrestore(&desc
->lock
,flags
);
324 * init_IRQ is called early in the boot sequence from init/main.c. It
325 * is responsible for setting up the interrupt mapper and installing the
326 * handler that will be responsible for dispatching interrupts to the
330 * For now, map all interrupts to IP[2]. We could save
331 * some cycles by parceling out system interrupts to different
332 * IP lines, but keep it simple for bringup. We'll also direct
333 * all interrupts to a single CPU; we should probably route
334 * PCI and LDT to one cpu and everything else to the other
335 * to balance the load a bit.
337 * On the second cpu, everything is set to IP5, which is
338 * ignored, EXCEPT the mailbox interrupt. That one is
339 * set to IP[2] so it is handled. This is needed so we
340 * can do cross-cpu function calls, as requred by SMP
343 #define IMR_IP2_VAL K_BCM1480_INT_MAP_I0
344 #define IMR_IP3_VAL K_BCM1480_INT_MAP_I1
345 #define IMR_IP4_VAL K_BCM1480_INT_MAP_I2
346 #define IMR_IP5_VAL K_BCM1480_INT_MAP_I3
347 #define IMR_IP6_VAL K_BCM1480_INT_MAP_I4
349 void __init
arch_init_irq(void)
354 unsigned int imask
= STATUSF_IP4
| STATUSF_IP3
| STATUSF_IP2
|
355 STATUSF_IP1
| STATUSF_IP0
;
357 /* Default everything to IP2 */
358 /* Start with _high registers which has no bit 0 interrupt source */
359 for (i
= 1; i
< BCM1480_NR_IRQS_HALF
; i
++) { /* was I0 */
360 for (cpu
= 0; cpu
< 4; cpu
++) {
361 __raw_writeq(IMR_IP2_VAL
,
362 IOADDR(A_BCM1480_IMR_REGISTER(cpu
,
363 R_BCM1480_IMR_INTERRUPT_MAP_BASE_H
) + (i
<< 3)));
367 /* Now do _low registers */
368 for (i
= 0; i
< BCM1480_NR_IRQS_HALF
; i
++) {
369 for (cpu
= 0; cpu
< 4; cpu
++) {
370 __raw_writeq(IMR_IP2_VAL
,
371 IOADDR(A_BCM1480_IMR_REGISTER(cpu
,
372 R_BCM1480_IMR_INTERRUPT_MAP_BASE_L
) + (i
<< 3)));
379 * Map the high 16 bits of mailbox_0 registers to IP[3], for
383 for (cpu
= 0; cpu
< 4; cpu
++) {
384 __raw_writeq(IMR_IP3_VAL
, IOADDR(A_BCM1480_IMR_REGISTER(cpu
, R_BCM1480_IMR_INTERRUPT_MAP_BASE_H
) +
385 (K_BCM1480_INT_MBOX_0_0
<< 3)));
389 /* Clear the mailboxes. The firmware may leave them dirty */
390 for (cpu
= 0; cpu
< 4; cpu
++) {
391 __raw_writeq(0xffffffffffffffffULL
,
392 IOADDR(A_BCM1480_IMR_REGISTER(cpu
, R_BCM1480_IMR_MAILBOX_0_CLR_CPU
)));
393 __raw_writeq(0xffffffffffffffffULL
,
394 IOADDR(A_BCM1480_IMR_REGISTER(cpu
, R_BCM1480_IMR_MAILBOX_1_CLR_CPU
)));
398 /* Mask everything except the high 16 bit of mailbox_0 registers for all cpus */
399 tmp
= ~((u64
) 0) ^ ( (((u64
) 1) << K_BCM1480_INT_MBOX_0_0
));
400 for (cpu
= 0; cpu
< 4; cpu
++) {
401 __raw_writeq(tmp
, IOADDR(A_BCM1480_IMR_REGISTER(cpu
, R_BCM1480_IMR_INTERRUPT_MASK_H
)));
404 for (cpu
= 0; cpu
< 4; cpu
++) {
405 __raw_writeq(tmp
, IOADDR(A_BCM1480_IMR_REGISTER(cpu
, R_BCM1480_IMR_INTERRUPT_MASK_L
)));
408 bcm1480_steal_irq(K_BCM1480_INT_MBOX_0_0
);
411 * Note that the timer interrupts are also mapped, but this is
412 * done in bcm1480_time_init(). Also, the profiling driver
413 * does its own management of IP7.
417 imask
|= STATUSF_IP6
;
419 /* Enable necessary IPs, disable the rest */
420 change_c0_status(ST0_IM
, imask
);
424 kgdb_irq
= K_BCM1480_INT_UART_0
+ kgdb_port
;
426 #ifdef CONFIG_SIBYTE_SB1250_DUART
427 sb1250_duart_present
[kgdb_port
] = 0;
429 /* Setup uart 1 settings, mapper */
431 __raw_writeq(M_DUART_IMR_BRK
, IO_SPACE_BASE
+ A_DUART_IMRREG(kgdb_port
));
433 bcm1480_steal_irq(kgdb_irq
);
434 __raw_writeq(IMR_IP6_VAL
,
435 IO_SPACE_BASE
+ A_BCM1480_IMR_REGISTER(0, R_BCM1480_IMR_INTERRUPT_MAP_BASE_H
) +
437 bcm1480_unmask_irq(0, kgdb_irq
);
439 #ifdef CONFIG_GDB_CONSOLE
440 register_gdb_console();
442 prom_printf("Waiting for GDB on UART port %d\n", kgdb_port
);
451 #include <linux/delay.h>
453 #define duart_out(reg, val) csr_out32(val, IOADDR(A_DUART_CHANREG(kgdb_port,reg)))
454 #define duart_in(reg) csr_in32(IOADDR(A_DUART_CHANREG(kgdb_port,reg)))
456 static void bcm1480_kgdb_interrupt(void)
459 * Clear break-change status (allow some time for the remote
460 * host to stop the break, since we would see another
461 * interrupt on the end-of-break too)
463 kstat
.irqs
[smp_processor_id()][kgdb_irq
]++;
465 duart_out(R_DUART_CMD
, V_DUART_MISC_CMD_RESET_BREAK_INT
|
466 M_DUART_RX_EN
| M_DUART_TX_EN
);
467 set_async_breakpoint(&get_irq_regs()->cp0_epc
);
470 #endif /* CONFIG_KGDB */
472 extern void bcm1480_timer_interrupt(void);
473 extern void bcm1480_mailbox_interrupt(void);
475 asmlinkage
void plat_irq_dispatch(void)
477 unsigned int pending
;
479 #ifdef CONFIG_SIBYTE_BCM1480_PROF
480 /* Set compare to count to silence count/compare timer interrupts */
481 write_c0_compare(read_c0_count());
484 pending
= read_c0_cause() & read_c0_status();
486 #ifdef CONFIG_SIBYTE_BCM1480_PROF
487 if (pending
& CAUSEF_IP7
) /* Cpu performance counter interrupt */
492 if (pending
& CAUSEF_IP4
)
493 bcm1480_timer_interrupt();
496 else if (pending
& CAUSEF_IP3
)
497 bcm1480_mailbox_interrupt();
501 else if (pending
& CAUSEF_IP6
)
502 bcm1480_kgdb_interrupt(); /* KGDB (uart 1) */
505 else if (pending
& CAUSEF_IP2
) {
506 unsigned long long mask_h
, mask_l
;
510 * Default...we've hit an IP[2] interrupt, which means we've
511 * got to check the 1480 interrupt registers to figure out what
512 * to do. Need to detect which CPU we're on, now that
513 * smp_affinity is supported.
515 base
= A_BCM1480_IMR_MAPPER(smp_processor_id());
516 mask_h
= __raw_readq(
517 IOADDR(base
+ R_BCM1480_IMR_INTERRUPT_STATUS_BASE_H
));
518 mask_l
= __raw_readq(
519 IOADDR(base
+ R_BCM1480_IMR_INTERRUPT_STATUS_BASE_L
));
523 do_IRQ(fls64(mask_h
) - 1);
525 do_IRQ(63 + fls64(mask_l
));