drivers/pci/msi.c

   1 /*
   2  * File:        msi.c
   3  * Purpose:     PCI Message Signaled Interrupt (MSI)
   4  *
   5  * Copyright (C) 2003-2004 Intel
   6  * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
   7  */
   8
   9 #include <linux/err.h>
  10 #include <linux/mm.h>
  11 #include <linux/irq.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/init.h>
  14 #include <linux/ioport.h>
  15 #include <linux/smp_lock.h>
  16 #include <linux/pci.h>
  17 #include <linux/proc_fs.h>
  18 #include <linux/msi.h>
  19
  20 #include <asm/errno.h>
  21 #include <asm/io.h>
  22 #include <asm/smp.h>
  23
  24 #include "pci.h"
  25 #include "msi.h"
  26
  27 static DEFINE_SPINLOCK(msi_lock);
  28 static struct msi_desc* msi_desc[NR_IRQS] = { [0 ... NR_IRQS-1] = NULL };
  29 static struct kmem_cache* msi_cachep;
  30
  31 static int pci_msi_enable = 1;
  32
  33 static int msi_cache_init(void)
  34 {
  35         msi_cachep = kmem_cache_create("msi_cache", sizeof(struct msi_desc),
  36                                         0, SLAB_HWCACHE_ALIGN, NULL, NULL);
  37         if (!msi_cachep)
  38                 return -ENOMEM;
  39
  40         return 0;
  41 }
  42
  43 static void msi_set_mask_bit(unsigned int irq, int flag)
  44 {
  45         struct msi_desc *entry;
  46
  47         entry = msi_desc[irq];
  48         BUG_ON(!entry || !entry->dev);
  49         switch (entry->msi_attrib.type) {
  50         case PCI_CAP_ID_MSI:
  51                 if (entry->msi_attrib.maskbit) {
  52                         int pos;
  53                         u32 mask_bits;
  54
  55                         pos = (long)entry->mask_base;
  56                         pci_read_config_dword(entry->dev, pos, &mask_bits);
  57                         mask_bits &= ~(1);
  58                         mask_bits |= flag;
  59                         pci_write_config_dword(entry->dev, pos, mask_bits);
  60                 }
  61                 break;
  62         case PCI_CAP_ID_MSIX:
  63         {
  64                 int offset = entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
  65                         PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET;
  66                 writel(flag, entry->mask_base + offset);
  67                 break;
  68         }
  69         default:
  70                 BUG();
  71                 break;
  72         }
  73 }
  74
  75 void read_msi_msg(unsigned int irq, struct msi_msg *msg)
  76 {
  77         struct msi_desc *entry = get_irq_data(irq);
  78         switch(entry->msi_attrib.type) {
  79         case PCI_CAP_ID_MSI:
  80         {
  81                 struct pci_dev *dev = entry->dev;
  82                 int pos = entry->msi_attrib.pos;
  83                 u16 data;
  84
  85                 pci_read_config_dword(dev, msi_lower_address_reg(pos),
  86                                         &msg->address_lo);
  87                 if (entry->msi_attrib.is_64) {
  88                         pci_read_config_dword(dev, msi_upper_address_reg(pos),
  89                                                 &msg->address_hi);
  90                         pci_read_config_word(dev, msi_data_reg(pos, 1), &data);
  91                 } else {
  92                         msg->address_hi = 0;
  93                         pci_read_config_word(dev, msi_data_reg(pos, 1), &data);
  94                 }
  95                 msg->data = data;
  96                 break;
  97         }
  98         case PCI_CAP_ID_MSIX:
  99         {
 100                 void __iomem *base;
 101                 base = entry->mask_base +
 102                         entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
 103
 104                 msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET);
 105                 msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET);
 106                 msg->data = readl(base + PCI_MSIX_ENTRY_DATA_OFFSET);
 107                 break;
 108         }
 109         default:
 110                 BUG();
 111         }
 112 }
 113
 114 void write_msi_msg(unsigned int irq, struct msi_msg *msg)
 115 {
 116         struct msi_desc *entry = get_irq_data(irq);
 117         switch (entry->msi_attrib.type) {
 118         case PCI_CAP_ID_MSI:
 119         {
 120                 struct pci_dev *dev = entry->dev;
 121                 int pos = entry->msi_attrib.pos;
 122
 123                 pci_write_config_dword(dev, msi_lower_address_reg(pos),
 124                                         msg->address_lo);
 125                 if (entry->msi_attrib.is_64) {
 126                         pci_write_config_dword(dev, msi_upper_address_reg(pos),
 127                                                 msg->address_hi);
 128                         pci_write_config_word(dev, msi_data_reg(pos, 1),
 129                                                 msg->data);
 130                 } else {
 131                         pci_write_config_word(dev, msi_data_reg(pos, 0),
 132                                                 msg->data);
 133                 }
 134                 break;
 135         }
 136         case PCI_CAP_ID_MSIX:
 137         {
 138                 void __iomem *base;
 139                 base = entry->mask_base +
 140                         entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
 141
 142                 writel(msg->address_lo,
 143                         base + PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET);
 144                 writel(msg->address_hi,
 145                         base + PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET);
 146                 writel(msg->data, base + PCI_MSIX_ENTRY_DATA_OFFSET);
 147                 break;
 148         }
 149         default:
 150                 BUG();
 151         }
 152 }
 153
 154 void mask_msi_irq(unsigned int irq)
 155 {
 156         msi_set_mask_bit(irq, 1);
 157 }
 158
 159 void unmask_msi_irq(unsigned int irq)
 160 {
 161         msi_set_mask_bit(irq, 0);
 162 }
 163
 164 static int msi_free_irq(struct pci_dev* dev, int irq);
 165
 166 static int msi_init(void)
 167 {
 168         static int status = -ENOMEM;
 169
 170         if (!status)
 171                 return status;
 172
 173         status = msi_cache_init();
 174         if (status < 0) {
 175                 pci_msi_enable = 0;
 176                 printk(KERN_WARNING "PCI: MSI cache init failed\n");
 177                 return status;
 178         }
 179
 180         return status;
 181 }
 182
 183 static struct msi_desc* alloc_msi_entry(void)
 184 {
 185         struct msi_desc *entry;
 186
 187         entry = kmem_cache_zalloc(msi_cachep, GFP_KERNEL);
 188         if (!entry)
 189                 return NULL;
 190
 191         entry->link.tail = entry->link.head = 0;        /* single message */
 192         entry->dev = NULL;
 193
 194         return entry;
 195 }
 196
 197 static void attach_msi_entry(struct msi_desc *entry, int irq)
 198 {
 199         unsigned long flags;
 200
 201         spin_lock_irqsave(&msi_lock, flags);
 202         msi_desc[irq] = entry;
 203         spin_unlock_irqrestore(&msi_lock, flags);
 204 }
 205
 206 static int create_msi_irq(void)
 207 {
 208         struct msi_desc *entry;
 209         int irq;
 210
 211         entry = alloc_msi_entry();
 212         if (!entry)
 213                 return -ENOMEM;
 214
 215         irq = create_irq();
 216         if (irq < 0) {
 217                 kmem_cache_free(msi_cachep, entry);
 218                 return -EBUSY;
 219         }
 220
 221         set_irq_data(irq, entry);
 222
 223         return irq;
 224 }
 225
 226 static void destroy_msi_irq(unsigned int irq)
 227 {
 228         struct msi_desc *entry;
 229
 230         entry = get_irq_data(irq);
 231         set_irq_chip(irq, NULL);
 232         set_irq_data(irq, NULL);
 233         destroy_irq(irq);
 234         kmem_cache_free(msi_cachep, entry);
 235 }
 236
 237 static void enable_msi_mode(struct pci_dev *dev, int pos, int type)
 238 {
 239         u16 control;
 240
 241         pci_read_config_word(dev, msi_control_reg(pos), &control);
 242         if (type == PCI_CAP_ID_MSI) {
 243                 /* Set enabled bits to single MSI & enable MSI_enable bit */
 244                 msi_enable(control, 1);
 245                 pci_write_config_word(dev, msi_control_reg(pos), control);
 246                 dev->msi_enabled = 1;
 247         } else {
 248                 msix_enable(control);
 249                 pci_write_config_word(dev, msi_control_reg(pos), control);
 250                 dev->msix_enabled = 1;
 251         }
 252
 253         pci_intx(dev, 0);  /* disable intx */
 254 }
 255
 256 void disable_msi_mode(struct pci_dev *dev, int pos, int type)
 257 {
 258         u16 control;
 259
 260         pci_read_config_word(dev, msi_control_reg(pos), &control);
 261         if (type == PCI_CAP_ID_MSI) {
 262                 /* Set enabled bits to single MSI & enable MSI_enable bit */
 263                 msi_disable(control);
 264                 pci_write_config_word(dev, msi_control_reg(pos), control);
 265                 dev->msi_enabled = 0;
 266         } else {
 267                 msix_disable(control);
 268                 pci_write_config_word(dev, msi_control_reg(pos), control);
 269                 dev->msix_enabled = 0;
 270         }
 271
 272         pci_intx(dev, 1);  /* enable intx */
 273 }
 274
 275 static int msi_lookup_irq(struct pci_dev *dev, int type)
 276 {
 277         int irq;
 278         unsigned long flags;
 279
 280         spin_lock_irqsave(&msi_lock, flags);
 281         for (irq = 0; irq < NR_IRQS; irq++) {
 282                 if (!msi_desc[irq] || msi_desc[irq]->dev != dev ||
 283                         msi_desc[irq]->msi_attrib.type != type ||
 284                         msi_desc[irq]->msi_attrib.default_irq != dev->irq)
 285                         continue;
 286                 spin_unlock_irqrestore(&msi_lock, flags);
 287                 /* This pre-assigned MSI irq for this device
 288                    already exists. Override dev->irq with this irq */
 289                 dev->irq = irq;
 290                 return 0;
 291         }
 292         spin_unlock_irqrestore(&msi_lock, flags);
 293
 294         return -EACCES;
 295 }
 296
 297 #ifdef CONFIG_PM
 298 static int __pci_save_msi_state(struct pci_dev *dev)
 299 {
 300         int pos, i = 0;
 301         u16 control;
 302         struct pci_cap_saved_state *save_state;
 303         u32 *cap;
 304
 305         pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
 306         if (pos <= 0 || dev->no_msi)
 307                 return 0;
 308
 309         pci_read_config_word(dev, msi_control_reg(pos), &control);
 310         if (!(control & PCI_MSI_FLAGS_ENABLE))
 311                 return 0;
 312
 313         save_state = kzalloc(sizeof(struct pci_cap_saved_state) + sizeof(u32) * 5,
 314                 GFP_KERNEL);
 315         if (!save_state) {
 316                 printk(KERN_ERR "Out of memory in pci_save_msi_state\n");
 317                 return -ENOMEM;
 318         }
 319         cap = &save_state->data[0];
 320
 321         pci_read_config_dword(dev, pos, &cap[i++]);
 322         control = cap[0] >> 16;
 323         pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, &cap[i++]);
 324         if (control & PCI_MSI_FLAGS_64BIT) {
 325                 pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, &cap[i++]);
 326                 pci_read_config_dword(dev, pos + PCI_MSI_DATA_64, &cap[i++]);
 327         } else
 328                 pci_read_config_dword(dev, pos + PCI_MSI_DATA_32, &cap[i++]);
 329         if (control & PCI_MSI_FLAGS_MASKBIT)
 330                 pci_read_config_dword(dev, pos + PCI_MSI_MASK_BIT, &cap[i++]);
 331         save_state->cap_nr = PCI_CAP_ID_MSI;
 332         pci_add_saved_cap(dev, save_state);
 333         return 0;
 334 }
 335
 336 static void __pci_restore_msi_state(struct pci_dev *dev)
 337 {
 338         int i = 0, pos;
 339         u16 control;
 340         struct pci_cap_saved_state *save_state;
 341         u32 *cap;
 342
 343         save_state = pci_find_saved_cap(dev, PCI_CAP_ID_MSI);
 344         pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
 345         if (!save_state || pos <= 0)
 346                 return;
 347         cap = &save_state->data[0];
 348
 349         control = cap[i++] >> 16;
 350         pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, cap[i++]);
 351         if (control & PCI_MSI_FLAGS_64BIT) {
 352                 pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, cap[i++]);
 353                 pci_write_config_dword(dev, pos + PCI_MSI_DATA_64, cap[i++]);
 354         } else
 355                 pci_write_config_dword(dev, pos + PCI_MSI_DATA_32, cap[i++]);
 356         if (control & PCI_MSI_FLAGS_MASKBIT)
 357                 pci_write_config_dword(dev, pos + PCI_MSI_MASK_BIT, cap[i++]);
 358         pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
 359         enable_msi_mode(dev, pos, PCI_CAP_ID_MSI);
 360         pci_remove_saved_cap(save_state);
 361         kfree(save_state);
 362 }
 363
 364 static int __pci_save_msix_state(struct pci_dev *dev)
 365 {
 366         int pos;
 367         int temp;
 368         int irq, head, tail = 0;
 369         u16 control;
 370         struct pci_cap_saved_state *save_state;
 371
 372         pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
 373         if (pos <= 0 || dev->no_msi)
 374                 return 0;
 375
 376         /* save the capability */
 377         pci_read_config_word(dev, msi_control_reg(pos), &control);
 378         if (!(control & PCI_MSIX_FLAGS_ENABLE))
 379                 return 0;
 380         save_state = kzalloc(sizeof(struct pci_cap_saved_state) + sizeof(u16),
 381                 GFP_KERNEL);
 382         if (!save_state) {
 383                 printk(KERN_ERR "Out of memory in pci_save_msix_state\n");
 384                 return -ENOMEM;
 385         }
 386         *((u16 *)&save_state->data[0]) = control;
 387
 388         /* save the table */
 389         temp = dev->irq;
 390         if (msi_lookup_irq(dev, PCI_CAP_ID_MSIX)) {
 391                 kfree(save_state);
 392                 return -EINVAL;
 393         }
 394
 395         irq = head = dev->irq;
 396         while (head != tail) {
 397                 struct msi_desc *entry;
 398
 399                 entry = msi_desc[irq];
 400                 read_msi_msg(irq, &entry->msg_save);
 401
 402                 tail = msi_desc[irq]->link.tail;
 403                 irq = tail;
 404         }
 405         dev->irq = temp;
 406
 407         save_state->cap_nr = PCI_CAP_ID_MSIX;
 408         pci_add_saved_cap(dev, save_state);
 409         return 0;
 410 }
 411
 412 int pci_save_msi_state(struct pci_dev *dev)
 413 {
 414         int rc;
 415
 416         rc = __pci_save_msi_state(dev);
 417         if (rc)
 418                 return rc;
 419
 420         rc = __pci_save_msix_state(dev);
 421
 422         return rc;
 423 }
 424
 425 static void __pci_restore_msix_state(struct pci_dev *dev)
 426 {
 427         u16 save;
 428         int pos;
 429         int irq, head, tail = 0;
 430         struct msi_desc *entry;
 431         int temp;
 432         struct pci_cap_saved_state *save_state;
 433
 434         save_state = pci_find_saved_cap(dev, PCI_CAP_ID_MSIX);
 435         if (!save_state)
 436                 return;
 437         save = *((u16 *)&save_state->data[0]);
 438         pci_remove_saved_cap(save_state);
 439         kfree(save_state);
 440
 441         pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
 442         if (pos <= 0)
 443                 return;
 444
 445         /* route the table */
 446         temp = dev->irq;
 447         if (msi_lookup_irq(dev, PCI_CAP_ID_MSIX))
 448                 return;
 449         irq = head = dev->irq;
 450         while (head != tail) {
 451                 entry = msi_desc[irq];
 452                 write_msi_msg(irq, &entry->msg_save);
 453
 454                 tail = msi_desc[irq]->link.tail;
 455                 irq = tail;
 456         }
 457         dev->irq = temp;
 458
 459         pci_write_config_word(dev, msi_control_reg(pos), save);
 460         enable_msi_mode(dev, pos, PCI_CAP_ID_MSIX);
 461 }
 462
 463 void pci_restore_msi_state(struct pci_dev *dev)
 464 {
 465         __pci_restore_msi_state(dev);
 466         __pci_restore_msix_state(dev);
 467 }
 468 #endif  /* CONFIG_PM */
 469
 470 /**
 471  * msi_capability_init - configure device's MSI capability structure
 472  * @dev: pointer to the pci_dev data structure of MSI device function
 473  *
 474  * Setup the MSI capability structure of device function with a single
 475  * MSI irq, regardless of device function is capable of handling
 476  * multiple messages. A return of zero indicates the successful setup
 477  * of an entry zero with the new MSI irq or non-zero for otherwise.
 478  **/
 479 static int msi_capability_init(struct pci_dev *dev)
 480 {
 481         int status;
 482         struct msi_desc *entry;
 483         int pos, irq;
 484         u16 control;
 485
 486         pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
 487         pci_read_config_word(dev, msi_control_reg(pos), &control);
 488         /* MSI Entry Initialization */
 489         irq = create_msi_irq();
 490         if (irq < 0)
 491                 return irq;
 492
 493         entry = get_irq_data(irq);
 494         entry->link.head = irq;
 495         entry->link.tail = irq;
 496         entry->msi_attrib.type = PCI_CAP_ID_MSI;
 497         entry->msi_attrib.is_64 = is_64bit_address(control);
 498         entry->msi_attrib.entry_nr = 0;
 499         entry->msi_attrib.maskbit = is_mask_bit_support(control);
 500         entry->msi_attrib.default_irq = dev->irq;       /* Save IOAPIC IRQ */
 501         entry->msi_attrib.pos = pos;
 502         if (is_mask_bit_support(control)) {
 503                 entry->mask_base = (void __iomem *)(long)msi_mask_bits_reg(pos,
 504                                 is_64bit_address(control));
 505         }
 506         entry->dev = dev;
 507         if (entry->msi_attrib.maskbit) {
 508                 unsigned int maskbits, temp;
 509                 /* All MSIs are unmasked by default, Mask them all */
 510                 pci_read_config_dword(dev,
 511                         msi_mask_bits_reg(pos, is_64bit_address(control)),
 512                         &maskbits);
 513                 temp = (1 << multi_msi_capable(control));
 514                 temp = ((temp - 1) & ~temp);
 515                 maskbits |= temp;
 516                 pci_write_config_dword(dev,
 517                         msi_mask_bits_reg(pos, is_64bit_address(control)),
 518                         maskbits);
 519         }
 520         /* Configure MSI capability structure */
 521         status = arch_setup_msi_irq(irq, dev);
 522         if (status < 0) {
 523                 destroy_msi_irq(irq);
 524                 return status;
 525         }
 526
 527         attach_msi_entry(entry, irq);
 528         /* Set MSI enabled bits  */
 529         enable_msi_mode(dev, pos, PCI_CAP_ID_MSI);
 530
 531         dev->irq = irq;
 532         return 0;
 533 }
 534
 535 /**
 536  * msix_capability_init - configure device's MSI-X capability
 537  * @dev: pointer to the pci_dev data structure of MSI-X device function
 538  * @entries: pointer to an array of struct msix_entry entries
 539  * @nvec: number of @entries
 540  *
 541  * Setup the MSI-X capability structure of device function with a
 542  * single MSI-X irq. A return of zero indicates the successful setup of
 543  * requested MSI-X entries with allocated irqs or non-zero for otherwise.
 544  **/
 545 static int msix_capability_init(struct pci_dev *dev,
 546                                 struct msix_entry *entries, int nvec)
 547 {
 548         struct msi_desc *head = NULL, *tail = NULL, *entry = NULL;
 549         int status;
 550         int irq, pos, i, j, nr_entries, temp = 0;
 551         unsigned long phys_addr;
 552         u32 table_offset;
 553         u16 control;
 554         u8 bir;
 555         void __iomem *base;
 556
 557         pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
 558         /* Request & Map MSI-X table region */
 559         pci_read_config_word(dev, msi_control_reg(pos), &control);
 560         nr_entries = multi_msix_capable(control);
 561
 562         pci_read_config_dword(dev, msix_table_offset_reg(pos), &table_offset);
 563         bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK);
 564         table_offset &= ~PCI_MSIX_FLAGS_BIRMASK;
 565         phys_addr = pci_resource_start (dev, bir) + table_offset;
 566         base = ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE);
 567         if (base == NULL)
 568                 return -ENOMEM;
 569
 570         /* MSI-X Table Initialization */
 571         for (i = 0; i < nvec; i++) {
 572                 irq = create_msi_irq();
 573                 if (irq < 0)
 574                         break;
 575
 576                 entry = get_irq_data(irq);
 577                 j = entries[i].entry;
 578                 entries[i].vector = irq;
 579                 entry->msi_attrib.type = PCI_CAP_ID_MSIX;
 580                 entry->msi_attrib.is_64 = 1;
 581                 entry->msi_attrib.entry_nr = j;
 582                 entry->msi_attrib.maskbit = 1;
 583                 entry->msi_attrib.default_irq = dev->irq;
 584                 entry->msi_attrib.pos = pos;
 585                 entry->dev = dev;
 586                 entry->mask_base = base;
 587                 if (!head) {
 588                         entry->link.head = irq;
 589                         entry->link.tail = irq;
 590                         head = entry;
 591                 } else {
 592                         entry->link.head = temp;
 593                         entry->link.tail = tail->link.tail;
 594                         tail->link.tail = irq;
 595                         head->link.head = irq;
 596                 }
 597                 temp = irq;
 598                 tail = entry;
 599                 /* Configure MSI-X capability structure */
 600                 status = arch_setup_msi_irq(irq, dev);
 601                 if (status < 0) {
 602                         destroy_msi_irq(irq);
 603                         break;
 604                 }
 605
 606                 attach_msi_entry(entry, irq);
 607         }
 608         if (i != nvec) {
 609                 int avail = i - 1;
 610                 i--;
 611                 for (; i >= 0; i--) {
 612                         irq = (entries + i)->vector;
 613                         msi_free_irq(dev, irq);
 614                         (entries + i)->vector = 0;
 615                 }
 616                 /* If we had some success report the number of irqs
 617                  * we succeeded in setting up.
 618                  */
 619                 if (avail <= 0)
 620                         avail = -EBUSY;
 621                 return avail;
 622         }
 623         /* Set MSI-X enabled bits */
 624         enable_msi_mode(dev, pos, PCI_CAP_ID_MSIX);
 625
 626         return 0;
 627 }
 628
 629 /**
 630  * pci_msi_supported - check whether MSI may be enabled on device
 631  * @dev: pointer to the pci_dev data structure of MSI device function
 632  *
 633  * Look at global flags, the device itself, and its parent busses
 634  * to return 0 if MSI are supported for the device.
 635  **/
 636 static
 637 int pci_msi_supported(struct pci_dev * dev)
 638 {
 639         struct pci_bus *bus;
 640
 641         /* MSI must be globally enabled and supported by the device */
 642         if (!pci_msi_enable || !dev || dev->no_msi)
 643                 return -EINVAL;
 644
 645         /* Any bridge which does NOT route MSI transactions from it's
 646          * secondary bus to it's primary bus must set NO_MSI flag on
 647          * the secondary pci_bus.
 648          * We expect only arch-specific PCI host bus controller driver
 649          * or quirks for specific PCI bridges to be setting NO_MSI.
 650          */
 651         for (bus = dev->bus; bus; bus = bus->parent)
 652                 if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI)
 653                         return -EINVAL;
 654
 655         return 0;
 656 }
 657
 658 /**
 659  * pci_enable_msi - configure device's MSI capability structure
 660  * @dev: pointer to the pci_dev data structure of MSI device function
 661  *
 662  * Setup the MSI capability structure of device function with
 663  * a single MSI irq upon its software driver call to request for
 664  * MSI mode enabled on its hardware device function. A return of zero
 665  * indicates the successful setup of an entry zero with the new MSI
 666  * irq or non-zero for otherwise.
 667  **/
 668 int pci_enable_msi(struct pci_dev* dev)
 669 {
 670         int pos, temp, status;
 671
 672         if (pci_msi_supported(dev) < 0)
 673                 return -EINVAL;
 674
 675         temp = dev->irq;
 676
 677         status = msi_init();
 678         if (status < 0)
 679                 return status;
 680
 681         pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
 682         if (!pos)
 683                 return -EINVAL;
 684
 685         WARN_ON(!msi_lookup_irq(dev, PCI_CAP_ID_MSI));
 686
 687         /* Check whether driver already requested for MSI-X irqs */
 688         pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
 689         if (pos > 0 && !msi_lookup_irq(dev, PCI_CAP_ID_MSIX)) {
 690                         printk(KERN_INFO "PCI: %s: Can't enable MSI.  "
 691                                "Device already has MSI-X irq assigned\n",
 692                                pci_name(dev));
 693                         dev->irq = temp;
 694                         return -EINVAL;
 695         }
 696         status = msi_capability_init(dev);
 697         return status;
 698 }
 699
 700 void pci_disable_msi(struct pci_dev* dev)
 701 {
 702         struct msi_desc *entry;
 703         int pos, default_irq;
 704         u16 control;
 705         unsigned long flags;
 706
 707         if (!pci_msi_enable)
 708                 return;
 709         if (!dev)
 710                 return;
 711
 712         pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
 713         if (!pos)
 714                 return;
 715
 716         pci_read_config_word(dev, msi_control_reg(pos), &control);
 717         if (!(control & PCI_MSI_FLAGS_ENABLE))
 718                 return;
 719
 720         disable_msi_mode(dev, pos, PCI_CAP_ID_MSI);
 721
 722         spin_lock_irqsave(&msi_lock, flags);
 723         entry = msi_desc[dev->irq];
 724         if (!entry || !entry->dev || entry->msi_attrib.type != PCI_CAP_ID_MSI) {
 725                 spin_unlock_irqrestore(&msi_lock, flags);
 726                 return;
 727         }
 728         if (irq_has_action(dev->irq)) {
 729                 spin_unlock_irqrestore(&msi_lock, flags);
 730                 printk(KERN_WARNING "PCI: %s: pci_disable_msi() called without "
 731                        "free_irq() on MSI irq %d\n",
 732                        pci_name(dev), dev->irq);
 733                 BUG_ON(irq_has_action(dev->irq));
 734         } else {
 735                 default_irq = entry->msi_attrib.default_irq;
 736                 spin_unlock_irqrestore(&msi_lock, flags);
 737                 msi_free_irq(dev, dev->irq);
 738
 739                 /* Restore dev->irq to its default pin-assertion irq */
 740                 dev->irq = default_irq;
 741         }
 742 }
 743
 744 static int msi_free_irq(struct pci_dev* dev, int irq)
 745 {
 746         struct msi_desc *entry;
 747         int head, entry_nr, type;
 748         void __iomem *base;
 749         unsigned long flags;
 750
 751         arch_teardown_msi_irq(irq);
 752
 753         spin_lock_irqsave(&msi_lock, flags);
 754         entry = msi_desc[irq];
 755         if (!entry || entry->dev != dev) {
 756                 spin_unlock_irqrestore(&msi_lock, flags);
 757                 return -EINVAL;
 758         }
 759         type = entry->msi_attrib.type;
 760         entry_nr = entry->msi_attrib.entry_nr;
 761         head = entry->link.head;
 762         base = entry->mask_base;
 763         msi_desc[entry->link.head]->link.tail = entry->link.tail;
 764         msi_desc[entry->link.tail]->link.head = entry->link.head;
 765         entry->dev = NULL;
 766         msi_desc[irq] = NULL;
 767         spin_unlock_irqrestore(&msi_lock, flags);
 768
 769         destroy_msi_irq(irq);
 770
 771         if (type == PCI_CAP_ID_MSIX) {
 772                 writel(1, base + entry_nr * PCI_MSIX_ENTRY_SIZE +
 773                         PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET);
 774
 775                 if (head == irq)
 776                         iounmap(base);
 777         }
 778
 779         return 0;
 780 }
 781
 782 /**
 783  * pci_enable_msix - configure device's MSI-X capability structure
 784  * @dev: pointer to the pci_dev data structure of MSI-X device function
 785  * @entries: pointer to an array of MSI-X entries
 786  * @nvec: number of MSI-X irqs requested for allocation by device driver
 787  *
 788  * Setup the MSI-X capability structure of device function with the number
 789  * of requested irqs upon its software driver call to request for
 790  * MSI-X mode enabled on its hardware device function. A return of zero
 791  * indicates the successful configuration of MSI-X capability structure
 792  * with new allocated MSI-X irqs. A return of < 0 indicates a failure.
 793  * Or a return of > 0 indicates that driver request is exceeding the number
 794  * of irqs available. Driver should use the returned value to re-send
 795  * its request.
 796  **/
 797 int pci_enable_msix(struct pci_dev* dev, struct msix_entry *entries, int nvec)
 798 {
 799         int status, pos, nr_entries;
 800         int i, j, temp;
 801         u16 control;
 802
 803         if (!entries || pci_msi_supported(dev) < 0)
 804                 return -EINVAL;
 805
 806         status = msi_init();
 807         if (status < 0)
 808                 return status;
 809
 810         pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
 811         if (!pos)
 812                 return -EINVAL;
 813
 814         pci_read_config_word(dev, msi_control_reg(pos), &control);
 815         nr_entries = multi_msix_capable(control);
 816         if (nvec > nr_entries)
 817                 return -EINVAL;
 818
 819         /* Check for any invalid entries */
 820         for (i = 0; i < nvec; i++) {
 821                 if (entries[i].entry >= nr_entries)
 822                         return -EINVAL;         /* invalid entry */
 823                 for (j = i + 1; j < nvec; j++) {
 824                         if (entries[i].entry == entries[j].entry)
 825                                 return -EINVAL; /* duplicate entry */
 826                 }
 827         }
 828         temp = dev->irq;
 829         WARN_ON(!msi_lookup_irq(dev, PCI_CAP_ID_MSIX));
 830
 831         /* Check whether driver already requested for MSI irq */
 832         if (pci_find_capability(dev, PCI_CAP_ID_MSI) > 0 &&
 833                 !msi_lookup_irq(dev, PCI_CAP_ID_MSI)) {
 834                 printk(KERN_INFO "PCI: %s: Can't enable MSI-X.  "
 835                        "Device already has an MSI irq assigned\n",
 836                        pci_name(dev));
 837                 dev->irq = temp;
 838                 return -EINVAL;
 839         }
 840         status = msix_capability_init(dev, entries, nvec);
 841         return status;
 842 }
 843
 844 void pci_disable_msix(struct pci_dev* dev)
 845 {
 846         int pos, temp;
 847         u16 control;
 848
 849         if (!pci_msi_enable)
 850                 return;
 851         if (!dev)
 852                 return;
 853
 854         pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
 855         if (!pos)
 856                 return;
 857
 858         pci_read_config_word(dev, msi_control_reg(pos), &control);
 859         if (!(control & PCI_MSIX_FLAGS_ENABLE))
 860                 return;
 861
 862         disable_msi_mode(dev, pos, PCI_CAP_ID_MSIX);
 863
 864         temp = dev->irq;
 865         if (!msi_lookup_irq(dev, PCI_CAP_ID_MSIX)) {
 866                 int irq, head, tail = 0, warning = 0;
 867                 unsigned long flags;
 868
 869                 irq = head = dev->irq;
 870                 dev->irq = temp;                        /* Restore pin IRQ */
 871                 while (head != tail) {
 872                         spin_lock_irqsave(&msi_lock, flags);
 873                         tail = msi_desc[irq]->link.tail;
 874                         spin_unlock_irqrestore(&msi_lock, flags);
 875                         if (irq_has_action(irq))
 876                                 warning = 1;
 877                         else if (irq != head)   /* Release MSI-X irq */
 878                                 msi_free_irq(dev, irq);
 879                         irq = tail;
 880                 }
 881                 msi_free_irq(dev, irq);
 882                 if (warning) {
 883                         printk(KERN_WARNING "PCI: %s: pci_disable_msix() called without "
 884                                "free_irq() on all MSI-X irqs\n",
 885                                pci_name(dev));
 886                         BUG_ON(warning > 0);
 887                 }
 888         }
 889 }
 890
 891 /**
 892  * msi_remove_pci_irq_vectors - reclaim MSI(X) irqs to unused state
 893  * @dev: pointer to the pci_dev data structure of MSI(X) device function
 894  *
 895  * Being called during hotplug remove, from which the device function
 896  * is hot-removed. All previous assigned MSI/MSI-X irqs, if
 897  * allocated for this device function, are reclaimed to unused state,
 898  * which may be used later on.
 899  **/
 900 void msi_remove_pci_irq_vectors(struct pci_dev* dev)
 901 {
 902         int pos, temp;
 903         unsigned long flags;
 904
 905         if (!pci_msi_enable || !dev)
 906                 return;
 907
 908         temp = dev->irq;                /* Save IOAPIC IRQ */
 909         pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
 910         if (pos > 0 && !msi_lookup_irq(dev, PCI_CAP_ID_MSI)) {
 911                 if (irq_has_action(dev->irq)) {
 912                         printk(KERN_WARNING "PCI: %s: msi_remove_pci_irq_vectors() "
 913                                "called without free_irq() on MSI irq %d\n",
 914                                pci_name(dev), dev->irq);
 915                         BUG_ON(irq_has_action(dev->irq));
 916                 } else /* Release MSI irq assigned to this device */
 917                         msi_free_irq(dev, dev->irq);
 918                 dev->irq = temp;                /* Restore IOAPIC IRQ */
 919         }
 920         pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
 921         if (pos > 0 && !msi_lookup_irq(dev, PCI_CAP_ID_MSIX)) {
 922                 int irq, head, tail = 0, warning = 0;
 923                 void __iomem *base = NULL;
 924
 925                 irq = head = dev->irq;
 926                 while (head != tail) {
 927                         spin_lock_irqsave(&msi_lock, flags);
 928                         tail = msi_desc[irq]->link.tail;
 929                         base = msi_desc[irq]->mask_base;
 930                         spin_unlock_irqrestore(&msi_lock, flags);
 931                         if (irq_has_action(irq))
 932                                 warning = 1;
 933                         else if (irq != head) /* Release MSI-X irq */
 934                                 msi_free_irq(dev, irq);
 935                         irq = tail;
 936                 }
 937                 msi_free_irq(dev, irq);
 938                 if (warning) {
 939                         iounmap(base);
 940                         printk(KERN_WARNING "PCI: %s: msi_remove_pci_irq_vectors() "
 941                                "called without free_irq() on all MSI-X irqs\n",
 942                                pci_name(dev));
 943                         BUG_ON(warning > 0);
 944                 }
 945                 dev->irq = temp;                /* Restore IOAPIC IRQ */
 946         }
 947 }
 948
 949 void pci_no_msi(void)
 950 {
 951         pci_msi_enable = 0;
 952 }
 953
 954 EXPORT_SYMBOL(pci_enable_msi);
 955 EXPORT_SYMBOL(pci_disable_msi);
 956 EXPORT_SYMBOL(pci_enable_msix);
 957 EXPORT_SYMBOL(pci_disable_msix);