1 /* $Id: pbm.h,v 1.27 2001/08/12 13:18:23 davem Exp $
2 * pbm.h: UltraSparc PCI controller software state.
4 * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@redhat.com)
7 #ifndef __SPARC64_PBM_H
8 #define __SPARC64_PBM_H
10 #include <linux/types.h>
11 #include <linux/pci.h>
12 #include <linux/ioport.h>
13 #include <linux/spinlock.h>
14 #include <linux/msi.h>
18 #include <asm/oplib.h>
20 #include <asm/of_device.h>
21 #include <asm/iommu.h>
23 /* The abstraction used here is that there are PCI controllers,
24 * each with one (Sabre) or two (PSYCHO/SCHIZO) PCI bus modules
25 * underneath. Each PCI bus module uses an IOMMU (shared by both
26 * PBMs of a controller, or per-PBM), and if a streaming buffer
27 * is present, each PCI bus module has it's own. (ie. the IOMMU
28 * might be shared between PBMs, the STC is never shared)
29 * Furthermore, each PCI bus module controls it's own autonomous
33 struct pci_controller_info
;
35 /* This contains the software state necessary to drive a PCI
38 struct pci_iommu_arena
{
45 /* This protects the controller's IOMMU and all
46 * streaming buffers underneath.
50 struct pci_iommu_arena arena
;
52 /* IOMMU page table, a linear array of ioptes. */
53 iopte_t
*page_table
; /* The page table itself. */
55 /* Base PCI memory space address where IOMMU mappings
58 u32 page_table_map_base
;
60 /* IOMMU Controller Registers */
61 unsigned long iommu_control
; /* IOMMU control register */
62 unsigned long iommu_tsbbase
; /* IOMMU page table base register */
63 unsigned long iommu_flush
; /* IOMMU page flush register */
64 unsigned long iommu_ctxflush
; /* IOMMU context flush register */
66 /* This is a register in the PCI controller, which if
67 * read will have no side-effects but will guarantee
68 * completion of all previous writes into IOMMU/STC.
70 unsigned long write_complete_reg
;
72 /* In order to deal with some buggy third-party PCI bridges that
73 * do wrong prefetching, we never mark valid mappings as invalid.
74 * Instead we point them at this dummy page.
76 unsigned long dummy_page
;
77 unsigned long dummy_page_pa
;
80 unsigned long ctx_lowest_free
;
81 unsigned long ctx_bitmap
[IOMMU_NUM_CTXS
/ (sizeof(unsigned long) * 8)];
83 /* Here a PCI controller driver describes the areas of
84 * PCI memory space where DMA to/from physical memory
85 * are addressed. Drivers interrogate the PCI layer
86 * if their device has addressing limitations. They
87 * do so via pci_dma_supported, and pass in a mask of
88 * DMA address bits their device can actually drive.
90 * The test for being usable is:
91 * (device_mask & dma_addr_mask) == dma_addr_mask
96 extern void pci_iommu_table_init(struct pci_iommu
*iommu
, int tsbsize
, u32 dma_offset
, u32 dma_addr_mask
);
98 /* This describes a PCI bus module's streaming buffer. */
100 int strbuf_enabled
; /* Present and using it? */
102 /* Streaming Buffer Control Registers */
103 unsigned long strbuf_control
; /* STC control register */
104 unsigned long strbuf_pflush
; /* STC page flush register */
105 unsigned long strbuf_fsync
; /* STC flush synchronization reg */
106 unsigned long strbuf_ctxflush
; /* STC context flush register */
107 unsigned long strbuf_ctxmatch_base
; /* STC context flush match reg */
108 unsigned long strbuf_flushflag_pa
; /* Physical address of flush flag */
109 volatile unsigned long *strbuf_flushflag
; /* The flush flag itself */
111 /* And this is the actual flush flag area.
112 * We allocate extra because the chips require
113 * a 64-byte aligned area.
115 volatile unsigned long __flushflag_buf
[(64 + (64 - 1)) / sizeof(long)];
118 #define PCI_STC_FLUSHFLAG_INIT(STC) \
119 (*((STC)->strbuf_flushflag) = 0UL)
120 #define PCI_STC_FLUSHFLAG_SET(STC) \
121 (*((STC)->strbuf_flushflag) != 0UL)
123 /* There can be quite a few ranges and interrupt maps on a PCI
126 #define PROM_PCIRNG_MAX 64
127 #define PROM_PCIIMAP_MAX 64
129 struct pci_pbm_info
{
130 /* PCI controller we sit under. */
131 struct pci_controller_info
*parent
;
133 /* Physical address base of controller registers. */
134 unsigned long controller_regs
;
136 /* Physical address base of PBM registers. */
137 unsigned long pbm_regs
;
139 /* Physical address of DMA sync register, if any. */
140 unsigned long sync_reg
;
142 /* Opaque 32-bit system bus Port ID. */
145 /* Opaque 32-bit handle used for hypervisor calls. */
148 /* Chipset version information. */
150 #define PBM_CHIP_TYPE_SABRE 1
151 #define PBM_CHIP_TYPE_PSYCHO 2
152 #define PBM_CHIP_TYPE_SCHIZO 3
153 #define PBM_CHIP_TYPE_SCHIZO_PLUS 4
154 #define PBM_CHIP_TYPE_TOMATILLO 5
158 /* Name used for top-level resources. */
161 /* OBP specific information. */
162 struct device_node
*prom_node
;
165 /* PBM I/O and Memory space resources. */
166 struct resource io_space
;
167 struct resource mem_space
;
169 /* Base of PCI Config space, can be per-PBM or shared. */
170 unsigned long config_space
;
172 /* State of 66MHz capabilities on this PBM. */
173 int is_66mhz_capable
;
176 #ifdef CONFIG_PCI_MSI
181 u32 msiq_first_devino
;
191 unsigned long *msi_bitmap
;
192 #endif /* !(CONFIG_PCI_MSI) */
194 /* This PBM's streaming buffer. */
195 struct pci_strbuf stc
;
197 /* IOMMU state, potentially shared by both PBM segments. */
198 struct pci_iommu
*iommu
;
200 /* PCI slot mapping. */
201 unsigned int pci_first_slot
;
203 /* Now things for the actual PCI bus probes. */
204 unsigned int pci_first_busno
;
205 unsigned int pci_last_busno
;
206 struct pci_bus
*pci_bus
;
209 struct pci_controller_info
{
210 /* List of all PCI controllers. */
211 struct pci_controller_info
*next
;
213 /* Each controller gets a unique index, used mostly for
214 * error logging purposes.
218 /* Do the PBMs both exist in the same PCI domain? */
219 int pbms_same_domain
;
221 /* The PCI bus modules controlled by us. */
222 struct pci_pbm_info pbm_A
;
223 struct pci_pbm_info pbm_B
;
225 /* Operations which are controller specific. */
226 void (*scan_bus
)(struct pci_controller_info
*);
228 #ifdef CONFIG_PCI_MSI
229 int (*setup_msi_irq
)(unsigned int *virt_irq_p
, struct pci_dev
*pdev
,
230 struct msi_desc
*entry
);
231 void (*teardown_msi_irq
)(unsigned int virt_irq
, struct pci_dev
*pdev
);
234 /* Now things for the actual PCI bus probes. */
235 struct pci_ops
*pci_ops
;
236 unsigned int pci_first_busno
;
237 unsigned int pci_last_busno
;
240 #endif /* !(__SPARC64_PBM_H) */