arch/powerpc/kernel/pci_32.c

   1 /*
   2  * Common pmac/prep/chrp pci routines. -- Cort
   3  */
   4
   5 #include <linux/kernel.h>
   6 #include <linux/pci.h>
   7 #include <linux/delay.h>
   8 #include <linux/string.h>
   9 #include <linux/init.h>
  10 #include <linux/capability.h>
  11 #include <linux/sched.h>
  12 #include <linux/errno.h>
  13 #include <linux/bootmem.h>
  14 #include <linux/irq.h>
  15 #include <linux/list.h>
  16
  17 #include <asm/processor.h>
  18 #include <asm/io.h>
  19 #include <asm/prom.h>
  20 #include <asm/sections.h>
  21 #include <asm/pci-bridge.h>
  22 #include <asm/byteorder.h>
  23 #include <asm/uaccess.h>
  24 #include <asm/machdep.h>
  25
  26 #undef DEBUG
  27
  28 #ifdef DEBUG
  29 #define DBG(x...) printk(x)
  30 #else
  31 #define DBG(x...)
  32 #endif
  33
  34 unsigned long isa_io_base     = 0;
  35 unsigned long isa_mem_base    = 0;
  36 unsigned long pci_dram_offset = 0;
  37 int pcibios_assign_bus_offset = 1;
  38
  39 void pcibios_make_OF_bus_map(void);
  40
  41 static int pci_relocate_bridge_resource(struct pci_bus *bus, int i);
  42 static int probe_resource(struct pci_bus *parent, struct resource *pr,
  43                           struct resource *res, struct resource **conflict);
  44 static void update_bridge_base(struct pci_bus *bus, int i);
  45 static void pcibios_fixup_resources(struct pci_dev* dev);
  46 static void fixup_broken_pcnet32(struct pci_dev* dev);
  47 static int reparent_resources(struct resource *parent, struct resource *res);
  48 static void fixup_cpc710_pci64(struct pci_dev* dev);
  49 #ifdef CONFIG_PPC_OF
  50 static u8* pci_to_OF_bus_map;
  51 #endif
  52
  53 /* By default, we don't re-assign bus numbers. We do this only on
  54  * some pmacs
  55  */
  56 int pci_assign_all_buses;
  57
  58 struct pci_controller* hose_head;
  59 struct pci_controller** hose_tail = &hose_head;
  60
  61 static int pci_bus_count;
  62
  63 static void
  64 fixup_broken_pcnet32(struct pci_dev* dev)
  65 {
  66         if ((dev->class>>8 == PCI_CLASS_NETWORK_ETHERNET)) {
  67                 dev->vendor = PCI_VENDOR_ID_AMD;
  68                 pci_write_config_word(dev, PCI_VENDOR_ID, PCI_VENDOR_ID_AMD);
  69         }
  70 }
  71 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TRIDENT, PCI_ANY_ID,                     fixup_broken_pcnet32);
  72
  73 static void
  74 fixup_cpc710_pci64(struct pci_dev* dev)
  75 {
  76         /* Hide the PCI64 BARs from the kernel as their content doesn't
  77          * fit well in the resource management
  78          */
  79         dev->resource[0].start = dev->resource[0].end = 0;
  80         dev->resource[0].flags = 0;
  81         dev->resource[1].start = dev->resource[1].end = 0;
  82         dev->resource[1].flags = 0;
  83 }
  84 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM,     PCI_DEVICE_ID_IBM_CPC710_PCI64, fixup_cpc710_pci64);
  85
  86 static void
  87 pcibios_fixup_resources(struct pci_dev *dev)
  88 {
  89         struct pci_controller* hose = (struct pci_controller *)dev->sysdata;
  90         int i;
  91         unsigned long offset;
  92
  93         if (!hose) {
  94                 printk(KERN_ERR "No hose for PCI dev %s!\n", pci_name(dev));
  95                 return;
  96         }
  97         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
  98                 struct resource *res = dev->resource + i;
  99                 if (!res->flags)
 100                         continue;
 101                 if (res->end == 0xffffffff) {
 102                         DBG("PCI:%s Resource %d [%016llx-%016llx] is unassigned\n",
 103                             pci_name(dev), i, (u64)res->start, (u64)res->end);
 104                         res->end -= res->start;
 105                         res->start = 0;
 106                         res->flags |= IORESOURCE_UNSET;
 107                         continue;
 108                 }
 109                 offset = 0;
 110                 if (res->flags & IORESOURCE_MEM) {
 111                         offset = hose->pci_mem_offset;
 112                 } else if (res->flags & IORESOURCE_IO) {
 113                         offset = (unsigned long) hose->io_base_virt
 114                                 - isa_io_base;
 115                 }
 116                 if (offset != 0) {
 117                         res->start += offset;
 118                         res->end += offset;
 119                         DBG("Fixup res %d (%lx) of dev %s: %llx -> %llx\n",
 120                             i, res->flags, pci_name(dev),
 121                             (u64)res->start - offset, (u64)res->start);
 122                 }
 123         }
 124
 125         /* Call machine specific resource fixup */
 126         if (ppc_md.pcibios_fixup_resources)
 127                 ppc_md.pcibios_fixup_resources(dev);
 128 }
 129 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID,            PCI_ANY_ID,                     pcibios_fixup_resources);
 130
 131 void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
 132                         struct resource *res)
 133 {
 134         unsigned long offset = 0;
 135         struct pci_controller *hose = dev->sysdata;
 136
 137         if (hose && res->flags & IORESOURCE_IO)
 138                 offset = (unsigned long)hose->io_base_virt - isa_io_base;
 139         else if (hose && res->flags & IORESOURCE_MEM)
 140                 offset = hose->pci_mem_offset;
 141         region->start = res->start - offset;
 142         region->end = res->end - offset;
 143 }
 144 EXPORT_SYMBOL(pcibios_resource_to_bus);
 145
 146 void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
 147                              struct pci_bus_region *region)
 148 {
 149         unsigned long offset = 0;
 150         struct pci_controller *hose = dev->sysdata;
 151
 152         if (hose && res->flags & IORESOURCE_IO)
 153                 offset = (unsigned long)hose->io_base_virt - isa_io_base;
 154         else if (hose && res->flags & IORESOURCE_MEM)
 155                 offset = hose->pci_mem_offset;
 156         res->start = region->start + offset;
 157         res->end = region->end + offset;
 158 }
 159 EXPORT_SYMBOL(pcibios_bus_to_resource);
 160
 161 /*
 162  * We need to avoid collisions with `mirrored' VGA ports
 163  * and other strange ISA hardware, so we always want the
 164  * addresses to be allocated in the 0x000-0x0ff region
 165  * modulo 0x400.
 166  *
 167  * Why? Because some silly external IO cards only decode
 168  * the low 10 bits of the IO address. The 0x00-0xff region
 169  * is reserved for motherboard devices that decode all 16
 170  * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
 171  * but we want to try to avoid allocating at 0x2900-0x2bff
 172  * which might have be mirrored at 0x0100-0x03ff..
 173  */
 174 void pcibios_align_resource(void *data, struct resource *res,
 175                                 resource_size_t size, resource_size_t align)
 176 {
 177         struct pci_dev *dev = data;
 178
 179         if (res->flags & IORESOURCE_IO) {
 180                 resource_size_t start = res->start;
 181
 182                 if (size > 0x100) {
 183                         printk(KERN_ERR "PCI: I/O Region %s/%d too large"
 184                                " (%lld bytes)\n", pci_name(dev),
 185                                dev->resource - res, (unsigned long long)size);
 186                 }
 187
 188                 if (start & 0x300) {
 189                         start = (start + 0x3ff) & ~0x3ff;
 190                         res->start = start;
 191                 }
 192         }
 193 }
 194 EXPORT_SYMBOL(pcibios_align_resource);
 195
 196 /*
 197  *  Handle resources of PCI devices.  If the world were perfect, we could
 198  *  just allocate all the resource regions and do nothing more.  It isn't.
 199  *  On the other hand, we cannot just re-allocate all devices, as it would
 200  *  require us to know lots of host bridge internals.  So we attempt to
 201  *  keep as much of the original configuration as possible, but tweak it
 202  *  when it's found to be wrong.
 203  *
 204  *  Known BIOS problems we have to work around:
 205  *      - I/O or memory regions not configured
 206  *      - regions configured, but not enabled in the command register
 207  *      - bogus I/O addresses above 64K used
 208  *      - expansion ROMs left enabled (this may sound harmless, but given
 209  *        the fact the PCI specs explicitly allow address decoders to be
 210  *        shared between expansion ROMs and other resource regions, it's
 211  *        at least dangerous)
 212  *
 213  *  Our solution:
 214  *      (1) Allocate resources for all buses behind PCI-to-PCI bridges.
 215  *          This gives us fixed barriers on where we can allocate.
 216  *      (2) Allocate resources for all enabled devices.  If there is
 217  *          a collision, just mark the resource as unallocated. Also
 218  *          disable expansion ROMs during this step.
 219  *      (3) Try to allocate resources for disabled devices.  If the
 220  *          resources were assigned correctly, everything goes well,
 221  *          if they weren't, they won't disturb allocation of other
 222  *          resources.
 223  *      (4) Assign new addresses to resources which were either
 224  *          not configured at all or misconfigured.  If explicitly
 225  *          requested by the user, configure expansion ROM address
 226  *          as well.
 227  */
 228
 229 static void __init
 230 pcibios_allocate_bus_resources(struct list_head *bus_list)
 231 {
 232         struct pci_bus *bus;
 233         int i;
 234         struct resource *res, *pr;
 235
 236         /* Depth-First Search on bus tree */
 237         list_for_each_entry(bus, bus_list, node) {
 238                 for (i = 0; i < 4; ++i) {
 239                         if ((res = bus->resource[i]) == NULL || !res->flags
 240                             || res->start > res->end)
 241                                 continue;
 242                         if (bus->parent == NULL)
 243                                 pr = (res->flags & IORESOURCE_IO)?
 244                                         &ioport_resource: &iomem_resource;
 245                         else {
 246                                 pr = pci_find_parent_resource(bus->self, res);
 247                                 if (pr == res) {
 248                                         /* this happens when the generic PCI
 249                                          * code (wrongly) decides that this
 250                                          * bridge is transparent  -- paulus
 251                                          */
 252                                         continue;
 253                                 }
 254                         }
 255
 256                         DBG("PCI: bridge rsrc %llx..%llx (%lx), parent %p\n",
 257                             (u64)res->start, (u64)res->end, res->flags, pr);
 258                         if (pr) {
 259                                 if (request_resource(pr, res) == 0)
 260                                         continue;
 261                                 /*
 262                                  * Must be a conflict with an existing entry.
 263                                  * Move that entry (or entries) under the
 264                                  * bridge resource and try again.
 265                                  */
 266                                 if (reparent_resources(pr, res) == 0)
 267                                         continue;
 268                         }
 269                         printk(KERN_ERR "PCI: Cannot allocate resource region "
 270                                "%d of PCI bridge %d\n", i, bus->number);
 271                         if (pci_relocate_bridge_resource(bus, i))
 272                                 bus->resource[i] = NULL;
 273                 }
 274                 pcibios_allocate_bus_resources(&bus->children);
 275         }
 276 }
 277
 278 /*
 279  * Reparent resource children of pr that conflict with res
 280  * under res, and make res replace those children.
 281  */
 282 static int __init
 283 reparent_resources(struct resource *parent, struct resource *res)
 284 {
 285         struct resource *p, **pp;
 286         struct resource **firstpp = NULL;
 287
 288         for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) {
 289                 if (p->end < res->start)
 290                         continue;
 291                 if (res->end < p->start)
 292                         break;
 293                 if (p->start < res->start || p->end > res->end)
 294                         return -1;      /* not completely contained */
 295                 if (firstpp == NULL)
 296                         firstpp = pp;
 297         }
 298         if (firstpp == NULL)
 299                 return -1;      /* didn't find any conflicting entries? */
 300         res->parent = parent;
 301         res->child = *firstpp;
 302         res->sibling = *pp;
 303         *firstpp = res;
 304         *pp = NULL;
 305         for (p = res->child; p != NULL; p = p->sibling) {
 306                 p->parent = res;
 307                 DBG(KERN_INFO "PCI: reparented %s [%llx..%llx] under %s\n",
 308                     p->name, (u64)p->start, (u64)p->end, res->name);
 309         }
 310         return 0;
 311 }
 312
 313 /*
 314  * A bridge has been allocated a range which is outside the range
 315  * of its parent bridge, so it needs to be moved.
 316  */
 317 static int __init
 318 pci_relocate_bridge_resource(struct pci_bus *bus, int i)
 319 {
 320         struct resource *res, *pr, *conflict;
 321         unsigned long try, size;
 322         int j;
 323         struct pci_bus *parent = bus->parent;
 324
 325         if (parent == NULL) {
 326                 /* shouldn't ever happen */
 327                 printk(KERN_ERR "PCI: can't move host bridge resource\n");
 328                 return -1;
 329         }
 330         res = bus->resource[i];
 331         if (res == NULL)
 332                 return -1;
 333         pr = NULL;
 334         for (j = 0; j < 4; j++) {
 335                 struct resource *r = parent->resource[j];
 336                 if (!r)
 337                         continue;
 338                 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
 339                         continue;
 340                 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH)) {
 341                         pr = r;
 342                         break;
 343                 }
 344                 if (res->flags & IORESOURCE_PREFETCH)
 345                         pr = r;
 346         }
 347         if (pr == NULL)
 348                 return -1;
 349         size = res->end - res->start;
 350         if (pr->start > pr->end || size > pr->end - pr->start)
 351                 return -1;
 352         try = pr->end;
 353         for (;;) {
 354                 res->start = try - size;
 355                 res->end = try;
 356                 if (probe_resource(bus->parent, pr, res, &conflict) == 0)
 357                         break;
 358                 if (conflict->start <= pr->start + size)
 359                         return -1;
 360                 try = conflict->start - 1;
 361         }
 362         if (request_resource(pr, res)) {
 363                 DBG(KERN_ERR "PCI: huh? couldn't move to %llx..%llx\n",
 364                     (u64)res->start, (u64)res->end);
 365                 return -1;              /* "can't happen" */
 366         }
 367         update_bridge_base(bus, i);
 368         printk(KERN_INFO "PCI: bridge %d resource %d moved to %llx..%llx\n",
 369                bus->number, i, (unsigned long long)res->start,
 370                (unsigned long long)res->end);
 371         return 0;
 372 }
 373
 374 static int __init
 375 probe_resource(struct pci_bus *parent, struct resource *pr,
 376                struct resource *res, struct resource **conflict)
 377 {
 378         struct pci_bus *bus;
 379         struct pci_dev *dev;
 380         struct resource *r;
 381         int i;
 382
 383         for (r = pr->child; r != NULL; r = r->sibling) {
 384                 if (r->end >= res->start && res->end >= r->start) {
 385                         *conflict = r;
 386                         return 1;
 387                 }
 388         }
 389         list_for_each_entry(bus, &parent->children, node) {
 390                 for (i = 0; i < 4; ++i) {
 391                         if ((r = bus->resource[i]) == NULL)
 392                                 continue;
 393                         if (!r->flags || r->start > r->end || r == res)
 394                                 continue;
 395                         if (pci_find_parent_resource(bus->self, r) != pr)
 396                                 continue;
 397                         if (r->end >= res->start && res->end >= r->start) {
 398                                 *conflict = r;
 399                                 return 1;
 400                         }
 401                 }
 402         }
 403         list_for_each_entry(dev, &parent->devices, bus_list) {
 404                 for (i = 0; i < 6; ++i) {
 405                         r = &dev->resource[i];
 406                         if (!r->flags || (r->flags & IORESOURCE_UNSET))
 407                                 continue;
 408                         if (pci_find_parent_resource(dev, r) != pr)
 409                                 continue;
 410                         if (r->end >= res->start && res->end >= r->start) {
 411                                 *conflict = r;
 412                                 return 1;
 413                         }
 414                 }
 415         }
 416         return 0;
 417 }
 418
 419 static void __init
 420 update_bridge_base(struct pci_bus *bus, int i)
 421 {
 422         struct resource *res = bus->resource[i];
 423         u8 io_base_lo, io_limit_lo;
 424         u16 mem_base, mem_limit;
 425         u16 cmd;
 426         unsigned long start, end, off;
 427         struct pci_dev *dev = bus->self;
 428         struct pci_controller *hose = dev->sysdata;
 429
 430         if (!hose) {
 431                 printk("update_bridge_base: no hose?\n");
 432                 return;
 433         }
 434         pci_read_config_word(dev, PCI_COMMAND, &cmd);
 435         pci_write_config_word(dev, PCI_COMMAND,
 436                               cmd & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY));
 437         if (res->flags & IORESOURCE_IO) {
 438                 off = (unsigned long) hose->io_base_virt - isa_io_base;
 439                 start = res->start - off;
 440                 end = res->end - off;
 441                 io_base_lo = (start >> 8) & PCI_IO_RANGE_MASK;
 442                 io_limit_lo = (end >> 8) & PCI_IO_RANGE_MASK;
 443                 if (end > 0xffff)
 444                         io_base_lo |= PCI_IO_RANGE_TYPE_32;
 445                 else
 446                         io_base_lo |= PCI_IO_RANGE_TYPE_16;
 447                 pci_write_config_word(dev, PCI_IO_BASE_UPPER16,
 448                                 start >> 16);
 449                 pci_write_config_word(dev, PCI_IO_LIMIT_UPPER16,
 450                                 end >> 16);
 451                 pci_write_config_byte(dev, PCI_IO_BASE, io_base_lo);
 452                 pci_write_config_byte(dev, PCI_IO_LIMIT, io_limit_lo);
 453
 454         } else if ((res->flags & (IORESOURCE_MEM | IORESOURCE_PREFETCH))
 455                    == IORESOURCE_MEM) {
 456                 off = hose->pci_mem_offset;
 457                 mem_base = ((res->start - off) >> 16) & PCI_MEMORY_RANGE_MASK;
 458                 mem_limit = ((res->end - off) >> 16) & PCI_MEMORY_RANGE_MASK;
 459                 pci_write_config_word(dev, PCI_MEMORY_BASE, mem_base);
 460                 pci_write_config_word(dev, PCI_MEMORY_LIMIT, mem_limit);
 461
 462         } else if ((res->flags & (IORESOURCE_MEM | IORESOURCE_PREFETCH))
 463                    == (IORESOURCE_MEM | IORESOURCE_PREFETCH)) {
 464                 off = hose->pci_mem_offset;
 465                 mem_base = ((res->start - off) >> 16) & PCI_PREF_RANGE_MASK;
 466                 mem_limit = ((res->end - off) >> 16) & PCI_PREF_RANGE_MASK;
 467                 pci_write_config_word(dev, PCI_PREF_MEMORY_BASE, mem_base);
 468                 pci_write_config_word(dev, PCI_PREF_MEMORY_LIMIT, mem_limit);
 469
 470         } else {
 471                 DBG(KERN_ERR "PCI: ugh, bridge %s res %d has flags=%lx\n",
 472                     pci_name(dev), i, res->flags);
 473         }
 474         pci_write_config_word(dev, PCI_COMMAND, cmd);
 475 }
 476
 477 static inline void alloc_resource(struct pci_dev *dev, int idx)
 478 {
 479         struct resource *pr, *r = &dev->resource[idx];
 480
 481         DBG("PCI:%s: Resource %d: %016llx-%016llx (f=%lx)\n",
 482             pci_name(dev), idx, (u64)r->start, (u64)r->end, r->flags);
 483         pr = pci_find_parent_resource(dev, r);
 484         if (!pr || request_resource(pr, r) < 0) {
 485                 printk(KERN_ERR "PCI: Cannot allocate resource region %d"
 486                        " of device %s\n", idx, pci_name(dev));
 487                 if (pr)
 488                         DBG("PCI:  parent is %p: %016llx-%016llx (f=%lx)\n",
 489                             pr, (u64)pr->start, (u64)pr->end, pr->flags);
 490                 /* We'll assign a new address later */
 491                 r->flags |= IORESOURCE_UNSET;
 492                 r->end -= r->start;
 493                 r->start = 0;
 494         }
 495 }
 496
 497 static void __init
 498 pcibios_allocate_resources(int pass)
 499 {
 500         struct pci_dev *dev = NULL;
 501         int idx, disabled;
 502         u16 command;
 503         struct resource *r;
 504
 505         for_each_pci_dev(dev) {
 506                 pci_read_config_word(dev, PCI_COMMAND, &command);
 507                 for (idx = 0; idx < 6; idx++) {
 508                         r = &dev->resource[idx];
 509                         if (r->parent)          /* Already allocated */
 510                                 continue;
 511                         if (!r->flags || (r->flags & IORESOURCE_UNSET))
 512                                 continue;       /* Not assigned at all */
 513                         if (r->flags & IORESOURCE_IO)
 514                                 disabled = !(command & PCI_COMMAND_IO);
 515                         else
 516                                 disabled = !(command & PCI_COMMAND_MEMORY);
 517                         if (pass == disabled)
 518                                 alloc_resource(dev, idx);
 519                 }
 520                 if (pass)
 521                         continue;
 522                 r = &dev->resource[PCI_ROM_RESOURCE];
 523                 if (r->flags & IORESOURCE_ROM_ENABLE) {
 524                         /* Turn the ROM off, leave the resource region, but keep it unregistered. */
 525                         u32 reg;
 526                         DBG("PCI: Switching off ROM of %s\n", pci_name(dev));
 527                         r->flags &= ~IORESOURCE_ROM_ENABLE;
 528                         pci_read_config_dword(dev, dev->rom_base_reg, &reg);
 529                         pci_write_config_dword(dev, dev->rom_base_reg,
 530                                                reg & ~PCI_ROM_ADDRESS_ENABLE);
 531                 }
 532         }
 533 }
 534
 535 static void __init
 536 pcibios_assign_resources(void)
 537 {
 538         struct pci_dev *dev = NULL;
 539         int idx;
 540         struct resource *r;
 541
 542         for_each_pci_dev(dev) {
 543                 int class = dev->class >> 8;
 544
 545                 /* Don't touch classless devices and host bridges */
 546                 if (!class || class == PCI_CLASS_BRIDGE_HOST)
 547                         continue;
 548
 549                 for (idx = 0; idx < 6; idx++) {
 550                         r = &dev->resource[idx];
 551
 552                         /*
 553                          * We shall assign a new address to this resource,
 554                          * either because the BIOS (sic) forgot to do so
 555                          * or because we have decided the old address was
 556                          * unusable for some reason.
 557                          */
 558                         if ((r->flags & IORESOURCE_UNSET) && r->end &&
 559                             (!ppc_md.pcibios_enable_device_hook ||
 560                              !ppc_md.pcibios_enable_device_hook(dev, 1))) {
 561                                 r->flags &= ~IORESOURCE_UNSET;
 562                                 pci_assign_resource(dev, idx);
 563                         }
 564                 }
 565
 566 #if 0 /* don't assign ROMs */
 567                 r = &dev->resource[PCI_ROM_RESOURCE];
 568                 r->end -= r->start;
 569                 r->start = 0;
 570                 if (r->end)
 571                         pci_assign_resource(dev, PCI_ROM_RESOURCE);
 572 #endif
 573         }
 574 }
 575
 576
 577 int
 578 pcibios_enable_resources(struct pci_dev *dev, int mask)
 579 {
 580         u16 cmd, old_cmd;
 581         int idx;
 582         struct resource *r;
 583
 584         pci_read_config_word(dev, PCI_COMMAND, &cmd);
 585         old_cmd = cmd;
 586         for (idx=0; idx<6; idx++) {
 587                 /* Only set up the requested stuff */
 588                 if (!(mask & (1<<idx)))
 589                         continue;
 590
 591                 r = &dev->resource[idx];
 592                 if (r->flags & IORESOURCE_UNSET) {
 593                         printk(KERN_ERR "PCI: Device %s not available because of resource collisions\n", pci_name(dev));
 594                         return -EINVAL;
 595                 }
 596                 if (r->flags & IORESOURCE_IO)
 597                         cmd |= PCI_COMMAND_IO;
 598                 if (r->flags & IORESOURCE_MEM)
 599                         cmd |= PCI_COMMAND_MEMORY;
 600         }
 601         if (dev->resource[PCI_ROM_RESOURCE].start)
 602                 cmd |= PCI_COMMAND_MEMORY;
 603         if (cmd != old_cmd) {
 604                 printk("PCI: Enabling device %s (%04x -> %04x)\n", pci_name(dev), old_cmd, cmd);
 605                 pci_write_config_word(dev, PCI_COMMAND, cmd);
 606         }
 607         return 0;
 608 }
 609
 610 static int next_controller_index;
 611
 612 struct pci_controller * __init
 613 pcibios_alloc_controller(void)
 614 {
 615         struct pci_controller *hose;
 616
 617         hose = (struct pci_controller *)alloc_bootmem(sizeof(*hose));
 618         memset(hose, 0, sizeof(struct pci_controller));
 619
 620         *hose_tail = hose;
 621         hose_tail = &hose->next;
 622
 623         hose->index = next_controller_index++;
 624
 625         return hose;
 626 }
 627
 628 #ifdef CONFIG_PPC_OF
 629 /*
 630  * Functions below are used on OpenFirmware machines.
 631  */
 632 static void
 633 make_one_node_map(struct device_node* node, u8 pci_bus)
 634 {
 635         const int *bus_range;
 636         int len;
 637
 638         if (pci_bus >= pci_bus_count)
 639                 return;
 640         bus_range = of_get_property(node, "bus-range", &len);
 641         if (bus_range == NULL || len < 2 * sizeof(int)) {
 642                 printk(KERN_WARNING "Can't get bus-range for %s, "
 643                        "assuming it starts at 0\n", node->full_name);
 644                 pci_to_OF_bus_map[pci_bus] = 0;
 645         } else
 646                 pci_to_OF_bus_map[pci_bus] = bus_range[0];
 647
 648         for (node=node->child; node != 0;node = node->sibling) {
 649                 struct pci_dev* dev;
 650                 const unsigned int *class_code, *reg;
 651
 652                 class_code = of_get_property(node, "class-code", NULL);
 653                 if (!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI &&
 654                         (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS))
 655                         continue;
 656                 reg = of_get_property(node, "reg", NULL);
 657                 if (!reg)
 658                         continue;
 659                 dev = pci_find_slot(pci_bus, ((reg[0] >> 8) & 0xff));
 660                 if (!dev || !dev->subordinate)
 661                         continue;
 662                 make_one_node_map(node, dev->subordinate->number);
 663         }
 664 }
 665
 666 void
 667 pcibios_make_OF_bus_map(void)
 668 {
 669         int i;
 670         struct pci_controller* hose;
 671         struct property *map_prop;
 672         struct device_node *dn;
 673
 674         pci_to_OF_bus_map = kmalloc(pci_bus_count, GFP_KERNEL);
 675         if (!pci_to_OF_bus_map) {
 676                 printk(KERN_ERR "Can't allocate OF bus map !\n");
 677                 return;
 678         }
 679
 680         /* We fill the bus map with invalid values, that helps
 681          * debugging.
 682          */
 683         for (i=0; i<pci_bus_count; i++)
 684                 pci_to_OF_bus_map[i] = 0xff;
 685
 686         /* For each hose, we begin searching bridges */
 687         for(hose=hose_head; hose; hose=hose->next) {
 688                 struct device_node* node;
 689                 node = (struct device_node *)hose->arch_data;
 690                 if (!node)
 691                         continue;
 692                 make_one_node_map(node, hose->first_busno);
 693         }
 694         dn = of_find_node_by_path("/");
 695         map_prop = of_find_property(dn, "pci-OF-bus-map", NULL);
 696         if (map_prop) {
 697                 BUG_ON(pci_bus_count > map_prop->length);
 698                 memcpy(map_prop->value, pci_to_OF_bus_map, pci_bus_count);
 699         }
 700         of_node_put(dn);
 701 #ifdef DEBUG
 702         printk("PCI->OF bus map:\n");
 703         for (i=0; i<pci_bus_count; i++) {
 704                 if (pci_to_OF_bus_map[i] == 0xff)
 705                         continue;
 706                 printk("%d -> %d\n", i, pci_to_OF_bus_map[i]);
 707         }
 708 #endif
 709 }
 710
 711 typedef int (*pci_OF_scan_iterator)(struct device_node* node, void* data);
 712
 713 static struct device_node*
 714 scan_OF_pci_childs(struct device_node* node, pci_OF_scan_iterator filter, void* data)
 715 {
 716         struct device_node* sub_node;
 717
 718         for (; node != 0;node = node->sibling) {
 719                 const unsigned int *class_code;
 720
 721                 if (filter(node, data))
 722                         return node;
 723
 724                 /* For PCI<->PCI bridges or CardBus bridges, we go down
 725                  * Note: some OFs create a parent node "multifunc-device" as
 726                  * a fake root for all functions of a multi-function device,
 727                  * we go down them as well.
 728                  */
 729                 class_code = of_get_property(node, "class-code", NULL);
 730                 if ((!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI &&
 731                         (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS)) &&
 732                         strcmp(node->name, "multifunc-device"))
 733                         continue;
 734                 sub_node = scan_OF_pci_childs(node->child, filter, data);
 735                 if (sub_node)
 736                         return sub_node;
 737         }
 738         return NULL;
 739 }
 740
 741 static struct device_node *scan_OF_for_pci_dev(struct device_node *parent,
 742                                                unsigned int devfn)
 743 {
 744         struct device_node *np = NULL;
 745         const u32 *reg;
 746         unsigned int psize;
 747
 748         while ((np = of_get_next_child(parent, np)) != NULL) {
 749                 reg = of_get_property(np, "reg", &psize);
 750                 if (reg == NULL || psize < 4)
 751                         continue;
 752                 if (((reg[0] >> 8) & 0xff) == devfn)
 753                         return np;
 754         }
 755         return NULL;
 756 }
 757
 758
 759 static struct device_node *scan_OF_for_pci_bus(struct pci_bus *bus)
 760 {
 761         struct device_node *parent, *np;
 762
 763         /* Are we a root bus ? */
 764         if (bus->self == NULL || bus->parent == NULL) {
 765                 struct pci_controller *hose = pci_bus_to_hose(bus->number);
 766                 if (hose == NULL)
 767                         return NULL;
 768                 return of_node_get(hose->arch_data);
 769         }
 770
 771         /* not a root bus, we need to get our parent */
 772         parent = scan_OF_for_pci_bus(bus->parent);
 773         if (parent == NULL)
 774                 return NULL;
 775
 776         /* now iterate for children for a match */
 777         np = scan_OF_for_pci_dev(parent, bus->self->devfn);
 778         of_node_put(parent);
 779
 780         return np;
 781 }
 782
 783 /*
 784  * Scans the OF tree for a device node matching a PCI device
 785  */
 786 struct device_node *
 787 pci_busdev_to_OF_node(struct pci_bus *bus, int devfn)
 788 {
 789         struct device_node *parent, *np;
 790
 791         if (!have_of)
 792                 return NULL;
 793
 794         DBG("pci_busdev_to_OF_node(%d,0x%x)\n", bus->number, devfn);
 795         parent = scan_OF_for_pci_bus(bus);
 796         if (parent == NULL)
 797                 return NULL;
 798         DBG(" parent is %s\n", parent ? parent->full_name : "<NULL>");
 799         np = scan_OF_for_pci_dev(parent, devfn);
 800         of_node_put(parent);
 801         DBG(" result is %s\n", np ? np->full_name : "<NULL>");
 802
 803         /* XXX most callers don't release the returned node
 804          * mostly because ppc64 doesn't increase the refcount,
 805          * we need to fix that.
 806          */
 807         return np;
 808 }
 809 EXPORT_SYMBOL(pci_busdev_to_OF_node);
 810
 811 struct device_node*
 812 pci_device_to_OF_node(struct pci_dev *dev)
 813 {
 814         return pci_busdev_to_OF_node(dev->bus, dev->devfn);
 815 }
 816 EXPORT_SYMBOL(pci_device_to_OF_node);
 817
 818 /* This routine is meant to be used early during boot, when the
 819  * PCI bus numbers have not yet been assigned, and you need to
 820  * issue PCI config cycles to an OF device.
 821  * It could also be used to "fix" RTAS config cycles if you want
 822  * to set pci_assign_all_buses to 1 and still use RTAS for PCI
 823  * config cycles.
 824  */
 825 struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node)
 826 {
 827         if (!have_of)
 828                 return NULL;
 829         while(node) {
 830                 struct pci_controller* hose;
 831                 for (hose=hose_head;hose;hose=hose->next)
 832                         if (hose->arch_data == node)
 833                                 return hose;
 834                 node=node->parent;
 835         }
 836         return NULL;
 837 }
 838
 839 static int
 840 find_OF_pci_device_filter(struct device_node* node, void* data)
 841 {
 842         return ((void *)node == data);
 843 }
 844
 845 /*
 846  * Returns the PCI device matching a given OF node
 847  */
 848 int
 849 pci_device_from_OF_node(struct device_node* node, u8* bus, u8* devfn)
 850 {
 851         const unsigned int *reg;
 852         struct pci_controller* hose;
 853         struct pci_dev* dev = NULL;
 854
 855         if (!have_of)
 856                 return -ENODEV;
 857         /* Make sure it's really a PCI device */
 858         hose = pci_find_hose_for_OF_device(node);
 859         if (!hose || !hose->arch_data)
 860                 return -ENODEV;
 861         if (!scan_OF_pci_childs(((struct device_node*)hose->arch_data)->child,
 862                         find_OF_pci_device_filter, (void *)node))
 863                 return -ENODEV;
 864         reg = of_get_property(node, "reg", NULL);
 865         if (!reg)
 866                 return -ENODEV;
 867         *bus = (reg[0] >> 16) & 0xff;
 868         *devfn = ((reg[0] >> 8) & 0xff);
 869
 870         /* Ok, here we need some tweak. If we have already renumbered
 871          * all busses, we can't rely on the OF bus number any more.
 872          * the pci_to_OF_bus_map is not enough as several PCI busses
 873          * may match the same OF bus number.
 874          */
 875         if (!pci_to_OF_bus_map)
 876                 return 0;
 877
 878         for_each_pci_dev(dev)
 879                 if (pci_to_OF_bus_map[dev->bus->number] == *bus &&
 880                                 dev->devfn == *devfn) {
 881                         *bus = dev->bus->number;
 882                         pci_dev_put(dev);
 883                         return 0;
 884                 }
 885
 886         return -ENODEV;
 887 }
 888 EXPORT_SYMBOL(pci_device_from_OF_node);
 889
 890 void __init
 891 pci_process_bridge_OF_ranges(struct pci_controller *hose,
 892                            struct device_node *dev, int primary)
 893 {
 894         static unsigned int static_lc_ranges[256] __initdata;
 895         const unsigned int *dt_ranges;
 896         unsigned int *lc_ranges, *ranges, *prev, size;
 897         int rlen = 0, orig_rlen;
 898         int memno = 0;
 899         struct resource *res;
 900         int np, na = of_n_addr_cells(dev);
 901         np = na + 5;
 902
 903         /* First we try to merge ranges to fix a problem with some pmacs
 904          * that can have more than 3 ranges, fortunately using contiguous
 905          * addresses -- BenH
 906          */
 907         dt_ranges = of_get_property(dev, "ranges", &rlen);
 908         if (!dt_ranges)
 909                 return;
 910         /* Sanity check, though hopefully that never happens */
 911         if (rlen > sizeof(static_lc_ranges)) {
 912                 printk(KERN_WARNING "OF ranges property too large !\n");
 913                 rlen = sizeof(static_lc_ranges);
 914         }
 915         lc_ranges = static_lc_ranges;
 916         memcpy(lc_ranges, dt_ranges, rlen);
 917         orig_rlen = rlen;
 918
 919         /* Let's work on a copy of the "ranges" property instead of damaging
 920          * the device-tree image in memory
 921          */
 922         ranges = lc_ranges;
 923         prev = NULL;
 924         while ((rlen -= np * sizeof(unsigned int)) >= 0) {
 925                 if (prev) {
 926                         if (prev[0] == ranges[0] && prev[1] == ranges[1] &&
 927                                 (prev[2] + prev[na+4]) == ranges[2] &&
 928                                 (prev[na+2] + prev[na+4]) == ranges[na+2]) {
 929                                 prev[na+4] += ranges[na+4];
 930                                 ranges[0] = 0;
 931                                 ranges += np;
 932                                 continue;
 933                         }
 934                 }
 935                 prev = ranges;
 936                 ranges += np;
 937         }
 938
 939         /*
 940          * The ranges property is laid out as an array of elements,
 941          * each of which comprises:
 942          *   cells 0 - 2:       a PCI address
 943          *   cells 3 or 3+4:    a CPU physical address
 944          *                      (size depending on dev->n_addr_cells)
 945          *   cells 4+5 or 5+6:  the size of the range
 946          */
 947         ranges = lc_ranges;
 948         rlen = orig_rlen;
 949         while (ranges && (rlen -= np * sizeof(unsigned int)) >= 0) {
 950                 res = NULL;
 951                 size = ranges[na+4];
 952                 switch ((ranges[0] >> 24) & 0x3) {
 953                 case 1:         /* I/O space */
 954                         if (ranges[2] != 0)
 955                                 break;
 956                         hose->io_base_phys = ranges[na+2];
 957                         /* limit I/O space to 16MB */
 958                         if (size > 0x01000000)
 959                                 size = 0x01000000;
 960                         hose->io_base_virt = ioremap(ranges[na+2], size);
 961                         if (primary)
 962                                 isa_io_base = (unsigned long) hose->io_base_virt;
 963                         res = &hose->io_resource;
 964                         res->flags = IORESOURCE_IO;
 965                         res->start = ranges[2];
 966                         DBG("PCI: IO 0x%llx -> 0x%llx\n",
 967                             (u64)res->start, (u64)res->start + size - 1);
 968                         break;
 969                 case 2:         /* memory space */
 970                         memno = 0;
 971                         if (ranges[1] == 0 && ranges[2] == 0
 972                             && ranges[na+4] <= (16 << 20)) {
 973                                 /* 1st 16MB, i.e. ISA memory area */
 974                                 if (primary)
 975                                         isa_mem_base = ranges[na+2];
 976                                 memno = 1;
 977                         }
 978                         while (memno < 3 && hose->mem_resources[memno].flags)
 979                                 ++memno;
 980                         if (memno == 0)
 981                                 hose->pci_mem_offset = ranges[na+2] - ranges[2];
 982                         if (memno < 3) {
 983                                 res = &hose->mem_resources[memno];
 984                                 res->flags = IORESOURCE_MEM;
 985                                 if(ranges[0] & 0x40000000)
 986                                         res->flags |= IORESOURCE_PREFETCH;
 987                                 res->start = ranges[na+2];
 988                                 DBG("PCI: MEM[%d] 0x%llx -> 0x%llx\n", memno,
 989                                     (u64)res->start, (u64)res->start + size - 1);
 990                         }
 991                         break;
 992                 }
 993                 if (res != NULL) {
 994                         res->name = dev->full_name;
 995                         res->end = res->start + size - 1;
 996                         res->parent = NULL;
 997                         res->sibling = NULL;
 998                         res->child = NULL;
 999                 }
1000                 ranges += np;
1001         }
1002 }
1003
1004 /* We create the "pci-OF-bus-map" property now so it appears in the
1005  * /proc device tree
1006  */
1007 void __init
1008 pci_create_OF_bus_map(void)
1009 {
1010         struct property* of_prop;
1011         struct device_node *dn;
1012
1013         of_prop = (struct property*) alloc_bootmem(sizeof(struct property) + 256);
1014         if (!of_prop)
1015                 return;
1016         dn = of_find_node_by_path("/");
1017         if (dn) {
1018                 memset(of_prop, -1, sizeof(struct property) + 256);
1019                 of_prop->name = "pci-OF-bus-map";
1020                 of_prop->length = 256;
1021                 of_prop->value = &of_prop[1];
1022                 prom_add_property(dn, of_prop);
1023                 of_node_put(dn);
1024         }
1025 }
1026
1027 static ssize_t pci_show_devspec(struct device *dev, struct device_attribute *attr, char *buf)
1028 {
1029         struct pci_dev *pdev;
1030         struct device_node *np;
1031
1032         pdev = to_pci_dev (dev);
1033         np = pci_device_to_OF_node(pdev);
1034         if (np == NULL || np->full_name == NULL)
1035                 return 0;
1036         return sprintf(buf, "%s", np->full_name);
1037 }
1038 static DEVICE_ATTR(devspec, S_IRUGO, pci_show_devspec, NULL);
1039
1040 #else /* CONFIG_PPC_OF */
1041 void pcibios_make_OF_bus_map(void)
1042 {
1043 }
1044 #endif /* CONFIG_PPC_OF */
1045
1046 /* Add sysfs properties */
1047 void pcibios_add_platform_entries(struct pci_dev *pdev)
1048 {
1049 #ifdef CONFIG_PPC_OF
1050         device_create_file(&pdev->dev, &dev_attr_devspec);
1051 #endif /* CONFIG_PPC_OF */
1052 }
1053
1054
1055 #ifdef CONFIG_PPC_PMAC
1056 /*
1057  * This set of routines checks for PCI<->PCI bridges that have closed
1058  * IO resources and have child devices. It tries to re-open an IO
1059  * window on them.
1060  *
1061  * This is a _temporary_ fix to workaround a problem with Apple's OF
1062  * closing IO windows on P2P bridges when the OF drivers of cards
1063  * below this bridge don't claim any IO range (typically ATI or
1064  * Adaptec).
1065  *
1066  * A more complete fix would be to use drivers/pci/setup-bus.c, which
1067  * involves a working pcibios_fixup_pbus_ranges(), some more care about
1068  * ordering when creating the host bus resources, and maybe a few more
1069  * minor tweaks
1070  */
1071
1072 /* Initialize bridges with base/limit values we have collected */
1073 static void __init
1074 do_update_p2p_io_resource(struct pci_bus *bus, int enable_vga)
1075 {
1076         struct pci_dev *bridge = bus->self;
1077         struct pci_controller* hose = (struct pci_controller *)bridge->sysdata;
1078         u32 l;
1079         u16 w;
1080         struct resource res;
1081
1082         if (bus->resource[0] == NULL)
1083                 return;
1084         res = *(bus->resource[0]);
1085
1086         DBG("Remapping Bus %d, bridge: %s\n", bus->number, pci_name(bridge));
1087         res.start -= ((unsigned long) hose->io_base_virt - isa_io_base);
1088         res.end -= ((unsigned long) hose->io_base_virt - isa_io_base);
1089         DBG("  IO window: %016llx-%016llx\n", res.start, res.end);
1090
1091         /* Set up the top and bottom of the PCI I/O segment for this bus. */
1092         pci_read_config_dword(bridge, PCI_IO_BASE, &l);
1093         l &= 0xffff000f;
1094         l |= (res.start >> 8) & 0x00f0;
1095         l |= res.end & 0xf000;
1096         pci_write_config_dword(bridge, PCI_IO_BASE, l);
1097
1098         if ((l & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
1099                 l = (res.start >> 16) | (res.end & 0xffff0000);
1100                 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, l);
1101         }
1102
1103         pci_read_config_word(bridge, PCI_COMMAND, &w);
1104         w |= PCI_COMMAND_IO;
1105         pci_write_config_word(bridge, PCI_COMMAND, w);
1106
1107 #if 0 /* Enabling this causes XFree 4.2.0 to hang during PCI probe */
1108         if (enable_vga) {
1109                 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL, &w);
1110                 w |= PCI_BRIDGE_CTL_VGA;
1111                 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, w);
1112         }
1113 #endif
1114 }
1115
1116 /* This function is pretty basic and actually quite broken for the
1117  * general case, it's enough for us right now though. It's supposed
1118  * to tell us if we need to open an IO range at all or not and what
1119  * size.
1120  */
1121 static int __init
1122 check_for_io_childs(struct pci_bus *bus, struct resource* res, int *found_vga)
1123 {
1124         struct pci_dev *dev;
1125         int     i;
1126         int     rc = 0;
1127
1128 #define push_end(res, mask) do {                \
1129         BUG_ON((mask+1) & mask);                \
1130         res->end = (res->end + mask) | mask;    \
1131 } while (0)
1132
1133         list_for_each_entry(dev, &bus->devices, bus_list) {
1134                 u16 class = dev->class >> 8;
1135
1136                 if (class == PCI_CLASS_DISPLAY_VGA ||
1137                     class == PCI_CLASS_NOT_DEFINED_VGA)
1138                         *found_vga = 1;
1139                 if (class >> 8 == PCI_BASE_CLASS_BRIDGE && dev->subordinate)
1140                         rc |= check_for_io_childs(dev->subordinate, res, found_vga);
1141                 if (class == PCI_CLASS_BRIDGE_CARDBUS)
1142                         push_end(res, 0xfff);
1143
1144                 for (i=0; i<PCI_NUM_RESOURCES; i++) {
1145                         struct resource *r;
1146                         unsigned long r_size;
1147
1148                         if (dev->class >> 8 == PCI_CLASS_BRIDGE_PCI
1149                             && i >= PCI_BRIDGE_RESOURCES)
1150                                 continue;
1151                         r = &dev->resource[i];
1152                         r_size = r->end - r->start;
1153                         if (r_size < 0xfff)
1154                                 r_size = 0xfff;
1155                         if (r->flags & IORESOURCE_IO && (r_size) != 0) {
1156                                 rc = 1;
1157                                 push_end(res, r_size);
1158                         }
1159                 }
1160         }
1161
1162         return rc;
1163 }
1164
1165 /* Here we scan all P2P bridges of a given level that have a closed
1166  * IO window. Note that the test for the presence of a VGA card should
1167  * be improved to take into account already configured P2P bridges,
1168  * currently, we don't see them and might end up configuring 2 bridges
1169  * with VGA pass through enabled
1170  */
1171 static void __init
1172 do_fixup_p2p_level(struct pci_bus *bus)
1173 {
1174         struct pci_bus *b;
1175         int i, parent_io;
1176         int has_vga = 0;
1177
1178         for (parent_io=0; parent_io<4; parent_io++)
1179                 if (bus->resource[parent_io]
1180                     && bus->resource[parent_io]->flags & IORESOURCE_IO)
1181                         break;
1182         if (parent_io >= 4)
1183                 return;
1184
1185         list_for_each_entry(b, &bus->children, node) {
1186                 struct pci_dev *d = b->self;
1187                 struct pci_controller* hose = (struct pci_controller *)d->sysdata;
1188                 struct resource *res = b->resource[0];
1189                 struct resource tmp_res;
1190                 unsigned long max;
1191                 int found_vga = 0;
1192
1193                 memset(&tmp_res, 0, sizeof(tmp_res));
1194                 tmp_res.start = bus->resource[parent_io]->start;
1195
1196                 /* We don't let low addresses go through that closed P2P bridge, well,
1197                  * that may not be necessary but I feel safer that way
1198                  */
1199                 if (tmp_res.start == 0)
1200                         tmp_res.start = 0x1000;
1201
1202                 if (!list_empty(&b->devices) && res && res->flags == 0 &&
1203                     res != bus->resource[parent_io] &&
1204                     (d->class >> 8) == PCI_CLASS_BRIDGE_PCI &&
1205                     check_for_io_childs(b, &tmp_res, &found_vga)) {
1206                         u8 io_base_lo;
1207
1208                         printk(KERN_INFO "Fixing up IO bus %s\n", b->name);
1209
1210                         if (found_vga) {
1211                                 if (has_vga) {
1212                                         printk(KERN_WARNING "Skipping VGA, already active"
1213                                             " on bus segment\n");
1214                                         found_vga = 0;
1215                                 } else
1216                                         has_vga = 1;
1217                         }
1218                         pci_read_config_byte(d, PCI_IO_BASE, &io_base_lo);
1219
1220                         if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32)
1221                                 max = ((unsigned long) hose->io_base_virt
1222                                         - isa_io_base) + 0xffffffff;
1223                         else
1224                                 max = ((unsigned long) hose->io_base_virt
1225                                         - isa_io_base) + 0xffff;
1226
1227                         *res = tmp_res;
1228                         res->flags = IORESOURCE_IO;
1229                         res->name = b->name;
1230
1231                         /* Find a resource in the parent where we can allocate */
1232                         for (i = 0 ; i < 4; i++) {
1233                                 struct resource *r = bus->resource[i];
1234                                 if (!r)
1235                                         continue;
1236                                 if ((r->flags & IORESOURCE_IO) == 0)
1237                                         continue;
1238                                 DBG("Trying to allocate from %016llx, size %016llx from parent"
1239                                     " res %d: %016llx -> %016llx\n",
1240                                         res->start, res->end, i, r->start, r->end);
1241
1242                                 if (allocate_resource(r, res, res->end + 1, res->start, max,
1243                                     res->end + 1, NULL, NULL) < 0) {
1244                                         DBG("Failed !\n");
1245                                         continue;
1246                                 }
1247                                 do_update_p2p_io_resource(b, found_vga);
1248                                 break;
1249                         }
1250                 }
1251                 do_fixup_p2p_level(b);
1252         }
1253 }
1254
1255 static void
1256 pcibios_fixup_p2p_bridges(void)
1257 {
1258         struct pci_bus *b;
1259
1260         list_for_each_entry(b, &pci_root_buses, node)
1261                 do_fixup_p2p_level(b);
1262 }
1263
1264 #endif /* CONFIG_PPC_PMAC */
1265
1266 static int __init
1267 pcibios_init(void)
1268 {
1269         struct pci_controller *hose;
1270         struct pci_bus *bus;
1271         int next_busno;
1272
1273         printk(KERN_INFO "PCI: Probing PCI hardware\n");
1274
1275         /* Scan all of the recorded PCI controllers.  */
1276         for (next_busno = 0, hose = hose_head; hose; hose = hose->next) {
1277                 if (pci_assign_all_buses)
1278                         hose->first_busno = next_busno;
1279                 hose->last_busno = 0xff;
1280                 bus = pci_scan_bus_parented(hose->parent, hose->first_busno,
1281                                             hose->ops, hose);
1282                 if (bus)
1283                         pci_bus_add_devices(bus);
1284                 hose->last_busno = bus->subordinate;
1285                 if (pci_assign_all_buses || next_busno <= hose->last_busno)
1286                         next_busno = hose->last_busno + pcibios_assign_bus_offset;
1287         }
1288         pci_bus_count = next_busno;
1289
1290         /* OpenFirmware based machines need a map of OF bus
1291          * numbers vs. kernel bus numbers since we may have to
1292          * remap them.
1293          */
1294         if (pci_assign_all_buses && have_of)
1295                 pcibios_make_OF_bus_map();
1296
1297         /* Call machine dependent fixup */
1298         if (ppc_md.pcibios_fixup)
1299                 ppc_md.pcibios_fixup();
1300
1301         /* Allocate and assign resources */
1302         pcibios_allocate_bus_resources(&pci_root_buses);
1303         pcibios_allocate_resources(0);
1304         pcibios_allocate_resources(1);
1305 #ifdef CONFIG_PPC_PMAC
1306         pcibios_fixup_p2p_bridges();
1307 #endif /* CONFIG_PPC_PMAC */
1308         pcibios_assign_resources();
1309
1310         /* Call machine dependent post-init code */
1311         if (ppc_md.pcibios_after_init)
1312                 ppc_md.pcibios_after_init();
1313
1314         return 0;
1315 }
1316
1317 subsys_initcall(pcibios_init);
1318
1319 unsigned long resource_fixup(struct pci_dev * dev, struct resource * res,
1320                              unsigned long start, unsigned long size)
1321 {
1322         return start;
1323 }
1324
1325 void __init pcibios_fixup_bus(struct pci_bus *bus)
1326 {
1327         struct pci_controller *hose = (struct pci_controller *) bus->sysdata;
1328         unsigned long io_offset;
1329         struct resource *res;
1330         struct pci_dev *dev;
1331         int i;
1332
1333         io_offset = (unsigned long)hose->io_base_virt - isa_io_base;
1334         if (bus->parent == NULL) {
1335                 /* This is a host bridge - fill in its resources */
1336                 hose->bus = bus;
1337
1338                 bus->resource[0] = res = &hose->io_resource;
1339                 if (!res->flags) {
1340                         if (io_offset)
1341                                 printk(KERN_ERR "I/O resource not set for host"
1342                                        " bridge %d\n", hose->index);
1343                         res->start = 0;
1344                         res->end = IO_SPACE_LIMIT;
1345                         res->flags = IORESOURCE_IO;
1346                 }
1347                 res->start += io_offset;
1348                 res->end += io_offset;
1349
1350                 for (i = 0; i < 3; ++i) {
1351                         res = &hose->mem_resources[i];
1352                         if (!res->flags) {
1353                                 if (i > 0)
1354                                         continue;
1355                                 printk(KERN_ERR "Memory resource not set for "
1356                                        "host bridge %d\n", hose->index);
1357                                 res->start = hose->pci_mem_offset;
1358                                 res->end = ~0U;
1359                                 res->flags = IORESOURCE_MEM;
1360                         }
1361                         bus->resource[i+1] = res;
1362                 }
1363         } else {
1364                 /* This is a subordinate bridge */
1365                 pci_read_bridge_bases(bus);
1366
1367                 for (i = 0; i < 4; ++i) {
1368                         if ((res = bus->resource[i]) == NULL)
1369                                 continue;
1370                         if (!res->flags)
1371                                 continue;
1372                         if (io_offset && (res->flags & IORESOURCE_IO)) {
1373                                 res->start += io_offset;
1374                                 res->end += io_offset;
1375                         } else if (hose->pci_mem_offset
1376                                    && (res->flags & IORESOURCE_MEM)) {
1377                                 res->start += hose->pci_mem_offset;
1378                                 res->end += hose->pci_mem_offset;
1379                         }
1380                 }
1381         }
1382
1383         /* Platform specific bus fixups */
1384         if (ppc_md.pcibios_fixup_bus)
1385                 ppc_md.pcibios_fixup_bus(bus);
1386
1387         /* Read default IRQs and fixup if necessary */
1388         list_for_each_entry(dev, &bus->devices, bus_list) {
1389                 pci_read_irq_line(dev);
1390                 if (ppc_md.pci_irq_fixup)
1391                         ppc_md.pci_irq_fixup(dev);
1392         }
1393 }
1394
1395 char __init *pcibios_setup(char *str)
1396 {
1397         return str;
1398 }
1399
1400 /* the next one is stolen from the alpha port... */
1401 void __init
1402 pcibios_update_irq(struct pci_dev *dev, int irq)
1403 {
1404         pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
1405         /* XXX FIXME - update OF device tree node interrupt property */
1406 }
1407
1408 #ifdef CONFIG_PPC_MERGE
1409 /* XXX This is a copy of the ppc64 version. This is temporary until we start
1410  * merging the 2 PCI layers
1411  */
1412 /*
1413  * Reads the interrupt pin to determine if interrupt is use by card.
1414  * If the interrupt is used, then gets the interrupt line from the
1415  * openfirmware and sets it in the pci_dev and pci_config line.
1416  */
1417 int pci_read_irq_line(struct pci_dev *pci_dev)
1418 {
1419         struct of_irq oirq;
1420         unsigned int virq;
1421
1422         DBG("Try to map irq for %s...\n", pci_name(pci_dev));
1423
1424         /* Try to get a mapping from the device-tree */
1425         if (of_irq_map_pci(pci_dev, &oirq)) {
1426                 u8 line, pin;
1427
1428                 /* If that fails, lets fallback to what is in the config
1429                  * space and map that through the default controller. We
1430                  * also set the type to level low since that's what PCI
1431                  * interrupts are. If your platform does differently, then
1432                  * either provide a proper interrupt tree or don't use this
1433                  * function.
1434                  */
1435                 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &pin))
1436                         return -1;
1437                 if (pin == 0)
1438                         return -1;
1439                 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) ||
1440                     line == 0xff) {
1441                         return -1;
1442                 }
1443                 DBG(" -> no map ! Using irq line %d from PCI config\n", line);
1444
1445                 virq = irq_create_mapping(NULL, line);
1446                 if (virq != NO_IRQ)
1447                         set_irq_type(virq, IRQ_TYPE_LEVEL_LOW);
1448         } else {
1449                 DBG(" -> got one, spec %d cells (0x%08x...) on %s\n",
1450                     oirq.size, oirq.specifier[0], oirq.controller->full_name);
1451
1452                 virq = irq_create_of_mapping(oirq.controller, oirq.specifier,
1453                                              oirq.size);
1454         }
1455         if(virq == NO_IRQ) {
1456                 DBG(" -> failed to map !\n");
1457                 return -1;
1458         }
1459         pci_dev->irq = virq;
1460
1461         return 0;
1462 }
1463 EXPORT_SYMBOL(pci_read_irq_line);
1464 #endif /* CONFIG_PPC_MERGE */
1465
1466 int pcibios_enable_device(struct pci_dev *dev, int mask)
1467 {
1468         u16 cmd, old_cmd;
1469         int idx;
1470         struct resource *r;
1471
1472         if (ppc_md.pcibios_enable_device_hook)
1473                 if (ppc_md.pcibios_enable_device_hook(dev, 0))
1474                         return -EINVAL;
1475
1476         pci_read_config_word(dev, PCI_COMMAND, &cmd);
1477         old_cmd = cmd;
1478         for (idx=0; idx<6; idx++) {
1479                 r = &dev->resource[idx];
1480                 if (r->flags & IORESOURCE_UNSET) {
1481                         printk(KERN_ERR "PCI: Device %s not available because of resource collisions\n", pci_name(dev));
1482                         return -EINVAL;
1483                 }
1484                 if (r->flags & IORESOURCE_IO)
1485                         cmd |= PCI_COMMAND_IO;
1486                 if (r->flags & IORESOURCE_MEM)
1487                         cmd |= PCI_COMMAND_MEMORY;
1488         }
1489         if (cmd != old_cmd) {
1490                 printk("PCI: Enabling device %s (%04x -> %04x)\n",
1491                        pci_name(dev), old_cmd, cmd);
1492                 pci_write_config_word(dev, PCI_COMMAND, cmd);
1493         }
1494         return 0;
1495 }
1496
1497 struct pci_controller*
1498 pci_bus_to_hose(int bus)
1499 {
1500         struct pci_controller* hose = hose_head;
1501
1502         for (; hose; hose = hose->next)
1503                 if (bus >= hose->first_busno && bus <= hose->last_busno)
1504                         return hose;
1505         return NULL;
1506 }
1507
1508 void __iomem *
1509 pci_bus_io_base(unsigned int bus)
1510 {
1511         struct pci_controller *hose;
1512
1513         hose = pci_bus_to_hose(bus);
1514         if (!hose)
1515                 return NULL;
1516         return hose->io_base_virt;
1517 }
1518
1519 unsigned long
1520 pci_bus_io_base_phys(unsigned int bus)
1521 {
1522         struct pci_controller *hose;
1523
1524         hose = pci_bus_to_hose(bus);
1525         if (!hose)
1526                 return 0;
1527         return hose->io_base_phys;
1528 }
1529
1530 unsigned long
1531 pci_bus_mem_base_phys(unsigned int bus)
1532 {
1533         struct pci_controller *hose;
1534
1535         hose = pci_bus_to_hose(bus);
1536         if (!hose)
1537                 return 0;
1538         return hose->pci_mem_offset;
1539 }
1540
1541 unsigned long
1542 pci_resource_to_bus(struct pci_dev *pdev, struct resource *res)
1543 {
1544         /* Hack alert again ! See comments in chrp_pci.c
1545          */
1546         struct pci_controller* hose =
1547                 (struct pci_controller *)pdev->sysdata;
1548         if (hose && res->flags & IORESOURCE_MEM)
1549                 return res->start - hose->pci_mem_offset;
1550         /* We may want to do something with IOs here... */
1551         return res->start;
1552 }
1553
1554
1555 static struct resource *__pci_mmap_make_offset(struct pci_dev *dev,
1556                                                resource_size_t *offset,
1557                                                enum pci_mmap_state mmap_state)
1558 {
1559         struct pci_controller *hose = pci_bus_to_hose(dev->bus->number);
1560         unsigned long io_offset = 0;
1561         int i, res_bit;
1562
1563         if (hose == 0)
1564                 return NULL;            /* should never happen */
1565
1566         /* If memory, add on the PCI bridge address offset */
1567         if (mmap_state == pci_mmap_mem) {
1568 #if 0 /* See comment in pci_resource_to_user() for why this is disabled */
1569                 *offset += hose->pci_mem_offset;
1570 #endif
1571                 res_bit = IORESOURCE_MEM;
1572         } else {
1573                 io_offset = hose->io_base_virt - (void __iomem *)_IO_BASE;
1574                 *offset += io_offset;
1575                 res_bit = IORESOURCE_IO;
1576         }
1577
1578         /*
1579          * Check that the offset requested corresponds to one of the
1580          * resources of the device.
1581          */
1582         for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
1583                 struct resource *rp = &dev->resource[i];
1584                 int flags = rp->flags;
1585
1586                 /* treat ROM as memory (should be already) */
1587                 if (i == PCI_ROM_RESOURCE)
1588                         flags |= IORESOURCE_MEM;
1589
1590                 /* Active and same type? */
1591                 if ((flags & res_bit) == 0)
1592                         continue;
1593
1594                 /* In the range of this resource? */
1595                 if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end)
1596                         continue;
1597
1598                 /* found it! construct the final physical address */
1599                 if (mmap_state == pci_mmap_io)
1600                         *offset += hose->io_base_phys - io_offset;
1601                 return rp;
1602         }
1603
1604         return NULL;
1605 }
1606
1607 /*
1608  * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
1609  * device mapping.
1610  */
1611 static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp,
1612                                       pgprot_t protection,
1613                                       enum pci_mmap_state mmap_state,
1614                                       int write_combine)
1615 {
1616         unsigned long prot = pgprot_val(protection);
1617
1618         /* Write combine is always 0 on non-memory space mappings. On
1619          * memory space, if the user didn't pass 1, we check for a
1620          * "prefetchable" resource. This is a bit hackish, but we use
1621          * this to workaround the inability of /sysfs to provide a write
1622          * combine bit
1623          */
1624         if (mmap_state != pci_mmap_mem)
1625                 write_combine = 0;
1626         else if (write_combine == 0) {
1627                 if (rp->flags & IORESOURCE_PREFETCH)
1628                         write_combine = 1;
1629         }
1630
1631         /* XXX would be nice to have a way to ask for write-through */
1632         prot |= _PAGE_NO_CACHE;
1633         if (write_combine)
1634                 prot &= ~_PAGE_GUARDED;
1635         else
1636                 prot |= _PAGE_GUARDED;
1637
1638         return __pgprot(prot);
1639 }
1640
1641 /*
1642  * This one is used by /dev/mem and fbdev who have no clue about the
1643  * PCI device, it tries to find the PCI device first and calls the
1644  * above routine
1645  */
1646 pgprot_t pci_phys_mem_access_prot(struct file *file,
1647                                   unsigned long pfn,
1648                                   unsigned long size,
1649                                   pgprot_t protection)
1650 {
1651         struct pci_dev *pdev = NULL;
1652         struct resource *found = NULL;
1653         unsigned long prot = pgprot_val(protection);
1654         unsigned long offset = pfn << PAGE_SHIFT;
1655         int i;
1656
1657         if (page_is_ram(pfn))
1658                 return prot;
1659
1660         prot |= _PAGE_NO_CACHE | _PAGE_GUARDED;
1661
1662         for_each_pci_dev(pdev) {
1663                 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
1664                         struct resource *rp = &pdev->resource[i];
1665                         int flags = rp->flags;
1666
1667                         /* Active and same type? */
1668                         if ((flags & IORESOURCE_MEM) == 0)
1669                                 continue;
1670                         /* In the range of this resource? */
1671                         if (offset < (rp->start & PAGE_MASK) ||
1672                             offset > rp->end)
1673                                 continue;
1674                         found = rp;
1675                         break;
1676                 }
1677                 if (found)
1678                         break;
1679         }
1680         if (found) {
1681                 if (found->flags & IORESOURCE_PREFETCH)
1682                         prot &= ~_PAGE_GUARDED;
1683                 pci_dev_put(pdev);
1684         }
1685
1686         DBG("non-PCI map for %lx, prot: %lx\n", offset, prot);
1687
1688         return __pgprot(prot);
1689 }
1690
1691
1692 /*
1693  * Perform the actual remap of the pages for a PCI device mapping, as
1694  * appropriate for this architecture.  The region in the process to map
1695  * is described by vm_start and vm_end members of VMA, the base physical
1696  * address is found in vm_pgoff.
1697  * The pci device structure is provided so that architectures may make mapping
1698  * decisions on a per-device or per-bus basis.
1699  *
1700  * Returns a negative error code on failure, zero on success.
1701  */
1702 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
1703                         enum pci_mmap_state mmap_state,
1704                         int write_combine)
1705 {
1706         resource_size_t offset = vma->vm_pgoff << PAGE_SHIFT;
1707         struct resource *rp;
1708         int ret;
1709
1710         rp = __pci_mmap_make_offset(dev, &offset, mmap_state);
1711         if (rp == NULL)
1712                 return -EINVAL;
1713
1714         vma->vm_pgoff = offset >> PAGE_SHIFT;
1715         vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp,
1716                                                   vma->vm_page_prot,
1717                                                   mmap_state, write_combine);
1718
1719         ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
1720                                vma->vm_end - vma->vm_start, vma->vm_page_prot);
1721
1722         return ret;
1723 }
1724
1725 /* Obsolete functions. Should be removed once the symbios driver
1726  * is fixed
1727  */
1728 unsigned long
1729 phys_to_bus(unsigned long pa)
1730 {
1731         struct pci_controller *hose;
1732         int i;
1733
1734         for (hose = hose_head; hose; hose = hose->next) {
1735                 for (i = 0; i < 3; ++i) {
1736                         if (pa >= hose->mem_resources[i].start
1737                             && pa <= hose->mem_resources[i].end) {
1738                                 /*
1739                                  * XXX the hose->pci_mem_offset really
1740                                  * only applies to mem_resources[0].
1741                                  * We need a way to store an offset for
1742                                  * the others.  -- paulus
1743                                  */
1744                                 if (i == 0)
1745                                         pa -= hose->pci_mem_offset;
1746                                 return pa;
1747                         }
1748                 }
1749         }
1750         /* hmmm, didn't find it */
1751         return 0;
1752 }
1753
1754 unsigned long
1755 pci_phys_to_bus(unsigned long pa, int busnr)
1756 {
1757         struct pci_controller* hose = pci_bus_to_hose(busnr);
1758         if (!hose)
1759                 return pa;
1760         return pa - hose->pci_mem_offset;
1761 }
1762
1763 unsigned long
1764 pci_bus_to_phys(unsigned int ba, int busnr)
1765 {
1766         struct pci_controller* hose = pci_bus_to_hose(busnr);
1767         if (!hose)
1768                 return ba;
1769         return ba + hose->pci_mem_offset;
1770 }
1771
1772 /* Provide information on locations of various I/O regions in physical
1773  * memory.  Do this on a per-card basis so that we choose the right
1774  * root bridge.
1775  * Note that the returned IO or memory base is a physical address
1776  */
1777
1778 long sys_pciconfig_iobase(long which, unsigned long bus, unsigned long devfn)
1779 {
1780         struct pci_controller* hose;
1781         long result = -EOPNOTSUPP;
1782
1783         /* Argh ! Please forgive me for that hack, but that's the
1784          * simplest way to get existing XFree to not lockup on some
1785          * G5 machines... So when something asks for bus 0 io base
1786          * (bus 0 is HT root), we return the AGP one instead.
1787          */
1788 #ifdef CONFIG_PPC_PMAC
1789         if (machine_is(powermac) && machine_is_compatible("MacRISC4"))
1790                 if (bus == 0)
1791                         bus = 0xf0;
1792 #endif /* CONFIG_PPC_PMAC */
1793
1794         hose = pci_bus_to_hose(bus);
1795         if (!hose)
1796                 return -ENODEV;
1797
1798         switch (which) {
1799         case IOBASE_BRIDGE_NUMBER:
1800                 return (long)hose->first_busno;
1801         case IOBASE_MEMORY:
1802                 return (long)hose->pci_mem_offset;
1803         case IOBASE_IO:
1804                 return (long)hose->io_base_phys;
1805         case IOBASE_ISA_IO:
1806                 return (long)isa_io_base;
1807         case IOBASE_ISA_MEM:
1808                 return (long)isa_mem_base;
1809         }
1810
1811         return result;
1812 }
1813
1814 void pci_resource_to_user(const struct pci_dev *dev, int bar,
1815                           const struct resource *rsrc,
1816                           resource_size_t *start, resource_size_t *end)
1817 {
1818         struct pci_controller *hose = pci_bus_to_hose(dev->bus->number);
1819         resource_size_t offset = 0;
1820
1821         if (hose == NULL)
1822                 return;
1823
1824         if (rsrc->flags & IORESOURCE_IO)
1825                 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
1826
1827         /* We pass a fully fixed up address to userland for MMIO instead of
1828          * a BAR value because X is lame and expects to be able to use that
1829          * to pass to /dev/mem !
1830          *
1831          * That means that we'll have potentially 64 bits values where some
1832          * userland apps only expect 32 (like X itself since it thinks only
1833          * Sparc has 64 bits MMIO) but if we don't do that, we break it on
1834          * 32 bits CHRPs :-(
1835          *
1836          * Hopefully, the sysfs insterface is immune to that gunk. Once X
1837          * has been fixed (and the fix spread enough), we can re-enable the
1838          * 2 lines below and pass down a BAR value to userland. In that case
1839          * we'll also have to re-enable the matching code in
1840          * __pci_mmap_make_offset().
1841          *
1842          * BenH.
1843          */
1844 #if 0
1845         else if (rsrc->flags & IORESOURCE_MEM)
1846                 offset = hose->pci_mem_offset;
1847 #endif
1848
1849         *start = rsrc->start - offset;
1850         *end = rsrc->end - offset;
1851 }
1852
1853 void __init pci_init_resource(struct resource *res, resource_size_t start,
1854                               resource_size_t end, int flags, char *name)
1855 {
1856         res->start = start;
1857         res->end = end;
1858         res->flags = flags;
1859         res->name = name;
1860         res->parent = NULL;
1861         res->sibling = NULL;
1862         res->child = NULL;
1863 }
1864
1865 unsigned long pci_address_to_pio(phys_addr_t address)
1866 {
1867         struct pci_controller* hose = hose_head;
1868
1869         for (; hose; hose = hose->next) {
1870                 unsigned int size = hose->io_resource.end -
1871                         hose->io_resource.start + 1;
1872                 if (address >= hose->io_base_phys &&
1873                     address < (hose->io_base_phys + size)) {
1874                         unsigned long base =
1875                                 (unsigned long)hose->io_base_virt - _IO_BASE;
1876                         return base + (address - hose->io_base_phys);
1877                 }
1878         }
1879         return (unsigned int)-1;
1880 }
1881 EXPORT_SYMBOL(pci_address_to_pio);
1882
1883 /*
1884  * Null PCI config access functions, for the case when we can't
1885  * find a hose.
1886  */
1887 #define NULL_PCI_OP(rw, size, type)                                     \
1888 static int                                                              \
1889 null_##rw##_config_##size(struct pci_dev *dev, int offset, type val)    \
1890 {                                                                       \
1891         return PCIBIOS_DEVICE_NOT_FOUND;                                \
1892 }
1893
1894 static int
1895 null_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
1896                  int len, u32 *val)
1897 {
1898         return PCIBIOS_DEVICE_NOT_FOUND;
1899 }
1900
1901 static int
1902 null_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
1903                   int len, u32 val)
1904 {
1905         return PCIBIOS_DEVICE_NOT_FOUND;
1906 }
1907
1908 static struct pci_ops null_pci_ops =
1909 {
1910         null_read_config,
1911         null_write_config
1912 };
1913
1914 /*
1915  * These functions are used early on before PCI scanning is done
1916  * and all of the pci_dev and pci_bus structures have been created.
1917  */
1918 static struct pci_bus *
1919 fake_pci_bus(struct pci_controller *hose, int busnr)
1920 {
1921         static struct pci_bus bus;
1922
1923         if (hose == 0) {
1924                 hose = pci_bus_to_hose(busnr);
1925                 if (hose == 0)
1926                         printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr);
1927         }
1928         bus.number = busnr;
1929         bus.sysdata = hose;
1930         bus.ops = hose? hose->ops: &null_pci_ops;
1931         return &bus;
1932 }
1933
1934 #define EARLY_PCI_OP(rw, size, type)                                    \
1935 int early_##rw##_config_##size(struct pci_controller *hose, int bus,    \
1936                                int devfn, int offset, type value)       \
1937 {                                                                       \
1938         return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus),    \
1939                                             devfn, offset, value);      \
1940 }
1941
1942 EARLY_PCI_OP(read, byte, u8 *)
1943 EARLY_PCI_OP(read, word, u16 *)
1944 EARLY_PCI_OP(read, dword, u32 *)
1945 EARLY_PCI_OP(write, byte, u8)
1946 EARLY_PCI_OP(write, word, u16)
1947 EARLY_PCI_OP(write, dword, u32)