2 * arch/ppc64/kernel/head.S
5 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
7 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
8 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
9 * Adapted for Power Macintosh by Paul Mackerras.
10 * Low-level exception handlers and MMU support
11 * rewritten by Paul Mackerras.
12 * Copyright (C) 1996 Paul Mackerras.
14 * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and
15 * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com
17 * This file contains the low-level support and setup for the
18 * PowerPC-64 platform, including trap and interrupt dispatch.
20 * This program is free software; you can redistribute it and/or
21 * modify it under the terms of the GNU General Public License
22 * as published by the Free Software Foundation; either version
23 * 2 of the License, or (at your option) any later version.
26 #include <linux/config.h>
27 #include <linux/threads.h>
31 #include <asm/ppc_asm.h>
32 #include <asm/asm-offsets.h>
34 #include <asm/cputable.h>
35 #include <asm/setup.h>
36 #include <asm/hvcall.h>
37 #include <asm/iseries/lpar_map.h>
38 #include <asm/thread_info.h>
40 #ifdef CONFIG_PPC_ISERIES
41 #define DO_SOFT_DISABLE
45 * We layout physical memory as follows:
46 * 0x0000 - 0x00ff : Secondary processor spin code
47 * 0x0100 - 0x2fff : pSeries Interrupt prologs
48 * 0x3000 - 0x5fff : interrupt support, iSeries and common interrupt prologs
49 * 0x6000 - 0x6fff : Initial (CPU0) segment table
50 * 0x7000 - 0x7fff : FWNMI data area
51 * 0x8000 - : Early init and support code
59 * SPRG0 reserved for hypervisor
60 * SPRG1 temp - used to save gpr
61 * SPRG2 temp - used to save gpr
62 * SPRG3 virt addr of paca
66 * Entering into this code we make the following assumptions:
68 * 1. The MMU is off & open firmware is running in real mode.
69 * 2. The kernel is entered at __start
72 * 1. The MMU is on (as it always is for iSeries)
73 * 2. The kernel is entered at system_reset_iSeries
79 #ifdef CONFIG_PPC_MULTIPLATFORM
81 /* NOP this out unconditionally */
83 b .__start_initialization_multiplatform
85 #endif /* CONFIG_PPC_MULTIPLATFORM */
87 /* Catch branch to 0 in real mode */
90 #ifdef CONFIG_PPC_ISERIES
92 * At offset 0x20, there is a pointer to iSeries LPAR data.
93 * This is required by the hypervisor
96 .llong hvReleaseData-KERNELBASE
99 * At offset 0x28 and 0x30 are offsets to the mschunks_map
100 * array (used by the iSeries LPAR debugger to do translation
101 * between physical addresses and absolute addresses) and
102 * to the pidhash table (also used by the debugger)
104 .llong mschunks_map-KERNELBASE
105 .llong 0 /* pidhash-KERNELBASE SFRXXX */
107 /* Offset 0x38 - Pointer to start of embedded System.map */
108 .globl embedded_sysmap_start
109 embedded_sysmap_start:
111 /* Offset 0x40 - Pointer to end of embedded System.map */
112 .globl embedded_sysmap_end
116 #endif /* CONFIG_PPC_ISERIES */
118 /* Secondary processors spin on this value until it goes to 1. */
119 .globl __secondary_hold_spinloop
120 __secondary_hold_spinloop:
123 /* Secondary processors write this value with their cpu # */
124 /* after they enter the spin loop immediately below. */
125 .globl __secondary_hold_acknowledge
126 __secondary_hold_acknowledge:
131 * The following code is used on pSeries to hold secondary processors
132 * in a spin loop after they have been freed from OpenFirmware, but
133 * before the bulk of the kernel has been relocated. This code
134 * is relocated to physical address 0x60 before prom_init is run.
135 * All of it must fit below the first exception vector at 0x100.
137 _GLOBAL(__secondary_hold)
140 mtmsrd r24 /* RI on */
142 /* Grab our linux cpu number */
145 /* Tell the master cpu we're here */
146 /* Relocation is off & we are located at an address less */
147 /* than 0x100, so only need to grab low order offset. */
148 std r24,__secondary_hold_acknowledge@l(0)
151 /* All secondary cpus wait here until told to start. */
152 100: ld r4,__secondary_hold_spinloop@l(0)
161 b .pSeries_secondary_smp_init
167 /* This value is used to mark exception frames on the stack. */
170 .tc ID_72656773_68657265[TC],0x7265677368657265
174 * The following macros define the code that appears as
175 * the prologue to each of the exception handlers. They
176 * are split into two parts to allow a single kernel binary
177 * to be used for pSeries and iSeries.
178 * LOL. One day... - paulus
182 * We make as much of the exception code common between native
183 * exception handlers (including pSeries LPAR) and iSeries LPAR
184 * implementations as possible.
188 * This is the start of the interrupt handlers for pSeries
189 * This code runs with relocation off.
203 #define EXCEPTION_PROLOG_PSERIES(area, label) \
204 mfspr r13,SPRN_SPRG3; /* get paca address into r13 */ \
205 std r9,area+EX_R9(r13); /* save r9 - r12 */ \
206 std r10,area+EX_R10(r13); \
207 std r11,area+EX_R11(r13); \
208 std r12,area+EX_R12(r13); \
209 mfspr r9,SPRN_SPRG1; \
210 std r9,area+EX_R13(r13); \
212 clrrdi r12,r13,32; /* get high part of &label */ \
214 mfspr r11,SPRN_SRR0; /* save SRR0 */ \
215 ori r12,r12,(label)@l; /* virt addr of handler */ \
216 ori r10,r10,MSR_IR|MSR_DR|MSR_RI; \
217 mtspr SPRN_SRR0,r12; \
218 mfspr r12,SPRN_SRR1; /* and SRR1 */ \
219 mtspr SPRN_SRR1,r10; \
221 b . /* prevent speculative execution */
224 * This is the start of the interrupt handlers for iSeries
225 * This code runs with relocation on.
227 #define EXCEPTION_PROLOG_ISERIES_1(area) \
228 mfspr r13,SPRN_SPRG3; /* get paca address into r13 */ \
229 std r9,area+EX_R9(r13); /* save r9 - r12 */ \
230 std r10,area+EX_R10(r13); \
231 std r11,area+EX_R11(r13); \
232 std r12,area+EX_R12(r13); \
233 mfspr r9,SPRN_SPRG1; \
234 std r9,area+EX_R13(r13); \
237 #define EXCEPTION_PROLOG_ISERIES_2 \
239 ld r11,PACALPPACA+LPPACASRR0(r13); \
240 ld r12,PACALPPACA+LPPACASRR1(r13); \
241 ori r10,r10,MSR_RI; \
245 * The common exception prolog is used for all except a few exceptions
246 * such as a segment miss on a kernel address. We have to be prepared
247 * to take another exception from the point where we first touch the
248 * kernel stack onwards.
250 * On entry r13 points to the paca, r9-r13 are saved in the paca,
251 * r9 contains the saved CR, r11 and r12 contain the saved SRR0 and
252 * SRR1, and relocation is on.
254 #define EXCEPTION_PROLOG_COMMON(n, area) \
255 andi. r10,r12,MSR_PR; /* See if coming from user */ \
256 mr r10,r1; /* Save r1 */ \
257 subi r1,r1,INT_FRAME_SIZE; /* alloc frame on kernel stack */ \
259 ld r1,PACAKSAVE(r13); /* kernel stack to use */ \
260 1: cmpdi cr1,r1,0; /* check if r1 is in userspace */ \
261 bge- cr1,bad_stack; /* abort if it is */ \
262 std r9,_CCR(r1); /* save CR in stackframe */ \
263 std r11,_NIP(r1); /* save SRR0 in stackframe */ \
264 std r12,_MSR(r1); /* save SRR1 in stackframe */ \
265 std r10,0(r1); /* make stack chain pointer */ \
266 std r0,GPR0(r1); /* save r0 in stackframe */ \
267 std r10,GPR1(r1); /* save r1 in stackframe */ \
268 std r2,GPR2(r1); /* save r2 in stackframe */ \
269 SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \
270 SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \
271 ld r9,area+EX_R9(r13); /* move r9, r10 to stackframe */ \
272 ld r10,area+EX_R10(r13); \
275 ld r9,area+EX_R11(r13); /* move r11 - r13 to stackframe */ \
276 ld r10,area+EX_R12(r13); \
277 ld r11,area+EX_R13(r13); \
281 ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \
282 mflr r9; /* save LR in stackframe */ \
284 mfctr r10; /* save CTR in stackframe */ \
286 mfspr r11,SPRN_XER; /* save XER in stackframe */ \
289 std r9,_TRAP(r1); /* set trap number */ \
291 ld r11,exception_marker@toc(r2); \
292 std r10,RESULT(r1); /* clear regs->result */ \
293 std r11,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */
298 #define STD_EXCEPTION_PSERIES(n, label) \
300 .globl label##_pSeries; \
303 mtspr SPRN_SPRG1,r13; /* save r13 */ \
305 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common)
307 #define STD_EXCEPTION_ISERIES(n, label, area) \
308 .globl label##_iSeries; \
311 mtspr SPRN_SPRG1,r13; /* save r13 */ \
313 EXCEPTION_PROLOG_ISERIES_1(area); \
314 EXCEPTION_PROLOG_ISERIES_2; \
317 #define MASKABLE_EXCEPTION_ISERIES(n, label) \
318 .globl label##_iSeries; \
321 mtspr SPRN_SPRG1,r13; /* save r13 */ \
323 EXCEPTION_PROLOG_ISERIES_1(PACA_EXGEN); \
324 lbz r10,PACAPROCENABLED(r13); \
326 beq- label##_iSeries_masked; \
327 EXCEPTION_PROLOG_ISERIES_2; \
330 #ifdef DO_SOFT_DISABLE
331 #define DISABLE_INTS \
332 lbz r10,PACAPROCENABLED(r13); \
336 stb r11,PACAPROCENABLED(r13); \
337 ori r10,r10,MSR_EE; \
340 #define ENABLE_INTS \
341 lbz r10,PACAPROCENABLED(r13); \
344 ori r11,r11,MSR_EE; \
347 #else /* hard enable/disable interrupts */
350 #define ENABLE_INTS \
353 rlwimi r11,r12,0,MSR_EE; \
358 #define STD_EXCEPTION_COMMON(trap, label, hdlr) \
360 .globl label##_common; \
362 EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \
365 addi r3,r1,STACK_FRAME_OVERHEAD; \
369 #define STD_EXCEPTION_COMMON_LITE(trap, label, hdlr) \
371 .globl label##_common; \
373 EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \
375 addi r3,r1,STACK_FRAME_OVERHEAD; \
377 b .ret_from_except_lite
380 * Start of pSeries system interrupt routines
383 .globl __start_interrupts
386 STD_EXCEPTION_PSERIES(0x100, system_reset)
389 _machine_check_pSeries:
391 mtspr SPRN_SPRG1,r13 /* save r13 */
393 EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common)
396 .globl data_access_pSeries
405 rlwimi r13,r12,16,0x20
408 beq .do_stab_bolted_pSeries
411 END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
412 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, data_access_common)
415 .globl data_access_slb_pSeries
416 data_access_slb_pSeries:
420 mfspr r13,SPRN_SPRG3 /* get paca address into r13 */
421 std r3,PACA_EXSLB+EX_R3(r13)
423 std r9,PACA_EXSLB+EX_R9(r13) /* save r9 - r12 */
426 /* Keep that around for when we re-implement dynamic VSIDs */
428 bge slb_miss_user_pseries
429 #endif /* __DISABLED__ */
430 std r10,PACA_EXSLB+EX_R10(r13)
431 std r11,PACA_EXSLB+EX_R11(r13)
432 std r12,PACA_EXSLB+EX_R12(r13)
434 std r10,PACA_EXSLB+EX_R13(r13)
435 mfspr r12,SPRN_SRR1 /* and SRR1 */
436 b .slb_miss_realmode /* Rel. branch works in real mode */
438 STD_EXCEPTION_PSERIES(0x400, instruction_access)
441 .globl instruction_access_slb_pSeries
442 instruction_access_slb_pSeries:
446 mfspr r13,SPRN_SPRG3 /* get paca address into r13 */
447 std r3,PACA_EXSLB+EX_R3(r13)
448 mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */
449 std r9,PACA_EXSLB+EX_R9(r13) /* save r9 - r12 */
452 /* Keep that around for when we re-implement dynamic VSIDs */
454 bge slb_miss_user_pseries
455 #endif /* __DISABLED__ */
456 std r10,PACA_EXSLB+EX_R10(r13)
457 std r11,PACA_EXSLB+EX_R11(r13)
458 std r12,PACA_EXSLB+EX_R12(r13)
460 std r10,PACA_EXSLB+EX_R13(r13)
461 mfspr r12,SPRN_SRR1 /* and SRR1 */
462 b .slb_miss_realmode /* Rel. branch works in real mode */
464 STD_EXCEPTION_PSERIES(0x500, hardware_interrupt)
465 STD_EXCEPTION_PSERIES(0x600, alignment)
466 STD_EXCEPTION_PSERIES(0x700, program_check)
467 STD_EXCEPTION_PSERIES(0x800, fp_unavailable)
468 STD_EXCEPTION_PSERIES(0x900, decrementer)
469 STD_EXCEPTION_PSERIES(0xa00, trap_0a)
470 STD_EXCEPTION_PSERIES(0xb00, trap_0b)
473 .globl system_call_pSeries
482 oris r12,r12,system_call_common@h
483 ori r12,r12,system_call_common@l
485 ori r10,r10,MSR_IR|MSR_DR|MSR_RI
489 b . /* prevent speculative execution */
491 STD_EXCEPTION_PSERIES(0xd00, single_step)
492 STD_EXCEPTION_PSERIES(0xe00, trap_0e)
494 /* We need to deal with the Altivec unavailable exception
495 * here which is at 0xf20, thus in the middle of the
496 * prolog code of the PerformanceMonitor one. A little
497 * trickery is thus necessary
500 b performance_monitor_pSeries
502 STD_EXCEPTION_PSERIES(0xf20, altivec_unavailable)
504 STD_EXCEPTION_PSERIES(0x1300, instruction_breakpoint)
505 STD_EXCEPTION_PSERIES(0x1700, altivec_assist)
509 /*** pSeries interrupt support ***/
511 /* moved from 0xf00 */
512 STD_EXCEPTION_PSERIES(., performance_monitor)
515 _GLOBAL(do_stab_bolted_pSeries)
518 EXCEPTION_PROLOG_PSERIES(PACA_EXSLB, .do_stab_bolted)
521 * We have some room here we use that to put
522 * the peries slb miss user trampoline code so it's reasonably
523 * away from slb_miss_user_common to avoid problems with rfid
525 * This is used for when the SLB miss handler has to go virtual,
526 * which doesn't happen for now anymore but will once we re-implement
527 * dynamic VSIDs for shared page tables
530 slb_miss_user_pseries:
531 std r10,PACA_EXGEN+EX_R10(r13)
532 std r11,PACA_EXGEN+EX_R11(r13)
533 std r12,PACA_EXGEN+EX_R12(r13)
535 ld r11,PACA_EXSLB+EX_R9(r13)
536 ld r12,PACA_EXSLB+EX_R3(r13)
537 std r10,PACA_EXGEN+EX_R13(r13)
538 std r11,PACA_EXGEN+EX_R9(r13)
539 std r12,PACA_EXGEN+EX_R3(r13)
542 mfspr r11,SRR0 /* save SRR0 */
543 ori r12,r12,slb_miss_user_common@l /* virt addr of handler */
544 ori r10,r10,MSR_IR|MSR_DR|MSR_RI
546 mfspr r12,SRR1 /* and SRR1 */
549 b . /* prevent spec. execution */
550 #endif /* __DISABLED__ */
553 * Vectors for the FWNMI option. Share common code.
555 .globl system_reset_fwnmi
559 mtspr SPRN_SPRG1,r13 /* save r13 */
561 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, system_reset_common)
563 .globl machine_check_fwnmi
567 mtspr SPRN_SPRG1,r13 /* save r13 */
569 EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common)
571 #ifdef CONFIG_PPC_ISERIES
572 /*** ISeries-LPAR interrupt handlers ***/
574 STD_EXCEPTION_ISERIES(0x200, machine_check, PACA_EXMC)
576 .globl data_access_iSeries
584 rlwimi r13,r12,16,0x20
587 beq .do_stab_bolted_iSeries
590 END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
591 EXCEPTION_PROLOG_ISERIES_1(PACA_EXGEN)
592 EXCEPTION_PROLOG_ISERIES_2
595 .do_stab_bolted_iSeries:
598 EXCEPTION_PROLOG_ISERIES_1(PACA_EXSLB)
599 EXCEPTION_PROLOG_ISERIES_2
602 .globl data_access_slb_iSeries
603 data_access_slb_iSeries:
604 mtspr SPRN_SPRG1,r13 /* save r13 */
605 mfspr r13,SPRN_SPRG3 /* get paca address into r13 */
606 std r3,PACA_EXSLB+EX_R3(r13)
608 std r9,PACA_EXSLB+EX_R9(r13)
612 bge slb_miss_user_iseries
614 std r10,PACA_EXSLB+EX_R10(r13)
615 std r11,PACA_EXSLB+EX_R11(r13)
616 std r12,PACA_EXSLB+EX_R12(r13)
618 std r10,PACA_EXSLB+EX_R13(r13)
619 ld r12,PACALPPACA+LPPACASRR1(r13);
622 STD_EXCEPTION_ISERIES(0x400, instruction_access, PACA_EXGEN)
624 .globl instruction_access_slb_iSeries
625 instruction_access_slb_iSeries:
626 mtspr SPRN_SPRG1,r13 /* save r13 */
627 mfspr r13,SPRN_SPRG3 /* get paca address into r13 */
628 std r3,PACA_EXSLB+EX_R3(r13)
629 ld r3,PACALPPACA+LPPACASRR0(r13) /* get SRR0 value */
630 std r9,PACA_EXSLB+EX_R9(r13)
634 bge .slb_miss_user_iseries
636 std r10,PACA_EXSLB+EX_R10(r13)
637 std r11,PACA_EXSLB+EX_R11(r13)
638 std r12,PACA_EXSLB+EX_R12(r13)
640 std r10,PACA_EXSLB+EX_R13(r13)
641 ld r12,PACALPPACA+LPPACASRR1(r13);
645 slb_miss_user_iseries:
646 std r10,PACA_EXGEN+EX_R10(r13)
647 std r11,PACA_EXGEN+EX_R11(r13)
648 std r12,PACA_EXGEN+EX_R12(r13)
650 ld r11,PACA_EXSLB+EX_R9(r13)
651 ld r12,PACA_EXSLB+EX_R3(r13)
652 std r10,PACA_EXGEN+EX_R13(r13)
653 std r11,PACA_EXGEN+EX_R9(r13)
654 std r12,PACA_EXGEN+EX_R3(r13)
655 EXCEPTION_PROLOG_ISERIES_2
656 b slb_miss_user_common
659 MASKABLE_EXCEPTION_ISERIES(0x500, hardware_interrupt)
660 STD_EXCEPTION_ISERIES(0x600, alignment, PACA_EXGEN)
661 STD_EXCEPTION_ISERIES(0x700, program_check, PACA_EXGEN)
662 STD_EXCEPTION_ISERIES(0x800, fp_unavailable, PACA_EXGEN)
663 MASKABLE_EXCEPTION_ISERIES(0x900, decrementer)
664 STD_EXCEPTION_ISERIES(0xa00, trap_0a, PACA_EXGEN)
665 STD_EXCEPTION_ISERIES(0xb00, trap_0b, PACA_EXGEN)
667 .globl system_call_iSeries
671 EXCEPTION_PROLOG_ISERIES_2
674 STD_EXCEPTION_ISERIES( 0xd00, single_step, PACA_EXGEN)
675 STD_EXCEPTION_ISERIES( 0xe00, trap_0e, PACA_EXGEN)
676 STD_EXCEPTION_ISERIES( 0xf00, performance_monitor, PACA_EXGEN)
678 .globl system_reset_iSeries
679 system_reset_iSeries:
680 mfspr r13,SPRN_SPRG3 /* Get paca address */
683 mtmsrd r24 /* RI on */
684 lhz r24,PACAPACAINDEX(r13) /* Get processor # */
685 cmpwi 0,r24,0 /* Are we processor 0? */
686 beq .__start_initialization_iSeries /* Start up the first processor */
688 li r5,CTRL_RUNLATCH /* Turn off the run light */
695 lbz r23,PACAPROCSTART(r13) /* Test if this processor
698 LOADADDR(r3,current_set)
699 sldi r28,r24,3 /* get current_set[cpu#] */
701 addi r1,r3,THREAD_SIZE
702 subi r1,r1,STACK_FRAME_OVERHEAD
705 beq iSeries_secondary_smp_loop /* Loop until told to go */
706 bne .__secondary_start /* Loop until told to go */
707 iSeries_secondary_smp_loop:
708 /* Let the Hypervisor know we are alive */
709 /* 8002 is a call to HvCallCfg::getLps, a harmless Hypervisor function */
711 rldicr r3,r3,32,15 /* r0 = (r3 << 32) & 0xffff000000000000 */
712 #else /* CONFIG_SMP */
713 /* Yield the processor. This is required for non-SMP kernels
714 which are running on multi-threaded machines. */
716 rldicr r3,r3,32,15 /* r3 = (r3 << 32) & 0xffff000000000000 */
717 addi r3,r3,18 /* r3 = 0x8000000000000012 which is "yield" */
718 li r4,0 /* "yield timed" */
719 li r5,-1 /* "yield forever" */
720 #endif /* CONFIG_SMP */
721 li r0,-1 /* r0=-1 indicates a Hypervisor call */
722 sc /* Invoke the hypervisor via a system call */
723 mfspr r13,SPRN_SPRG3 /* Put r13 back ???? */
724 b 1b /* If SMP not configured, secondaries
727 .globl decrementer_iSeries_masked
728 decrementer_iSeries_masked:
730 stb r11,PACALPPACA+LPPACADECRINT(r13)
731 LOADBASE(r12,tb_ticks_per_jiffy)
732 lwz r12,OFF(tb_ticks_per_jiffy)(r12)
736 .globl hardware_interrupt_iSeries_masked
737 hardware_interrupt_iSeries_masked:
738 mtcrf 0x80,r9 /* Restore regs */
739 ld r11,PACALPPACA+LPPACASRR0(r13)
740 ld r12,PACALPPACA+LPPACASRR1(r13)
743 ld r9,PACA_EXGEN+EX_R9(r13)
744 ld r10,PACA_EXGEN+EX_R10(r13)
745 ld r11,PACA_EXGEN+EX_R11(r13)
746 ld r12,PACA_EXGEN+EX_R12(r13)
747 ld r13,PACA_EXGEN+EX_R13(r13)
749 b . /* prevent speculative execution */
750 #endif /* CONFIG_PPC_ISERIES */
752 /*** Common interrupt handlers ***/
754 STD_EXCEPTION_COMMON(0x100, system_reset, .system_reset_exception)
757 * Machine check is different because we use a different
758 * save area: PACA_EXMC instead of PACA_EXGEN.
761 .globl machine_check_common
762 machine_check_common:
763 EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC)
766 addi r3,r1,STACK_FRAME_OVERHEAD
767 bl .machine_check_exception
770 STD_EXCEPTION_COMMON_LITE(0x900, decrementer, .timer_interrupt)
771 STD_EXCEPTION_COMMON(0xa00, trap_0a, .unknown_exception)
772 STD_EXCEPTION_COMMON(0xb00, trap_0b, .unknown_exception)
773 STD_EXCEPTION_COMMON(0xd00, single_step, .single_step_exception)
774 STD_EXCEPTION_COMMON(0xe00, trap_0e, .unknown_exception)
775 STD_EXCEPTION_COMMON(0xf00, performance_monitor, .performance_monitor_exception)
776 STD_EXCEPTION_COMMON(0x1300, instruction_breakpoint, .instruction_breakpoint_exception)
777 #ifdef CONFIG_ALTIVEC
778 STD_EXCEPTION_COMMON(0x1700, altivec_assist, .altivec_assist_exception)
780 STD_EXCEPTION_COMMON(0x1700, altivec_assist, .unknown_exception)
784 * Here we have detected that the kernel stack pointer is bad.
785 * R9 contains the saved CR, r13 points to the paca,
786 * r10 contains the (bad) kernel stack pointer,
787 * r11 and r12 contain the saved SRR0 and SRR1.
788 * We switch to using an emergency stack, save the registers there,
789 * and call kernel_bad_stack(), which panics.
792 ld r1,PACAEMERGSP(r13)
793 subi r1,r1,64+INT_FRAME_SIZE
814 addi r11,r1,INT_FRAME_SIZE
819 1: addi r3,r1,STACK_FRAME_OVERHEAD
824 * Return from an exception with minimal checks.
825 * The caller is assumed to have done EXCEPTION_PROLOG_COMMON.
826 * If interrupts have been enabled, or anything has been
827 * done that might have changed the scheduling status of
828 * any task or sent any task a signal, you should use
829 * ret_from_except or ret_from_except_lite instead of this.
831 .globl fast_exception_return
832 fast_exception_return:
835 andi. r3,r12,MSR_RI /* check if RI is set */
849 clrrdi r10,r10,2 /* clear RI (LE is 0 already) */
857 b . /* prevent speculative execution */
861 1: addi r3,r1,STACK_FRAME_OVERHEAD
862 bl .unrecoverable_exception
866 * Here r13 points to the paca, r9 contains the saved CR,
867 * SRR0 and SRR1 are saved in r11 and r12,
868 * r9 - r13 are saved in paca->exgen.
871 .globl data_access_common
873 RUNLATCH_ON(r10) /* It wont fit in the 0x300 handler */
875 std r10,PACA_EXGEN+EX_DAR(r13)
877 stw r10,PACA_EXGEN+EX_DSISR(r13)
878 EXCEPTION_PROLOG_COMMON(0x300, PACA_EXGEN)
879 ld r3,PACA_EXGEN+EX_DAR(r13)
880 lwz r4,PACA_EXGEN+EX_DSISR(r13)
882 b .do_hash_page /* Try to handle as hpte fault */
885 .globl instruction_access_common
886 instruction_access_common:
887 EXCEPTION_PROLOG_COMMON(0x400, PACA_EXGEN)
891 b .do_hash_page /* Try to handle as hpte fault */
894 * Here is the common SLB miss user that is used when going to virtual
895 * mode for SLB misses, that is currently not used
899 .globl slb_miss_user_common
900 slb_miss_user_common:
902 std r3,PACA_EXGEN+EX_DAR(r13)
903 stw r9,PACA_EXGEN+EX_CCR(r13)
904 std r10,PACA_EXGEN+EX_LR(r13)
905 std r11,PACA_EXGEN+EX_SRR0(r13)
906 bl .slb_allocate_user
908 ld r10,PACA_EXGEN+EX_LR(r13)
909 ld r3,PACA_EXGEN+EX_R3(r13)
910 lwz r9,PACA_EXGEN+EX_CCR(r13)
911 ld r11,PACA_EXGEN+EX_SRR0(r13)
915 andi. r10,r12,MSR_RI /* check for unrecoverable exception */
916 beq- unrecov_user_slb
924 clrrdi r10,r10,2 /* clear RI before setting SRR0/1 */
930 ld r9,PACA_EXGEN+EX_R9(r13)
931 ld r10,PACA_EXGEN+EX_R10(r13)
932 ld r11,PACA_EXGEN+EX_R11(r13)
933 ld r12,PACA_EXGEN+EX_R12(r13)
934 ld r13,PACA_EXGEN+EX_R13(r13)
939 EXCEPTION_PROLOG_COMMON(0x380, PACA_EXGEN)
940 ld r4,PACA_EXGEN+EX_DAR(r13)
947 EXCEPTION_PROLOG_COMMON(0x4200, PACA_EXGEN)
950 1: addi r3,r1,STACK_FRAME_OVERHEAD
951 bl .unrecoverable_exception
954 #endif /* __DISABLED__ */
958 * r13 points to the PACA, r9 contains the saved CR,
959 * r12 contain the saved SRR1, SRR0 is still ready for return
960 * r3 has the faulting address
961 * r9 - r13 are saved in paca->exslb.
962 * r3 is saved in paca->slb_r3
963 * We assume we aren't going to take any exceptions during this procedure.
965 _GLOBAL(slb_miss_realmode)
968 stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */
969 std r10,PACA_EXSLB+EX_LR(r13) /* save LR */
971 bl .slb_allocate_realmode
973 /* All done -- return from exception. */
975 ld r10,PACA_EXSLB+EX_LR(r13)
976 ld r3,PACA_EXSLB+EX_R3(r13)
977 lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */
978 #ifdef CONFIG_PPC_ISERIES
979 ld r11,PACALPPACA+LPPACASRR0(r13) /* get SRR0 value */
980 #endif /* CONFIG_PPC_ISERIES */
984 andi. r10,r12,MSR_RI /* check for unrecoverable exception */
990 mtcrf 0x01,r9 /* slb_allocate uses cr0 and cr7 */
993 #ifdef CONFIG_PPC_ISERIES
996 #endif /* CONFIG_PPC_ISERIES */
997 ld r9,PACA_EXSLB+EX_R9(r13)
998 ld r10,PACA_EXSLB+EX_R10(r13)
999 ld r11,PACA_EXSLB+EX_R11(r13)
1000 ld r12,PACA_EXSLB+EX_R12(r13)
1001 ld r13,PACA_EXSLB+EX_R13(r13)
1003 b . /* prevent speculative execution */
1006 EXCEPTION_PROLOG_COMMON(0x4100, PACA_EXSLB)
1009 1: addi r3,r1,STACK_FRAME_OVERHEAD
1010 bl .unrecoverable_exception
1014 .globl hardware_interrupt_common
1015 .globl hardware_interrupt_entry
1016 hardware_interrupt_common:
1017 EXCEPTION_PROLOG_COMMON(0x500, PACA_EXGEN)
1018 hardware_interrupt_entry:
1020 addi r3,r1,STACK_FRAME_OVERHEAD
1022 b .ret_from_except_lite
1025 .globl alignment_common
1028 std r10,PACA_EXGEN+EX_DAR(r13)
1029 mfspr r10,SPRN_DSISR
1030 stw r10,PACA_EXGEN+EX_DSISR(r13)
1031 EXCEPTION_PROLOG_COMMON(0x600, PACA_EXGEN)
1032 ld r3,PACA_EXGEN+EX_DAR(r13)
1033 lwz r4,PACA_EXGEN+EX_DSISR(r13)
1037 addi r3,r1,STACK_FRAME_OVERHEAD
1039 bl .alignment_exception
1043 .globl program_check_common
1044 program_check_common:
1045 EXCEPTION_PROLOG_COMMON(0x700, PACA_EXGEN)
1047 addi r3,r1,STACK_FRAME_OVERHEAD
1049 bl .program_check_exception
1053 .globl fp_unavailable_common
1054 fp_unavailable_common:
1055 EXCEPTION_PROLOG_COMMON(0x800, PACA_EXGEN)
1056 bne .load_up_fpu /* if from user, just load it up */
1058 addi r3,r1,STACK_FRAME_OVERHEAD
1060 bl .kernel_fp_unavailable_exception
1064 .globl altivec_unavailable_common
1065 altivec_unavailable_common:
1066 EXCEPTION_PROLOG_COMMON(0xf20, PACA_EXGEN)
1067 #ifdef CONFIG_ALTIVEC
1069 bne .load_up_altivec /* if from user, just load it up */
1070 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
1073 addi r3,r1,STACK_FRAME_OVERHEAD
1075 bl .altivec_unavailable_exception
1078 #ifdef CONFIG_ALTIVEC
1080 * load_up_altivec(unused, unused, tsk)
1081 * Disable VMX for the task which had it previously,
1082 * and save its vector registers in its thread_struct.
1083 * Enables the VMX for use in the kernel on return.
1084 * On SMP we know the VMX is free, since we give it up every
1085 * switch (ie, no lazy save of the vector registers).
1086 * On entry: r13 == 'current' && last_task_used_altivec != 'current'
1088 _STATIC(load_up_altivec)
1089 mfmsr r5 /* grab the current MSR */
1090 oris r5,r5,MSR_VEC@h
1091 mtmsrd r5 /* enable use of VMX now */
1095 * For SMP, we don't do lazy VMX switching because it just gets too
1096 * horrendously complex, especially when a task switches from one CPU
1097 * to another. Instead we call giveup_altvec in switch_to.
1098 * VRSAVE isn't dealt with here, that is done in the normal context
1099 * switch code. Note that we could rely on vrsave value to eventually
1100 * avoid saving all of the VREGs here...
1103 ld r3,last_task_used_altivec@got(r2)
1107 /* Save VMX state to last_task_used_altivec's THREAD struct */
1113 /* Disable VMX for last_task_used_altivec */
1115 ld r4,_MSR-STACK_FRAME_OVERHEAD(r5)
1118 std r4,_MSR-STACK_FRAME_OVERHEAD(r5)
1120 #endif /* CONFIG_SMP */
1121 /* Hack: if we get an altivec unavailable trap with VRSAVE
1122 * set to all zeros, we assume this is a broken application
1123 * that fails to set it properly, and thus we switch it to
1126 mfspr r4,SPRN_VRSAVE
1130 mtspr SPRN_VRSAVE,r4
1132 /* enable use of VMX after return */
1133 ld r4,PACACURRENT(r13)
1134 addi r5,r4,THREAD /* Get THREAD */
1135 oris r12,r12,MSR_VEC@h
1139 stw r4,THREAD_USED_VR(r5)
1144 /* Update last_task_used_math to 'current' */
1145 subi r4,r5,THREAD /* Back to 'current' */
1147 #endif /* CONFIG_SMP */
1148 /* restore registers and return */
1149 b fast_exception_return
1150 #endif /* CONFIG_ALTIVEC */
1156 _GLOBAL(do_hash_page)
1160 andis. r0,r4,0xa450 /* weird error? */
1161 bne- .handle_page_fault /* if not, try to insert a HPTE */
1163 andis. r0,r4,0x0020 /* Is it a segment table fault? */
1164 bne- .do_ste_alloc /* If so handle it */
1165 END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
1168 * We need to set the _PAGE_USER bit if MSR_PR is set or if we are
1169 * accessing a userspace segment (even from the kernel). We assume
1170 * kernel addresses always have the high bit set.
1172 rlwinm r4,r4,32-25+9,31-9,31-9 /* DSISR_STORE -> _PAGE_RW */
1173 rotldi r0,r3,15 /* Move high bit into MSR_PR posn */
1174 orc r0,r12,r0 /* MSR_PR | ~high_bit */
1175 rlwimi r4,r0,32-13,30,30 /* becomes _PAGE_USER access bit */
1176 ori r4,r4,1 /* add _PAGE_PRESENT */
1177 rlwimi r4,r5,22+2,31-2,31-2 /* Set _PAGE_EXEC if trap is 0x400 */
1180 * On iSeries, we soft-disable interrupts here, then
1181 * hard-enable interrupts so that the hash_page code can spin on
1182 * the hash_table_lock without problems on a shared processor.
1187 * r3 contains the faulting address
1188 * r4 contains the required access permissions
1189 * r5 contains the trap number
1191 * at return r3 = 0 for success
1193 bl .hash_page /* build HPTE if possible */
1194 cmpdi r3,0 /* see if hash_page succeeded */
1196 #ifdef DO_SOFT_DISABLE
1198 * If we had interrupts soft-enabled at the point where the
1199 * DSI/ISI occurred, and an interrupt came in during hash_page,
1201 * We jump to ret_from_except_lite rather than fast_exception_return
1202 * because ret_from_except_lite will check for and handle pending
1203 * interrupts if necessary.
1205 beq .ret_from_except_lite
1206 /* For a hash failure, we don't bother re-enabling interrupts */
1210 * hash_page couldn't handle it, set soft interrupt enable back
1211 * to what it was before the trap. Note that .local_irq_restore
1212 * handles any interrupts pending at this point.
1215 bl .local_irq_restore
1218 beq fast_exception_return /* Return from exception on success */
1219 ble- 12f /* Failure return from hash_page */
1224 /* Here we have a page fault that hash_page can't handle. */
1225 _GLOBAL(handle_page_fault)
1229 addi r3,r1,STACK_FRAME_OVERHEAD
1232 beq+ .ret_from_except_lite
1235 addi r3,r1,STACK_FRAME_OVERHEAD
1240 /* We have a page fault that hash_page could handle but HV refused
1244 addi r3,r1,STACK_FRAME_OVERHEAD
1249 /* here we have a segment miss */
1250 _GLOBAL(do_ste_alloc)
1251 bl .ste_allocate /* try to insert stab entry */
1253 beq+ fast_exception_return
1254 b .handle_page_fault
1257 * r13 points to the PACA, r9 contains the saved CR,
1258 * r11 and r12 contain the saved SRR0 and SRR1.
1259 * r9 - r13 are saved in paca->exslb.
1260 * We assume we aren't going to take any exceptions during this procedure.
1261 * We assume (DAR >> 60) == 0xc.
1264 _GLOBAL(do_stab_bolted)
1265 stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */
1266 std r11,PACA_EXSLB+EX_SRR0(r13) /* save SRR0 in exc. frame */
1268 /* Hash to the primary group */
1269 ld r10,PACASTABVIRT(r13)
1272 rldimi r10,r11,7,52 /* r10 = first ste of the group */
1274 /* Calculate VSID */
1275 /* This is a kernel address, so protovsid = ESID */
1276 ASM_VSID_SCRAMBLE(r11, r9)
1277 rldic r9,r11,12,16 /* r9 = vsid << 12 */
1279 /* Search the primary group for a free entry */
1280 1: ld r11,0(r10) /* Test valid bit of the current ste */
1287 /* Stick for only searching the primary group for now. */
1288 /* At least for now, we use a very simple random castout scheme */
1289 /* Use the TB as a random number ; OR in 1 to avoid entry 0 */
1291 rldic r11,r11,4,57 /* r11 = (r11 << 4) & 0x70 */
1294 /* r10 currently points to an ste one past the group of interest */
1295 /* make it point to the randomly selected entry */
1297 or r10,r10,r11 /* r10 is the entry to invalidate */
1299 isync /* mark the entry invalid */
1301 rldicl r11,r11,56,1 /* clear the valid bit */
1306 clrrdi r11,r11,28 /* Get the esid part of the ste */
1309 2: std r9,8(r10) /* Store the vsid part of the ste */
1312 mfspr r11,SPRN_DAR /* Get the new esid */
1313 clrrdi r11,r11,28 /* Permits a full 32b of ESID */
1314 ori r11,r11,0x90 /* Turn on valid and kp */
1315 std r11,0(r10) /* Put new entry back into the stab */
1319 /* All done -- return from exception. */
1320 lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */
1321 ld r11,PACA_EXSLB+EX_SRR0(r13) /* get saved SRR0 */
1323 andi. r10,r12,MSR_RI
1326 mtcrf 0x80,r9 /* restore CR */
1334 ld r9,PACA_EXSLB+EX_R9(r13)
1335 ld r10,PACA_EXSLB+EX_R10(r13)
1336 ld r11,PACA_EXSLB+EX_R11(r13)
1337 ld r12,PACA_EXSLB+EX_R12(r13)
1338 ld r13,PACA_EXSLB+EX_R13(r13)
1340 b . /* prevent speculative execution */
1343 * Space for CPU0's segment table.
1345 * On iSeries, the hypervisor must fill in at least one entry before
1346 * we get control (with relocate on). The address is give to the hv
1347 * as a page number (see xLparMap in lpardata.c), so this must be at a
1348 * fixed address (the linker can't compute (u64)&initial_stab >>
1351 . = STAB0_PHYS_ADDR /* 0x6000 */
1357 * Data area reserved for FWNMI option.
1358 * This address (0x7000) is fixed by the RPA.
1361 .globl fwnmi_data_area
1364 /* iSeries does not use the FWNMI stuff, so it is safe to put
1365 * this here, even if we later allow kernels that will boot on
1366 * both pSeries and iSeries */
1367 #ifdef CONFIG_PPC_ISERIES
1369 #include "lparmap.s"
1371 * This ".text" is here for old compilers that generate a trailing
1372 * .note section when compiling .c files to .s
1375 #endif /* CONFIG_PPC_ISERIES */
1380 * On pSeries, secondary processors spin in the following code.
1381 * At entry, r3 = this processor's number (physical cpu id)
1383 _GLOBAL(pSeries_secondary_smp_init)
1386 /* turn on 64-bit mode */
1390 /* Copy some CPU settings from CPU 0 */
1391 bl .__restore_cpu_setup
1393 /* Set up a paca value for this processor. Since we have the
1394 * physical cpu id in r24, we need to search the pacas to find
1395 * which logical id maps to our physical one.
1397 LOADADDR(r13, paca) /* Get base vaddr of paca array */
1398 li r5,0 /* logical cpu id */
1399 1: lhz r6,PACAHWCPUID(r13) /* Load HW procid from paca */
1400 cmpw r6,r24 /* Compare to our id */
1402 addi r13,r13,PACA_SIZE /* Loop to next PACA on miss */
1407 mr r3,r24 /* not found, copy phys to r3 */
1408 b .kexec_wait /* next kernel might do better */
1410 2: mtspr SPRN_SPRG3,r13 /* Save vaddr of paca in SPRG3 */
1411 /* From now on, r24 is expected to be logical cpuid */
1414 lbz r23,PACAPROCSTART(r13) /* Test if this processor should */
1418 /* Create a temp kernel stack for use before relocation is on. */
1419 ld r1,PACAEMERGSP(r13)
1420 subi r1,r1,STACK_FRAME_OVERHEAD
1424 bne .__secondary_start
1426 b 3b /* Loop until told to go */
1428 #ifdef CONFIG_PPC_ISERIES
1429 _STATIC(__start_initialization_iSeries)
1430 /* Clear out the BSS */
1431 LOADADDR(r11,__bss_stop)
1432 LOADADDR(r8,__bss_start)
1433 sub r11,r11,r8 /* bss size */
1434 addi r11,r11,7 /* round up to an even double word */
1435 rldicl. r11,r11,61,3 /* shift right by 3 */
1439 mtctr r11 /* zero this many doublewords */
1443 LOADADDR(r1,init_thread_union)
1444 addi r1,r1,THREAD_SIZE
1446 stdu r0,-STACK_FRAME_OVERHEAD(r1)
1448 LOADADDR(r3,cpu_specs)
1449 LOADADDR(r4,cur_cpu_spec)
1453 LOADADDR(r2,__toc_start)
1457 bl .iSeries_early_setup
1460 /* relocation is on at this point */
1462 b .start_here_common
1463 #endif /* CONFIG_PPC_ISERIES */
1465 #ifdef CONFIG_PPC_MULTIPLATFORM
1469 andi. r0,r3,MSR_IR|MSR_DR
1476 b . /* prevent speculative execution */
1480 * Here is our main kernel entry point. We support currently 2 kind of entries
1481 * depending on the value of r5.
1483 * r5 != NULL -> OF entry, we go to prom_init, "legacy" parameter content
1486 * r5 == NULL -> kexec style entry. r3 is a physical pointer to the
1487 * DT block, r4 is a physical pointer to the kernel itself
1490 _GLOBAL(__start_initialization_multiplatform)
1492 * Are we booted from a PROM Of-type client-interface ?
1495 bne .__boot_from_prom /* yes -> prom */
1497 /* Save parameters */
1501 /* Make sure we are running in 64 bits mode */
1504 /* Setup some critical 970 SPRs before switching MMU off */
1505 bl .__970_cpu_preinit
1510 /* Switch off MMU if not already */
1511 LOADADDR(r4, .__after_prom_start - KERNELBASE)
1514 b .__after_prom_start
1516 _STATIC(__boot_from_prom)
1517 /* Save parameters */
1524 /* Make sure we are running in 64 bits mode */
1527 /* put a relocation offset into r3 */
1530 LOADADDR(r2,__toc_start)
1534 /* Relocate the TOC from a virt addr to a real addr */
1537 /* Restore parameters */
1544 /* Do all of the interaction with OF client interface */
1546 /* We never return */
1550 * At this point, r3 contains the physical address we are running at,
1551 * returned by prom_init()
1553 _STATIC(__after_prom_start)
1556 * We need to run with __start at physical address 0.
1557 * This will leave some code in the first 256B of
1558 * real memory, which are reserved for software use.
1559 * The remainder of the first page is loaded with the fixed
1560 * interrupt vectors. The next two pages are filled with
1561 * unknown exception placeholders.
1563 * Note: This process overwrites the OF exception vectors.
1564 * r26 == relocation offset
1569 SET_REG_TO_CONST(r27,KERNELBASE)
1571 li r3,0 /* target addr */
1573 // XXX FIXME: Use phys returned by OF (r30)
1574 add r4,r27,r26 /* source addr */
1575 /* current address of _start */
1576 /* i.e. where we are running */
1577 /* the source addr */
1579 LOADADDR(r5,copy_to_here) /* # bytes of memory to copy */
1582 li r6,0x100 /* Start offset, the first 0x100 */
1583 /* bytes were copied earlier. */
1585 bl .copy_and_flush /* copy the first n bytes */
1586 /* this includes the code being */
1587 /* executed here. */
1589 LOADADDR(r0, 4f) /* Jump to the copy of this code */
1590 mtctr r0 /* that we just made/relocated */
1593 4: LOADADDR(r5,klimit)
1595 ld r5,0(r5) /* get the value of klimit */
1597 bl .copy_and_flush /* copy the rest */
1598 b .start_here_multiplatform
1600 #endif /* CONFIG_PPC_MULTIPLATFORM */
1603 * Copy routine used to copy the kernel to start at physical address 0
1604 * and flush and invalidate the caches as needed.
1605 * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset
1606 * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5.
1608 * Note: this routine *only* clobbers r0, r6 and lr
1610 _GLOBAL(copy_and_flush)
1613 4: li r0,16 /* Use the least common */
1614 /* denominator cache line */
1615 /* size. This results in */
1616 /* extra cache line flushes */
1617 /* but operation is correct. */
1618 /* Can't get cache line size */
1619 /* from NACA as it is being */
1622 mtctr r0 /* put # words/line in ctr */
1623 3: addi r6,r6,8 /* copy a cache line */
1627 dcbst r6,r3 /* write it to memory */
1629 icbi r6,r3 /* flush the icache line */
1641 #ifdef CONFIG_PPC_PMAC
1643 * On PowerMac, secondary processors starts from the reset vector, which
1644 * is temporarily turned into a call to one of the functions below.
1649 .globl __secondary_start_pmac_0
1650 __secondary_start_pmac_0:
1651 /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */
1661 _GLOBAL(pmac_secondary_start)
1662 /* turn on 64-bit mode */
1666 /* Copy some CPU settings from CPU 0 */
1667 bl .__restore_cpu_setup
1669 /* pSeries do that early though I don't think we really need it */
1672 mtmsrd r3 /* RI on */
1674 /* Set up a paca value for this processor. */
1675 LOADADDR(r4, paca) /* Get base vaddr of paca array */
1676 mulli r13,r24,PACA_SIZE /* Calculate vaddr of right paca */
1677 add r13,r13,r4 /* for this processor. */
1678 mtspr SPRN_SPRG3,r13 /* Save vaddr of paca in SPRG3 */
1680 /* Create a temp kernel stack for use before relocation is on. */
1681 ld r1,PACAEMERGSP(r13)
1682 subi r1,r1,STACK_FRAME_OVERHEAD
1684 b .__secondary_start
1686 #endif /* CONFIG_PPC_PMAC */
1689 * This function is called after the master CPU has released the
1690 * secondary processors. The execution environment is relocation off.
1691 * The paca for this processor has the following fields initialized at
1693 * 1. Processor number
1694 * 2. Segment table pointer (virtual address)
1695 * On entry the following are set:
1696 * r1 = stack pointer. vaddr for iSeries, raddr (temp stack) for pSeries
1697 * r24 = cpu# (in Linux terms)
1698 * r13 = paca virtual address
1699 * SPRG3 = paca virtual address
1701 _GLOBAL(__secondary_start)
1702 /* Set thread priority to MEDIUM */
1708 /* Do early setup for that CPU (stab, slb, hash table pointer) */
1709 bl .early_setup_secondary
1711 /* Initialize the kernel stack. Just a repeat for iSeries. */
1712 LOADADDR(r3,current_set)
1713 sldi r28,r24,3 /* get current_set[cpu#] */
1715 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
1716 std r1,PACAKSAVE(r13)
1718 /* Clear backchain so we get nice backtraces */
1722 /* enable MMU and jump to start_secondary */
1723 LOADADDR(r3,.start_secondary_prolog)
1724 SET_REG_TO_CONST(r4, MSR_KERNEL)
1725 #ifdef DO_SOFT_DISABLE
1731 b . /* prevent speculative execution */
1734 * Running with relocation on at this point. All we want to do is
1735 * zero the stack back-chain pointer before going into C code.
1737 _GLOBAL(start_secondary_prolog)
1739 std r3,0(r1) /* Zero the stack frame pointer */
1745 * This subroutine clobbers r11 and r12
1747 _GLOBAL(enable_64b_mode)
1748 mfmsr r11 /* grab the current MSR */
1750 rldicr r12,r12,MSR_SF_LG,(63-MSR_SF_LG)
1753 rldicr r12,r12,MSR_ISF_LG,(63-MSR_ISF_LG)
1759 #ifdef CONFIG_PPC_MULTIPLATFORM
1761 * This is where the main kernel code starts.
1763 _STATIC(start_here_multiplatform)
1764 /* get a new offset, now that the kernel has moved. */
1768 /* Clear out the BSS. It may have been done in prom_init,
1769 * already but that's irrelevant since prom_init will soon
1770 * be detached from the kernel completely. Besides, we need
1771 * to clear it now for kexec-style entry.
1773 LOADADDR(r11,__bss_stop)
1774 LOADADDR(r8,__bss_start)
1775 sub r11,r11,r8 /* bss size */
1776 addi r11,r11,7 /* round up to an even double word */
1777 rldicl. r11,r11,61,3 /* shift right by 3 */
1781 mtctr r11 /* zero this many doublewords */
1788 mtmsrd r6 /* RI on */
1791 /* Start up the second thread on cpu 0 */
1794 cmpwi r3,0x34 /* Pulsar */
1796 cmpwi r3,0x36 /* Icestar */
1798 cmpwi r3,0x37 /* SStar */
1800 b 91f /* HMT not supported */
1802 bl .hmt_start_secondary
1806 /* The following gets the stack and TOC set up with the regs */
1807 /* pointing to the real addr of the kernel stack. This is */
1808 /* all done to support the C function call below which sets */
1809 /* up the htab. This is done because we have relocated the */
1810 /* kernel but are still running in real mode. */
1812 LOADADDR(r3,init_thread_union)
1815 /* set up a stack pointer (physical address) */
1816 addi r1,r3,THREAD_SIZE
1818 stdu r0,-STACK_FRAME_OVERHEAD(r1)
1820 /* set up the TOC (physical address) */
1821 LOADADDR(r2,__toc_start)
1826 LOADADDR(r3,cpu_specs)
1828 LOADADDR(r4,cur_cpu_spec)
1833 /* Save some low level config HIDs of CPU0 to be copied to
1834 * other CPUs later on, or used for suspend/resume
1836 bl .__save_cpu_setup
1839 /* Setup a valid physical PACA pointer in SPRG3 for early_setup
1840 * note that boot_cpuid can always be 0 nowadays since there is
1841 * nowhere it can be initialized differently before we reach this
1844 LOADADDR(r27, boot_cpuid)
1848 LOADADDR(r24, paca) /* Get base vaddr of paca array */
1849 mulli r13,r27,PACA_SIZE /* Calculate vaddr of right paca */
1850 add r13,r13,r24 /* for this processor. */
1851 add r13,r13,r26 /* convert to physical addr */
1852 mtspr SPRN_SPRG3,r13 /* PPPBBB: Temp... -Peter */
1854 /* Do very early kernel initializations, including initial hash table,
1855 * stab and slb setup before we turn on relocation. */
1857 /* Restore parameters passed from prom_init/kexec */
1861 LOADADDR(r3,.start_here_common)
1862 SET_REG_TO_CONST(r4, MSR_KERNEL)
1866 b . /* prevent speculative execution */
1867 #endif /* CONFIG_PPC_MULTIPLATFORM */
1869 /* This is where all platforms converge execution */
1870 _STATIC(start_here_common)
1871 /* relocation is on at this point */
1873 /* The following code sets up the SP and TOC now that we are */
1874 /* running with translation enabled. */
1876 LOADADDR(r3,init_thread_union)
1878 /* set up the stack */
1879 addi r1,r3,THREAD_SIZE
1881 stdu r0,-STACK_FRAME_OVERHEAD(r1)
1883 /* Apply the CPUs-specific fixups (nop out sections not relevant
1887 bl .do_cpu_ftr_fixups
1889 LOADADDR(r26, boot_cpuid)
1892 LOADADDR(r24, paca) /* Get base vaddr of paca array */
1893 mulli r13,r26,PACA_SIZE /* Calculate vaddr of right paca */
1894 add r13,r13,r24 /* for this processor. */
1895 mtspr SPRN_SPRG3,r13
1897 /* ptr to current */
1898 LOADADDR(r4,init_task)
1899 std r4,PACACURRENT(r13)
1903 std r1,PACAKSAVE(r13)
1907 /* Load up the kernel context */
1909 #ifdef DO_SOFT_DISABLE
1911 stb r5,PACAPROCENABLED(r13) /* Soft Disabled */
1913 ori r5,r5,MSR_EE /* Hard Enabled */
1921 LOADADDR(r5, hmt_thread_data)
1924 cmpwi r7,0x34 /* Pulsar */
1926 cmpwi r7,0x36 /* Icestar */
1928 cmpwi r7,0x37 /* SStar */
1931 90: mfspr r6,SPRN_PIR
1934 91: mfspr r6,SPRN_PIR
1938 bl .hmt_start_secondary
1941 __hmt_secondary_hold:
1942 LOADADDR(r5, hmt_thread_data)
1952 93: andi. r6,r6,0x3f
1966 b .pSeries_secondary_smp_init
1969 _GLOBAL(hmt_start_secondary)
1970 LOADADDR(r4,__hmt_secondary_hold)
1972 mtspr SPRN_NIADORM, r4
1973 mfspr r4, SPRN_MSRDORM
1976 mtspr SPRN_MSRDORM, r4
1985 mfspr r4, SPRN_CTRLF
1987 mtspr SPRN_CTRLT, r4
1992 * We put a few things here that have to be page-aligned.
1993 * This stuff goes at the beginning of the bss, which is page-aligned.
1999 .globl empty_zero_page
2003 .globl swapper_pg_dir
2008 * This space gets a copy of optional info passed to us by the bootstrap
2009 * Used to pass parameters into the kernel like root=/dev/sda1, etc.
2013 .space COMMAND_LINE_SIZE