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[PATCH] i386: Warn upon absolute relocations being present
[usb.git] / include / asm-sh / irq.h
blob6cd3e9e2a76ac62334f28a379e610fc9a0599df4
1 #ifndef __ASM_SH_IRQ_H
2 #define __ASM_SH_IRQ_H
3
4 /*
5 *
6 * linux/include/asm-sh/irq.h
7 *
8 * Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi
9 * Copyright (C) 2000 Kazumoto Kojima
10 * Copyright (C) 2003 Paul Mundt
11 *
12 */
13
14 #include <asm/machvec.h>
15 #include <asm/ptrace.h> /* for pt_regs */
16
17 #ifndef CONFIG_CPU_SUBTYPE_SH7780
18
19 #define INTC_DMAC0_MSK 0
20
21 #if defined(CONFIG_CPU_SH3)
22 #define INTC_IPRA 0xfffffee2UL
23 #define INTC_IPRB 0xfffffee4UL
24 #elif defined(CONFIG_CPU_SH4)
25 #define INTC_IPRA 0xffd00004UL
26 #define INTC_IPRB 0xffd00008UL
27 #define INTC_IPRC 0xffd0000cUL
28 #define INTC_IPRD 0xffd00010UL
29 #endif
30
31 #define TIMER_IRQ 16
32 #define TIMER_IPR_ADDR INTC_IPRA
33 #define TIMER_IPR_POS 3
34 #define TIMER_PRIORITY 2
35
36 #define TIMER1_IRQ 17
37 #define TIMER1_IPR_ADDR INTC_IPRA
38 #define TIMER1_IPR_POS 2
39 #define TIMER1_PRIORITY 4
40
41 #define RTC_IRQ 22
42 #define RTC_IPR_ADDR INTC_IPRA
43 #define RTC_IPR_POS 0
44 #define RTC_PRIORITY TIMER_PRIORITY
45
46 #if defined(CONFIG_CPU_SH3)
47 #define DMTE0_IRQ 48
48 #define DMTE1_IRQ 49
49 #define DMTE2_IRQ 50
50 #define DMTE3_IRQ 51
51 #define DMA_IPR_ADDR INTC_IPRE
52 #define DMA_IPR_POS 3
53 #define DMA_PRIORITY 7
54 #if defined(CONFIG_CPU_SUBTYPE_SH7300)
55 /* TMU2 */
56 #define TIMER2_IRQ 18
57 #define TIMER2_IPR_ADDR INTC_IPRA
58 #define TIMER2_IPR_POS 1
59 #define TIMER2_PRIORITY 2
60
61 /* WDT */
62 #define WDT_IRQ 27
63 #define WDT_IPR_ADDR INTC_IPRB
64 #define WDT_IPR_POS 3
65 #define WDT_PRIORITY 2
66
67 /* SIM (SIM Card Module) */
68 #define SIM_ERI_IRQ 23
69 #define SIM_RXI_IRQ 24
70 #define SIM_TXI_IRQ 25
71 #define SIM_TEND_IRQ 26
72 #define SIM_IPR_ADDR INTC_IPRB
73 #define SIM_IPR_POS 1
74 #define SIM_PRIORITY 2
75
76 /* VIO (Video I/O) */
77 #define VIO_IRQ 52
78 #define VIO_IPR_ADDR INTC_IPRE
79 #define VIO_IPR_POS 2
80 #define VIO_PRIORITY 2
81
82 /* MFI (Multi Functional Interface) */
83 #define MFI_IRQ 56
84 #define MFI_IPR_ADDR INTC_IPRE
85 #define MFI_IPR_POS 1
86 #define MFI_PRIORITY 2
87
88 /* VPU (Video Processing Unit) */
89 #define VPU_IRQ 60
90 #define VPU_IPR_ADDR INTC_IPRE
91 #define VPU_IPR_POS 0
92 #define VPU_PRIORITY 2
93
94 /* KEY (Key Scan Interface) */
95 #define KEY_IRQ 79
96 #define KEY_IPR_ADDR INTC_IPRF
97 #define KEY_IPR_POS 3
98 #define KEY_PRIORITY 2
99
100 /* CMT (Compare Match Timer) */
101 #define CMT_IRQ 104
102 #define CMT_IPR_ADDR INTC_IPRF
103 #define CMT_IPR_POS 0
104 #define CMT_PRIORITY 2
105
106 /* DMAC(1) */
107 #define DMTE0_IRQ 48
108 #define DMTE1_IRQ 49
109 #define DMTE2_IRQ 50
110 #define DMTE3_IRQ 51
111 #define DMA1_IPR_ADDR INTC_IPRE
112 #define DMA1_IPR_POS 3
113 #define DMA1_PRIORITY 7
114
115 /* DMAC(2) */
116 #define DMTE4_IRQ 76
117 #define DMTE5_IRQ 77
118 #define DMA2_IPR_ADDR INTC_IPRF
119 #define DMA2_IPR_POS 2
120 #define DMA2_PRIORITY 7
121
122 /* SIOF0 */
123 #define SIOF0_IRQ 84
124 #define SIOF0_IPR_ADDR INTC_IPRH
125 #define SIOF0_IPR_POS 3
126 #define SIOF0_PRIORITY 3
127
128 /* FLCTL (Flash Memory Controller) */
129 #define FLSTE_IRQ 92
130 #define FLTEND_IRQ 93
131 #define FLTRQ0_IRQ 94
132 #define FLTRQ1_IRQ 95
133 #define FLCTL_IPR_ADDR INTC_IPRH
134 #define FLCTL_IPR_POS 1
135 #define FLCTL_PRIORITY 3
136
137 /* IIC (IIC Bus Interface) */
138 #define IIC_ALI_IRQ 96
139 #define IIC_TACKI_IRQ 97
140 #define IIC_WAITI_IRQ 98
141 #define IIC_DTEI_IRQ 99
142 #define IIC_IPR_ADDR INTC_IPRH
143 #define IIC_IPR_POS 0
144 #define IIC_PRIORITY 3
145
146 /* SIO0 */
147 #define SIO0_IRQ 88
148 #define SIO0_IPR_ADDR INTC_IPRI
149 #define SIO0_IPR_POS 3
150 #define SIO0_PRIORITY 3
151
152 /* SIU (Sound Interface Unit) */
153 #define SIU_IRQ 108
154 #define SIU_IPR_ADDR INTC_IPRJ
155 #define SIU_IPR_POS 1
156 #define SIU_PRIORITY 3
157
158 #endif
159 #elif defined(CONFIG_CPU_SH4)
160 #define DMTE0_IRQ 34
161 #define DMTE1_IRQ 35
162 #define DMTE2_IRQ 36
163 #define DMTE3_IRQ 37
164 #define DMTE4_IRQ 44 /* 7751R only */
165 #define DMTE5_IRQ 45 /* 7751R only */
166 #define DMTE6_IRQ 46 /* 7751R only */
167 #define DMTE7_IRQ 47 /* 7751R only */
168 #define DMAE_IRQ 38
169 #define DMA_IPR_ADDR INTC_IPRC
170 #define DMA_IPR_POS 2
171 #define DMA_PRIORITY 7
172 #endif
173
174 #if defined (CONFIG_CPU_SUBTYPE_SH7707) || defined (CONFIG_CPU_SUBTYPE_SH7708) || \
175 defined (CONFIG_CPU_SUBTYPE_SH7709) || defined (CONFIG_CPU_SUBTYPE_SH7750) || \
176 defined (CONFIG_CPU_SUBTYPE_SH7751) || defined (CONFIG_CPU_SUBTYPE_SH7706)
177 #define SCI_ERI_IRQ 23
178 #define SCI_RXI_IRQ 24
179 #define SCI_TXI_IRQ 25
180 #define SCI_IPR_ADDR INTC_IPRB
181 #define SCI_IPR_POS 1
182 #define SCI_PRIORITY 3
183 #endif
184
185 #if defined(CONFIG_CPU_SUBTYPE_SH7300)
186 #define SCIF0_IRQ 80
187 #define SCIF0_IPR_ADDR INTC_IPRG
188 #define SCIF0_IPR_POS 3
189 #define SCIF0_PRIORITY 3
190 #elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
191 defined(CONFIG_CPU_SUBTYPE_SH7706) || \
192 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
193 defined(CONFIG_CPU_SUBTYPE_SH7709)
194 #define SCIF_ERI_IRQ 56
195 #define SCIF_RXI_IRQ 57
196 #define SCIF_BRI_IRQ 58
197 #define SCIF_TXI_IRQ 59
198 #define SCIF_IPR_ADDR INTC_IPRE
199 #define SCIF_IPR_POS 1
200 #define SCIF_PRIORITY 3
201
202 #define IRDA_ERI_IRQ 52
203 #define IRDA_RXI_IRQ 53
204 #define IRDA_BRI_IRQ 54
205 #define IRDA_TXI_IRQ 55
206 #define IRDA_IPR_ADDR INTC_IPRE
207 #define IRDA_IPR_POS 2
208 #define IRDA_PRIORITY 3
209 #elif defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751) || \
210 defined(CONFIG_CPU_SUBTYPE_ST40STB1) || defined(CONFIG_CPU_SUBTYPE_SH4_202)
211 #define SCIF_ERI_IRQ 40
212 #define SCIF_RXI_IRQ 41
213 #define SCIF_BRI_IRQ 42
214 #define SCIF_TXI_IRQ 43
215 #define SCIF_IPR_ADDR INTC_IPRC
216 #define SCIF_IPR_POS 1
217 #define SCIF_PRIORITY 3
218 #if defined(CONFIG_CPU_SUBTYPE_ST40STB1)
219 #define SCIF1_ERI_IRQ 23
220 #define SCIF1_RXI_IRQ 24
221 #define SCIF1_BRI_IRQ 25
222 #define SCIF1_TXI_IRQ 26
223 #define SCIF1_IPR_ADDR INTC_IPRB
224 #define SCIF1_IPR_POS 1
225 #define SCIF1_PRIORITY 3
226 #endif /* ST40STB1 */
227
228 #endif /* 775x / SH4-202 / ST40STB1 */
229 #endif /* 7780 */
230
231 /* NR_IRQS is made from three components:
232 * 1. ONCHIP_NR_IRQS - number of IRLS + on-chip peripherial modules
233 * 2. PINT_NR_IRQS - number of PINT interrupts
234 * 3. OFFCHIP_NR_IRQS - numbe of IRQs from off-chip peripherial modules
235 */
236
237 /* 1. ONCHIP_NR_IRQS */
238 #if defined(CONFIG_CPU_SUBTYPE_SH7604)
239 # define ONCHIP_NR_IRQS 24 // Actually 21
240 #elif defined(CONFIG_CPU_SUBTYPE_SH7707)
241 # define ONCHIP_NR_IRQS 64
242 # define PINT_NR_IRQS 16
243 #elif defined(CONFIG_CPU_SUBTYPE_SH7708)
244 # define ONCHIP_NR_IRQS 32
245 #elif defined(CONFIG_CPU_SUBTYPE_SH7709) || \
246 defined(CONFIG_CPU_SUBTYPE_SH7706) || \
247 defined(CONFIG_CPU_SUBTYPE_SH7705)
248 # define ONCHIP_NR_IRQS 64 // Actually 61
249 # define PINT_NR_IRQS 16
250 #elif defined(CONFIG_CPU_SUBTYPE_SH7710)
251 # define ONCHIP_NR_IRQS 104
252 #elif defined(CONFIG_CPU_SUBTYPE_SH7750)
253 # define ONCHIP_NR_IRQS 48 // Actually 44
254 #elif defined(CONFIG_CPU_SUBTYPE_SH7751)
255 # define ONCHIP_NR_IRQS 72
256 #elif defined(CONFIG_CPU_SUBTYPE_SH7760)
257 # define ONCHIP_NR_IRQS 112 /* XXX */
258 #elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
259 # define ONCHIP_NR_IRQS 72
260 #elif defined(CONFIG_CPU_SUBTYPE_ST40STB1)
261 # define ONCHIP_NR_IRQS 144
262 #elif defined(CONFIG_CPU_SUBTYPE_SH7300) || \
263 defined(CONFIG_CPU_SUBTYPE_SH73180) || \
264 defined(CONFIG_CPU_SUBTYPE_SH7343)
265 # define ONCHIP_NR_IRQS 109
266 #elif defined(CONFIG_CPU_SUBTYPE_SH7780)
267 # define ONCHIP_NR_IRQS 111
268 #elif defined(CONFIG_SH_UNKNOWN) /* Most be last */
269 # define ONCHIP_NR_IRQS 144
270 #endif
271
272 /* 2. PINT_NR_IRQS */
273 #ifdef CONFIG_SH_UNKNOWN
274 # define PINT_NR_IRQS 16
275 #else
276 # ifndef PINT_NR_IRQS
277 # define PINT_NR_IRQS 0
278 # endif
279 #endif
280
281 #if PINT_NR_IRQS > 0
282 # define PINT_IRQ_BASE ONCHIP_NR_IRQS
283 #endif
284
285 /* 3. OFFCHIP_NR_IRQS */
286 #if defined(CONFIG_HD64461)
287 # define OFFCHIP_NR_IRQS 18
288 #elif defined (CONFIG_SH_BIGSUR) /* must be before CONFIG_HD64465 */
289 # define OFFCHIP_NR_IRQS 48
290 #elif defined(CONFIG_HD64465)
291 # define OFFCHIP_NR_IRQS 16
292 #elif defined (CONFIG_SH_EC3104)
293 # define OFFCHIP_NR_IRQS 16
294 #elif defined (CONFIG_SH_DREAMCAST)
295 # define OFFCHIP_NR_IRQS 96
296 #elif defined (CONFIG_SH_TITAN)
297 # define OFFCHIP_NR_IRQS 4
298 #elif defined(CONFIG_SH_R7780RP)
299 # define OFFCHIP_NR_IRQS 16
300 #elif defined(CONFIG_SH_7343_SOLUTION_ENGINE)
301 # define OFFCHIP_NR_IRQS 12
302 #elif defined(CONFIG_SH_UNKNOWN)
303 # define OFFCHIP_NR_IRQS 16 /* Must also be last */
304 #else
305 # define OFFCHIP_NR_IRQS 0
306 #endif
307
308 #if OFFCHIP_NR_IRQS > 0
309 # define OFFCHIP_IRQ_BASE (ONCHIP_NR_IRQS + PINT_NR_IRQS)
310 #endif
311
312 /* NR_IRQS. 1+2+3 */
313 #define NR_IRQS (ONCHIP_NR_IRQS + PINT_NR_IRQS + OFFCHIP_NR_IRQS)
314
315 extern void disable_irq(unsigned int);
316 extern void disable_irq_nosync(unsigned int);
317 extern void enable_irq(unsigned int);
318
319 /*
320 * Simple Mask Register Support
321 */
322 extern void make_maskreg_irq(unsigned int irq);
323 extern unsigned short *irq_mask_register;
324
325 /*
326 * PINT IRQs
327 */
328 void init_IRQ_pint(void);
329
330 struct ipr_data {
331 unsigned int irq;
332 unsigned int addr; /* Address of Interrupt Priority Register */
333 int shift; /* Shifts of the 16-bit data */
334 int priority; /* The priority */
335 };
336
337 /*
338 * Function for "on chip support modules".
339 */
340 extern void make_ipr_irq(struct ipr_data *table, unsigned int nr_irqs);
341 extern void make_imask_irq(unsigned int irq);
342
343 #if defined(CONFIG_CPU_SUBTYPE_SH7300)
344 #undef INTC_IPRA
345 #undef INTC_IPRB
346 #define INTC_IPRA 0xA414FEE2UL
347 #define INTC_IPRB 0xA414FEE4UL
348 #define INTC_IPRC 0xA4140016UL
349 #define INTC_IPRD 0xA4140018UL
350 #define INTC_IPRE 0xA414001AUL
351 #define INTC_IPRF 0xA4080000UL
352 #define INTC_IPRG 0xA4080002UL
353 #define INTC_IPRH 0xA4080004UL
354 #define INTC_IPRI 0xA4080006UL
355 #define INTC_IPRJ 0xA4080008UL
356
357 #define INTC_IMR0 0xA4080040UL
358 #define INTC_IMR1 0xA4080042UL
359 #define INTC_IMR2 0xA4080044UL
360 #define INTC_IMR3 0xA4080046UL
361 #define INTC_IMR4 0xA4080048UL
362 #define INTC_IMR5 0xA408004AUL
363 #define INTC_IMR6 0xA408004CUL
364 #define INTC_IMR7 0xA408004EUL
365 #define INTC_IMR8 0xA4080050UL
366 #define INTC_IMR9 0xA4080052UL
367 #define INTC_IMR10 0xA4080054UL
368
369 #define INTC_IMCR0 0xA4080060UL
370 #define INTC_IMCR1 0xA4080062UL
371 #define INTC_IMCR2 0xA4080064UL
372 #define INTC_IMCR3 0xA4080066UL
373 #define INTC_IMCR4 0xA4080068UL
374 #define INTC_IMCR5 0xA408006AUL
375 #define INTC_IMCR6 0xA408006CUL
376 #define INTC_IMCR7 0xA408006EUL
377 #define INTC_IMCR8 0xA4080070UL
378 #define INTC_IMCR9 0xA4080072UL
379 #define INTC_IMCR10 0xA4080074UL
380
381 #define INTC_ICR0 0xA414FEE0UL
382 #define INTC_ICR1 0xA4140010UL
383
384 #define INTC_IRR0 0xA4140004UL
385
386 #define PORT_PACR 0xA4050100UL
387 #define PORT_PBCR 0xA4050102UL
388 #define PORT_PCCR 0xA4050104UL
389 #define PORT_PDCR 0xA4050106UL
390 #define PORT_PECR 0xA4050108UL
391 #define PORT_PFCR 0xA405010AUL
392 #define PORT_PGCR 0xA405010CUL
393 #define PORT_PHCR 0xA405010EUL
394 #define PORT_PJCR 0xA4050110UL
395 #define PORT_PKCR 0xA4050112UL
396 #define PORT_PLCR 0xA4050114UL
397 #define PORT_SCPCR 0xA4050116UL
398 #define PORT_PMCR 0xA4050118UL
399 #define PORT_PNCR 0xA405011AUL
400 #define PORT_PQCR 0xA405011CUL
401
402 #define PORT_PSELA 0xA4050140UL
403 #define PORT_PSELB 0xA4050142UL
404 #define PORT_PSELC 0xA4050144UL
405
406 #define PORT_HIZCRA 0xA4050146UL
407 #define PORT_HIZCRB 0xA4050148UL
408 #define PORT_DRVCR 0xA4050150UL
409
410 #define PORT_PADR 0xA4050120UL
411 #define PORT_PBDR 0xA4050122UL
412 #define PORT_PCDR 0xA4050124UL
413 #define PORT_PDDR 0xA4050126UL
414 #define PORT_PEDR 0xA4050128UL
415 #define PORT_PFDR 0xA405012AUL
416 #define PORT_PGDR 0xA405012CUL
417 #define PORT_PHDR 0xA405012EUL
418 #define PORT_PJDR 0xA4050130UL
419 #define PORT_PKDR 0xA4050132UL
420 #define PORT_PLDR 0xA4050134UL
421 #define PORT_SCPDR 0xA4050136UL
422 #define PORT_PMDR 0xA4050138UL
423 #define PORT_PNDR 0xA405013AUL
424 #define PORT_PQDR 0xA405013CUL
425
426 #define IRQ0_IRQ 32
427 #define IRQ1_IRQ 33
428 #define IRQ2_IRQ 34
429 #define IRQ3_IRQ 35
430 #define IRQ4_IRQ 36
431 #define IRQ5_IRQ 37
432
433 #define IRQ0_IPR_ADDR INTC_IPRC
434 #define IRQ1_IPR_ADDR INTC_IPRC
435 #define IRQ2_IPR_ADDR INTC_IPRC
436 #define IRQ3_IPR_ADDR INTC_IPRC
437 #define IRQ4_IPR_ADDR INTC_IPRD
438 #define IRQ5_IPR_ADDR INTC_IPRD
439
440 #define IRQ0_IPR_POS 0
441 #define IRQ1_IPR_POS 1
442 #define IRQ2_IPR_POS 2
443 #define IRQ3_IPR_POS 3
444 #define IRQ4_IPR_POS 0
445 #define IRQ5_IPR_POS 1
446
447 #define IRQ0_PRIORITY 1
448 #define IRQ1_PRIORITY 1
449 #define IRQ2_PRIORITY 1
450 #define IRQ3_PRIORITY 1
451 #define IRQ4_PRIORITY 1
452 #define IRQ5_PRIORITY 1
453
454 extern int ipr_irq_demux(int irq);
455 #define __irq_demux(irq) ipr_irq_demux(irq)
456
457 #elif defined(CONFIG_CPU_SUBTYPE_SH7604)
458 #define INTC_IPRA 0xfffffee2UL
459 #define INTC_IPRB 0xfffffe60UL
460
461 #define INTC_VCRA 0xfffffe62UL
462 #define INTC_VCRB 0xfffffe64UL
463 #define INTC_VCRC 0xfffffe66UL
464 #define INTC_VCRD 0xfffffe68UL
465
466 #define INTC_VCRWDT 0xfffffee4UL
467 #define INTC_VCRDIV 0xffffff0cUL
468 #define INTC_VCRDMA0 0xffffffa0UL
469 #define INTC_VCRDMA1 0xffffffa8UL
470
471 #define INTC_ICR 0xfffffee0UL
472 #elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
473 defined(CONFIG_CPU_SUBTYPE_SH7706) || \
474 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
475 defined(CONFIG_CPU_SUBTYPE_SH7709) || \
476 defined(CONFIG_CPU_SUBTYPE_SH7710)
477 #define INTC_IRR0 0xa4000004UL
478 #define INTC_IRR1 0xa4000006UL
479 #define INTC_IRR2 0xa4000008UL
480
481 #define INTC_ICR0 0xfffffee0UL
482 #define INTC_ICR1 0xa4000010UL
483 #define INTC_ICR2 0xa4000012UL
484 #define INTC_INTER 0xa4000014UL
485
486 #define INTC_IPRC 0xa4000016UL
487 #define INTC_IPRD 0xa4000018UL
488 #define INTC_IPRE 0xa400001aUL
489 #if defined(CONFIG_CPU_SUBTYPE_SH7707)
490 #define INTC_IPRF 0xa400001cUL
491 #elif defined(CONFIG_CPU_SUBTYPE_SH7705)
492 #define INTC_IPRF 0xa4080000UL
493 #define INTC_IPRG 0xa4080002UL
494 #define INTC_IPRH 0xa4080004UL
495 #elif defined(CONFIG_CPU_SUBTYPE_SH7710)
496 /* Interrupt Controller Registers */
497 #undef INTC_IPRA
498 #undef INTC_IPRB
499 #define INTC_IPRA 0xA414FEE2UL
500 #define INTC_IPRB 0xA414FEE4UL
501 #define INTC_IPRF 0xA4080000UL
502 #define INTC_IPRG 0xA4080002UL
503 #define INTC_IPRH 0xA4080004UL
504 #define INTC_IPRI 0xA4080006UL
505
506 #undef INTC_ICR0
507 #undef INTC_ICR1
508 #define INTC_ICR0 0xA414FEE0UL
509 #define INTC_ICR1 0xA4140010UL
510
511 #define INTC_IRR0 0xa4000004UL
512 #define INTC_IRR1 0xa4000006UL
513 #define INTC_IRR2 0xa4000008UL
514 #define INTC_IRR3 0xa400000AUL
515 #define INTC_IRR4 0xa400000CUL
516 #define INTC_IRR5 0xa4080020UL
517 #define INTC_IRR7 0xa4080024UL
518 #define INTC_IRR8 0xa4080026UL
519
520 /* Interrupt numbers */
521 #define TIMER2_IRQ 18
522 #define TIMER2_IPR_ADDR INTC_IPRA
523 #define TIMER2_IPR_POS 1
524 #define TIMER2_PRIORITY 2
525
526 /* WDT */
527 #define WDT_IRQ 27
528 #define WDT_IPR_ADDR INTC_IPRB
529 #define WDT_IPR_POS 3
530 #define WDT_PRIORITY 2
531
532 #define SCIF0_ERI_IRQ 52
533 #define SCIF0_RXI_IRQ 53
534 #define SCIF0_BRI_IRQ 54
535 #define SCIF0_TXI_IRQ 55
536 #define SCIF0_IPR_ADDR INTC_IPRE
537 #define SCIF0_IPR_POS 2
538 #define SCIF0_PRIORITY 3
539
540 #define DMTE4_IRQ 76
541 #define DMTE5_IRQ 77
542 #define DMA2_IPR_ADDR INTC_IPRF
543 #define DMA2_IPR_POS 2
544 #define DMA2_PRIORITY 7
545
546 #define IPSEC_IRQ 79
547 #define IPSEC_IPR_ADDR INTC_IPRF
548 #define IPSEC_IPR_POS 3
549 #define IPSEC_PRIORITY 3
550
551 /* EDMAC */
552 #define EDMAC0_IRQ 80
553 #define EDMAC0_IPR_ADDR INTC_IPRG
554 #define EDMAC0_IPR_POS 3
555 #define EDMAC0_PRIORITY 3
556
557 #define EDMAC1_IRQ 81
558 #define EDMAC1_IPR_ADDR INTC_IPRG
559 #define EDMAC1_IPR_POS 2
560 #define EDMAC1_PRIORITY 3
561
562 #define EDMAC2_IRQ 82
563 #define EDMAC2_IPR_ADDR INTC_IPRG
564 #define EDMAC2_IPR_POS 1
565 #define EDMAC2_PRIORITY 3
566
567 /* SIOF */
568 #define SIOF0_ERI_IRQ 96
569 #define SIOF0_TXI_IRQ 97
570 #define SIOF0_RXI_IRQ 98
571 #define SIOF0_CCI_IRQ 99
572 #define SIOF0_IPR_ADDR INTC_IPRH
573 #define SIOF0_IPR_POS 0
574 #define SIOF0_PRIORITY 7
575
576 #define SIOF1_ERI_IRQ 100
577 #define SIOF1_TXI_IRQ 101
578 #define SIOF1_RXI_IRQ 102
579 #define SIOF1_CCI_IRQ 103
580 #define SIOF1_IPR_ADDR INTC_IPRI
581 #define SIOF1_IPR_POS 1
582 #define SIOF1_PRIORITY 7
583 #endif /* CONFIG_CPU_SUBTYPE_SH7710 */
584
585 #if defined(CONFIG_CPU_SUBTYPE_SH7710)
586 #define PORT_PACR 0xa4050100UL
587 #define PORT_PBCR 0xa4050102UL
588 #define PORT_PCCR 0xa4050104UL
589 #define PORT_PETCR 0xa4050106UL
590 #define PORT_PADR 0xa4050120UL
591 #define PORT_PBDR 0xa4050122UL
592 #define PORT_PCDR 0xa4050124UL
593 #else
594 #define PORT_PACR 0xa4000100UL
595 #define PORT_PBCR 0xa4000102UL
596 #define PORT_PCCR 0xa4000104UL
597 #define PORT_PFCR 0xa400010aUL
598 #define PORT_PADR 0xa4000120UL
599 #define PORT_PBDR 0xa4000122UL
600 #define PORT_PCDR 0xa4000124UL
601 #define PORT_PFDR 0xa400012aUL
602 #endif
603
604 #define IRQ0_IRQ 32
605 #define IRQ1_IRQ 33
606 #define IRQ2_IRQ 34
607 #define IRQ3_IRQ 35
608 #define IRQ4_IRQ 36
609 #define IRQ5_IRQ 37
610
611 #define IRQ0_IPR_ADDR INTC_IPRC
612 #define IRQ1_IPR_ADDR INTC_IPRC
613 #define IRQ2_IPR_ADDR INTC_IPRC
614 #define IRQ3_IPR_ADDR INTC_IPRC
615 #define IRQ4_IPR_ADDR INTC_IPRD
616 #define IRQ5_IPR_ADDR INTC_IPRD
617
618 #define IRQ0_IPR_POS 0
619 #define IRQ1_IPR_POS 1
620 #define IRQ2_IPR_POS 2
621 #define IRQ3_IPR_POS 3
622 #define IRQ4_IPR_POS 0
623 #define IRQ5_IPR_POS 1
624
625 #define IRQ0_PRIORITY 1
626 #define IRQ1_PRIORITY 1
627 #define IRQ2_PRIORITY 1
628 #define IRQ3_PRIORITY 1
629 #define IRQ4_PRIORITY 1
630 #define IRQ5_PRIORITY 1
631
632 #define PINT0_IRQ 40
633 #define PINT8_IRQ 41
634
635 #define PINT0_IPR_ADDR INTC_IPRD
636 #define PINT8_IPR_ADDR INTC_IPRD
637
638 #define PINT0_IPR_POS 3
639 #define PINT8_IPR_POS 2
640 #define PINT0_PRIORITY 2
641 #define PINT8_PRIORITY 2
642
643 extern int ipr_irq_demux(int irq);
644 #define __irq_demux(irq) ipr_irq_demux(irq)
645 #endif /* CONFIG_CPU_SUBTYPE_SH7707 || CONFIG_CPU_SUBTYPE_SH7709 */
646
647 #if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751) || \
648 defined(CONFIG_CPU_SUBTYPE_ST40STB1) || defined(CONFIG_CPU_SUBTYPE_SH4_202)
649 #define INTC_ICR 0xffd00000
650 #define INTC_ICR_NMIL (1<<15)
651 #define INTC_ICR_MAI (1<<14)
652 #define INTC_ICR_NMIB (1<<9)
653 #define INTC_ICR_NMIE (1<<8)
654 #define INTC_ICR_IRLM (1<<7)
655 #endif
656
657 #ifdef CONFIG_CPU_SUBTYPE_SH7780
658 #include <asm/irq-sh7780.h>
659 #endif
660
661 /* SH with INTC2-style interrupts */
662 #ifdef CONFIG_CPU_HAS_INTC2_IRQ
663 #if defined(CONFIG_CPU_SUBTYPE_ST40STB1)
664 #define INTC2_BASE 0xfe080000
665 #define INTC2_FIRST_IRQ 64
666 #define INTC2_INTREQ_OFFSET 0x20
667 #define INTC2_INTMSK_OFFSET 0x40
668 #define INTC2_INTMSKCLR_OFFSET 0x60
669 #define NR_INTC2_IRQS 25
670 #elif defined(CONFIG_CPU_SUBTYPE_SH7760)
671 #define INTC2_BASE 0xfe080000
672 #define INTC2_FIRST_IRQ 48 /* INTEVT 0x800 */
673 #define INTC2_INTREQ_OFFSET 0x20
674 #define INTC2_INTMSK_OFFSET 0x40
675 #define INTC2_INTMSKCLR_OFFSET 0x60
676 #define NR_INTC2_IRQS 64
677 #elif defined(CONFIG_CPU_SUBTYPE_SH7780)
678 #define INTC2_BASE 0xffd40000
679 #define INTC2_FIRST_IRQ 21
680 #define INTC2_INTMSK_OFFSET (0x38)
681 #define INTC2_INTMSKCLR_OFFSET (0x3c)
682 #define NR_INTC2_IRQS 60
683 #endif
684
685 #define INTC2_INTPRI_OFFSET 0x00
686
687 struct intc2_data {
688 unsigned short irq;
689 unsigned char ipr_offset, ipr_shift;
690 unsigned char msk_offset, msk_shift;
691 unsigned char priority;
692 };
693
694 void make_intc2_irq(struct intc2_data *, unsigned int nr_irqs);
695 void init_IRQ_intc2(void);
696 #endif
697
698 extern int shmse_irq_demux(int irq);
699
700 static inline int generic_irq_demux(int irq)
701 {
702 return irq;
703 }
704
705 #ifndef __irq_demux
706 #define __irq_demux(irq) (irq)
707 #endif
708 #define irq_canonicalize(irq) (irq)
709 #define irq_demux(irq) __irq_demux(sh_mv.mv_irq_demux(irq))
710
711 #ifdef CONFIG_4KSTACKS
712 extern void irq_ctx_init(int cpu);
713 extern void irq_ctx_exit(int cpu);
714 # define __ARCH_HAS_DO_SOFTIRQ
715 #else
716 # define irq_ctx_init(cpu) do { } while (0)
717 # define irq_ctx_exit(cpu) do { } while (0)
718 #endif
719
720 #if defined(CONFIG_CPU_SUBTYPE_SH73180)
721 #include <asm/irq-sh73180.h>
722 #endif
723
724 #if defined(CONFIG_CPU_SUBTYPE_SH7343)
725 #include <asm/irq-sh7343.h>
726 #endif
727
728 #endif /* __ASM_SH_IRQ_H */
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