3 * hda_intel.c - Implementation of primary alsa driver code base for Intel HD Audio.
5 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
8 * PeiSen Hou <pshou@realtek.com.tw>
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the Free
12 * Software Foundation; either version 2 of the License, or (at your option)
15 * This program is distributed in the hope that it will be useful, but WITHOUT
16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
20 * You should have received a copy of the GNU General Public License along with
21 * this program; if not, write to the Free Software Foundation, Inc., 59
22 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
26 * Matt Jared matt.jared@intel.com
27 * Andy Kopp andy.kopp@intel.com
28 * Dan Kogan dan.d.kogan@intel.com
32 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
36 #include <sound/driver.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/kernel.h>
41 #include <linux/module.h>
42 #include <linux/moduleparam.h>
43 #include <linux/init.h>
44 #include <linux/slab.h>
45 #include <linux/pci.h>
46 #include <linux/mutex.h>
47 #include <sound/core.h>
48 #include <sound/initval.h>
49 #include "hda_codec.h"
52 static int index
= SNDRV_DEFAULT_IDX1
;
53 static char *id
= SNDRV_DEFAULT_STR1
;
55 static int position_fix
;
56 static int probe_mask
= -1;
57 static int single_cmd
;
59 module_param(index
, int, 0444);
60 MODULE_PARM_DESC(index
, "Index value for Intel HD audio interface.");
61 module_param(id
, charp
, 0444);
62 MODULE_PARM_DESC(id
, "ID string for Intel HD audio interface.");
63 module_param(model
, charp
, 0444);
64 MODULE_PARM_DESC(model
, "Use the given board model.");
65 module_param(position_fix
, int, 0444);
66 MODULE_PARM_DESC(position_fix
, "Fix DMA pointer (0 = auto, 1 = none, 2 = POSBUF, 3 = FIFO size).");
67 module_param(probe_mask
, int, 0444);
68 MODULE_PARM_DESC(probe_mask
, "Bitmask to probe codecs (default = -1).");
69 module_param(single_cmd
, bool, 0444);
70 MODULE_PARM_DESC(single_cmd
, "Use single command to communicate with codecs (for debugging only).");
73 /* just for backward compatibility */
75 module_param(enable
, bool, 0444);
77 MODULE_LICENSE("GPL");
78 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
90 MODULE_DESCRIPTION("Intel HDA driver");
92 #define SFX "hda-intel: "
97 #define ICH6_REG_GCAP 0x00
98 #define ICH6_REG_VMIN 0x02
99 #define ICH6_REG_VMAJ 0x03
100 #define ICH6_REG_OUTPAY 0x04
101 #define ICH6_REG_INPAY 0x06
102 #define ICH6_REG_GCTL 0x08
103 #define ICH6_REG_WAKEEN 0x0c
104 #define ICH6_REG_STATESTS 0x0e
105 #define ICH6_REG_GSTS 0x10
106 #define ICH6_REG_INTCTL 0x20
107 #define ICH6_REG_INTSTS 0x24
108 #define ICH6_REG_WALCLK 0x30
109 #define ICH6_REG_SYNC 0x34
110 #define ICH6_REG_CORBLBASE 0x40
111 #define ICH6_REG_CORBUBASE 0x44
112 #define ICH6_REG_CORBWP 0x48
113 #define ICH6_REG_CORBRP 0x4A
114 #define ICH6_REG_CORBCTL 0x4c
115 #define ICH6_REG_CORBSTS 0x4d
116 #define ICH6_REG_CORBSIZE 0x4e
118 #define ICH6_REG_RIRBLBASE 0x50
119 #define ICH6_REG_RIRBUBASE 0x54
120 #define ICH6_REG_RIRBWP 0x58
121 #define ICH6_REG_RINTCNT 0x5a
122 #define ICH6_REG_RIRBCTL 0x5c
123 #define ICH6_REG_RIRBSTS 0x5d
124 #define ICH6_REG_RIRBSIZE 0x5e
126 #define ICH6_REG_IC 0x60
127 #define ICH6_REG_IR 0x64
128 #define ICH6_REG_IRS 0x68
129 #define ICH6_IRS_VALID (1<<1)
130 #define ICH6_IRS_BUSY (1<<0)
132 #define ICH6_REG_DPLBASE 0x70
133 #define ICH6_REG_DPUBASE 0x74
134 #define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
136 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
137 enum { SDI0
, SDI1
, SDI2
, SDI3
, SDO0
, SDO1
, SDO2
, SDO3
};
139 /* stream register offsets from stream base */
140 #define ICH6_REG_SD_CTL 0x00
141 #define ICH6_REG_SD_STS 0x03
142 #define ICH6_REG_SD_LPIB 0x04
143 #define ICH6_REG_SD_CBL 0x08
144 #define ICH6_REG_SD_LVI 0x0c
145 #define ICH6_REG_SD_FIFOW 0x0e
146 #define ICH6_REG_SD_FIFOSIZE 0x10
147 #define ICH6_REG_SD_FORMAT 0x12
148 #define ICH6_REG_SD_BDLPL 0x18
149 #define ICH6_REG_SD_BDLPU 0x1c
152 #define ICH6_PCIREG_TCSEL 0x44
158 /* max number of SDs */
159 /* ICH, ATI and VIA have 4 playback and 4 capture */
160 #define ICH6_CAPTURE_INDEX 0
161 #define ICH6_NUM_CAPTURE 4
162 #define ICH6_PLAYBACK_INDEX 4
163 #define ICH6_NUM_PLAYBACK 4
165 /* ULI has 6 playback and 5 capture */
166 #define ULI_CAPTURE_INDEX 0
167 #define ULI_NUM_CAPTURE 5
168 #define ULI_PLAYBACK_INDEX 5
169 #define ULI_NUM_PLAYBACK 6
171 /* ATI HDMI has 1 playback and 0 capture */
172 #define ATIHDMI_CAPTURE_INDEX 0
173 #define ATIHDMI_NUM_CAPTURE 0
174 #define ATIHDMI_PLAYBACK_INDEX 0
175 #define ATIHDMI_NUM_PLAYBACK 1
177 /* this number is statically defined for simplicity */
178 #define MAX_AZX_DEV 16
180 /* max number of fragments - we may use more if allocating more pages for BDL */
181 #define BDL_SIZE PAGE_ALIGN(8192)
182 #define AZX_MAX_FRAG (BDL_SIZE / (MAX_AZX_DEV * 16))
183 /* max buffer size - no h/w limit, you can increase as you like */
184 #define AZX_MAX_BUF_SIZE (1024*1024*1024)
185 /* max number of PCM devics per card */
186 #define AZX_MAX_AUDIO_PCMS 6
187 #define AZX_MAX_MODEM_PCMS 2
188 #define AZX_MAX_PCMS (AZX_MAX_AUDIO_PCMS + AZX_MAX_MODEM_PCMS)
190 /* RIRB int mask: overrun[2], response[0] */
191 #define RIRB_INT_RESPONSE 0x01
192 #define RIRB_INT_OVERRUN 0x04
193 #define RIRB_INT_MASK 0x05
195 /* STATESTS int mask: SD2,SD1,SD0 */
196 #define STATESTS_INT_MASK 0x07
197 #define AZX_MAX_CODECS 4
200 #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
201 #define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
202 #define SD_CTL_STREAM_TAG_MASK (0xf << 20)
203 #define SD_CTL_STREAM_TAG_SHIFT 20
205 /* SD_CTL and SD_STS */
206 #define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
207 #define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
208 #define SD_INT_COMPLETE 0x04 /* completion interrupt */
209 #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|SD_INT_COMPLETE)
212 #define SD_STS_FIFO_READY 0x20 /* FIFO ready */
214 /* INTCTL and INTSTS */
215 #define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
216 #define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
217 #define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
219 /* GCTL unsolicited response enable bit */
220 #define ICH6_GCTL_UREN (1<<8)
223 #define ICH6_GCTL_RESET (1<<0)
225 /* CORB/RIRB control, read/write pointer */
226 #define ICH6_RBCTL_DMA_EN 0x02 /* enable DMA */
227 #define ICH6_RBCTL_IRQ_EN 0x01 /* enable IRQ */
228 #define ICH6_RBRWP_CLR 0x8000 /* read/write pointer clear */
229 /* below are so far hardcoded - should read registers in future */
230 #define ICH6_MAX_CORB_ENTRIES 256
231 #define ICH6_MAX_RIRB_ENTRIES 256
233 /* position fix mode */
241 /* Defines for ATI HD Audio support in SB450 south bridge */
242 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
243 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
245 /* Defines for Nvidia HDA support */
246 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
247 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
253 u32
*bdl
; /* virtual address of the BDL */
254 dma_addr_t bdl_addr
; /* physical address of the BDL */
255 volatile u32
*posbuf
; /* position buffer pointer */
257 unsigned int bufsize
; /* size of the play buffer in bytes */
258 unsigned int fragsize
; /* size of each period in bytes */
259 unsigned int frags
; /* number for period in the play buffer */
260 unsigned int fifo_size
; /* FIFO size */
262 void __iomem
*sd_addr
; /* stream descriptor pointer */
264 u32 sd_int_sta_mask
; /* stream int status mask */
267 struct snd_pcm_substream
*substream
; /* assigned substream, set in PCM open */
268 unsigned int format_val
; /* format value to be set in the controller and the codec */
269 unsigned char stream_tag
; /* assigned stream */
270 unsigned char index
; /* stream index */
271 /* for sanity check of position buffer */
272 unsigned int period_intr
;
274 unsigned int opened
: 1;
275 unsigned int running
: 1;
280 u32
*buf
; /* CORB/RIRB buffer
281 * Each CORB entry is 4byte, RIRB is 8byte
283 dma_addr_t addr
; /* physical address of CORB/RIRB buffer */
285 unsigned short rp
, wp
; /* read/write pointers */
286 int cmds
; /* number of pending requests */
287 u32 res
; /* last read value */
291 struct snd_card
*card
;
294 /* chip type specific */
296 int playback_streams
;
297 int playback_index_offset
;
299 int capture_index_offset
;
304 void __iomem
*remap_addr
;
309 struct mutex open_mutex
;
311 /* streams (x num_streams) */
312 struct azx_dev
*azx_dev
;
315 unsigned int pcm_devs
;
316 struct snd_pcm
*pcm
[AZX_MAX_PCMS
];
319 unsigned short codec_mask
;
326 /* BDL, CORB/RIRB and position buffers */
327 struct snd_dma_buffer bdl
;
328 struct snd_dma_buffer rb
;
329 struct snd_dma_buffer posbuf
;
333 unsigned int initialized
: 1;
334 unsigned int single_cmd
: 1;
348 static char *driver_short_names
[] __devinitdata
= {
349 [AZX_DRIVER_ICH
] = "HDA Intel",
350 [AZX_DRIVER_ATI
] = "HDA ATI SB",
351 [AZX_DRIVER_ATIHDMI
] = "HDA ATI HDMI",
352 [AZX_DRIVER_VIA
] = "HDA VIA VT82xx",
353 [AZX_DRIVER_SIS
] = "HDA SIS966",
354 [AZX_DRIVER_ULI
] = "HDA ULI M5461",
355 [AZX_DRIVER_NVIDIA
] = "HDA NVidia",
359 * macros for easy use
361 #define azx_writel(chip,reg,value) \
362 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
363 #define azx_readl(chip,reg) \
364 readl((chip)->remap_addr + ICH6_REG_##reg)
365 #define azx_writew(chip,reg,value) \
366 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
367 #define azx_readw(chip,reg) \
368 readw((chip)->remap_addr + ICH6_REG_##reg)
369 #define azx_writeb(chip,reg,value) \
370 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
371 #define azx_readb(chip,reg) \
372 readb((chip)->remap_addr + ICH6_REG_##reg)
374 #define azx_sd_writel(dev,reg,value) \
375 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
376 #define azx_sd_readl(dev,reg) \
377 readl((dev)->sd_addr + ICH6_REG_##reg)
378 #define azx_sd_writew(dev,reg,value) \
379 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
380 #define azx_sd_readw(dev,reg) \
381 readw((dev)->sd_addr + ICH6_REG_##reg)
382 #define azx_sd_writeb(dev,reg,value) \
383 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
384 #define azx_sd_readb(dev,reg) \
385 readb((dev)->sd_addr + ICH6_REG_##reg)
387 /* for pcm support */
388 #define get_azx_dev(substream) (substream->runtime->private_data)
390 /* Get the upper 32bit of the given dma_addr_t
391 * Compiler should optimize and eliminate the code if dma_addr_t is 32bit
393 #define upper_32bit(addr) (sizeof(addr) > 4 ? (u32)((addr) >> 32) : (u32)0)
397 * Interface for HD codec
401 * CORB / RIRB interface
403 static int azx_alloc_cmd_io(struct azx
*chip
)
407 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
408 err
= snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV
, snd_dma_pci_data(chip
->pci
),
409 PAGE_SIZE
, &chip
->rb
);
411 snd_printk(KERN_ERR SFX
"cannot allocate CORB/RIRB\n");
417 static void azx_init_cmd_io(struct azx
*chip
)
420 chip
->corb
.addr
= chip
->rb
.addr
;
421 chip
->corb
.buf
= (u32
*)chip
->rb
.area
;
422 azx_writel(chip
, CORBLBASE
, (u32
)chip
->corb
.addr
);
423 azx_writel(chip
, CORBUBASE
, upper_32bit(chip
->corb
.addr
));
425 /* set the corb size to 256 entries (ULI requires explicitly) */
426 azx_writeb(chip
, CORBSIZE
, 0x02);
427 /* set the corb write pointer to 0 */
428 azx_writew(chip
, CORBWP
, 0);
429 /* reset the corb hw read pointer */
430 azx_writew(chip
, CORBRP
, ICH6_RBRWP_CLR
);
431 /* enable corb dma */
432 azx_writeb(chip
, CORBCTL
, ICH6_RBCTL_DMA_EN
);
435 chip
->rirb
.addr
= chip
->rb
.addr
+ 2048;
436 chip
->rirb
.buf
= (u32
*)(chip
->rb
.area
+ 2048);
437 azx_writel(chip
, RIRBLBASE
, (u32
)chip
->rirb
.addr
);
438 azx_writel(chip
, RIRBUBASE
, upper_32bit(chip
->rirb
.addr
));
440 /* set the rirb size to 256 entries (ULI requires explicitly) */
441 azx_writeb(chip
, RIRBSIZE
, 0x02);
442 /* reset the rirb hw write pointer */
443 azx_writew(chip
, RIRBWP
, ICH6_RBRWP_CLR
);
444 /* set N=1, get RIRB response interrupt for new entry */
445 azx_writew(chip
, RINTCNT
, 1);
446 /* enable rirb dma and response irq */
447 azx_writeb(chip
, RIRBCTL
, ICH6_RBCTL_DMA_EN
| ICH6_RBCTL_IRQ_EN
);
448 chip
->rirb
.rp
= chip
->rirb
.cmds
= 0;
451 static void azx_free_cmd_io(struct azx
*chip
)
453 /* disable ringbuffer DMAs */
454 azx_writeb(chip
, RIRBCTL
, 0);
455 azx_writeb(chip
, CORBCTL
, 0);
459 static int azx_corb_send_cmd(struct hda_codec
*codec
, hda_nid_t nid
, int direct
,
460 unsigned int verb
, unsigned int para
)
462 struct azx
*chip
= codec
->bus
->private_data
;
466 val
= (u32
)(codec
->addr
& 0x0f) << 28;
467 val
|= (u32
)direct
<< 27;
468 val
|= (u32
)nid
<< 20;
472 /* add command to corb */
473 wp
= azx_readb(chip
, CORBWP
);
475 wp
%= ICH6_MAX_CORB_ENTRIES
;
477 spin_lock_irq(&chip
->reg_lock
);
479 chip
->corb
.buf
[wp
] = cpu_to_le32(val
);
480 azx_writel(chip
, CORBWP
, wp
);
481 spin_unlock_irq(&chip
->reg_lock
);
486 #define ICH6_RIRB_EX_UNSOL_EV (1<<4)
488 /* retrieve RIRB entry - called from interrupt handler */
489 static void azx_update_rirb(struct azx
*chip
)
494 wp
= azx_readb(chip
, RIRBWP
);
495 if (wp
== chip
->rirb
.wp
)
499 while (chip
->rirb
.rp
!= wp
) {
501 chip
->rirb
.rp
%= ICH6_MAX_RIRB_ENTRIES
;
503 rp
= chip
->rirb
.rp
<< 1; /* an RIRB entry is 8-bytes */
504 res_ex
= le32_to_cpu(chip
->rirb
.buf
[rp
+ 1]);
505 res
= le32_to_cpu(chip
->rirb
.buf
[rp
]);
506 if (res_ex
& ICH6_RIRB_EX_UNSOL_EV
)
507 snd_hda_queue_unsol_event(chip
->bus
, res
, res_ex
);
508 else if (chip
->rirb
.cmds
) {
510 chip
->rirb
.res
= res
;
515 /* receive a response */
516 static unsigned int azx_rirb_get_response(struct hda_codec
*codec
)
518 struct azx
*chip
= codec
->bus
->private_data
;
521 while (chip
->rirb
.cmds
) {
524 "hda_intel: azx_get_response timeout, "
525 "switching to single_cmd mode...\n");
526 chip
->rirb
.rp
= azx_readb(chip
, RIRBWP
);
528 /* switch to single_cmd mode */
529 chip
->single_cmd
= 1;
530 azx_free_cmd_io(chip
);
535 return chip
->rirb
.res
; /* the last value */
539 * Use the single immediate command instead of CORB/RIRB for simplicity
541 * Note: according to Intel, this is not preferred use. The command was
542 * intended for the BIOS only, and may get confused with unsolicited
543 * responses. So, we shouldn't use it for normal operation from the
545 * I left the codes, however, for debugging/testing purposes.
549 static int azx_single_send_cmd(struct hda_codec
*codec
, hda_nid_t nid
,
550 int direct
, unsigned int verb
,
553 struct azx
*chip
= codec
->bus
->private_data
;
557 val
= (u32
)(codec
->addr
& 0x0f) << 28;
558 val
|= (u32
)direct
<< 27;
559 val
|= (u32
)nid
<< 20;
564 /* check ICB busy bit */
565 if (! (azx_readw(chip
, IRS
) & ICH6_IRS_BUSY
)) {
566 /* Clear IRV valid bit */
567 azx_writew(chip
, IRS
, azx_readw(chip
, IRS
) | ICH6_IRS_VALID
);
568 azx_writel(chip
, IC
, val
);
569 azx_writew(chip
, IRS
, azx_readw(chip
, IRS
) | ICH6_IRS_BUSY
);
574 snd_printd(SFX
"send_cmd timeout: IRS=0x%x, val=0x%x\n", azx_readw(chip
, IRS
), val
);
578 /* receive a response */
579 static unsigned int azx_single_get_response(struct hda_codec
*codec
)
581 struct azx
*chip
= codec
->bus
->private_data
;
585 /* check IRV busy bit */
586 if (azx_readw(chip
, IRS
) & ICH6_IRS_VALID
)
587 return azx_readl(chip
, IR
);
590 snd_printd(SFX
"get_response timeout: IRS=0x%x\n", azx_readw(chip
, IRS
));
591 return (unsigned int)-1;
595 * The below are the main callbacks from hda_codec.
597 * They are just the skeleton to call sub-callbacks according to the
598 * current setting of chip->single_cmd.
602 static int azx_send_cmd(struct hda_codec
*codec
, hda_nid_t nid
,
603 int direct
, unsigned int verb
,
606 struct azx
*chip
= codec
->bus
->private_data
;
607 if (chip
->single_cmd
)
608 return azx_single_send_cmd(codec
, nid
, direct
, verb
, para
);
610 return azx_corb_send_cmd(codec
, nid
, direct
, verb
, para
);
614 static unsigned int azx_get_response(struct hda_codec
*codec
)
616 struct azx
*chip
= codec
->bus
->private_data
;
617 if (chip
->single_cmd
)
618 return azx_single_get_response(codec
);
620 return azx_rirb_get_response(codec
);
624 /* reset codec link */
625 static int azx_reset(struct azx
*chip
)
629 /* reset controller */
630 azx_writel(chip
, GCTL
, azx_readl(chip
, GCTL
) & ~ICH6_GCTL_RESET
);
633 while (azx_readb(chip
, GCTL
) && --count
)
636 /* delay for >= 100us for codec PLL to settle per spec
637 * Rev 0.9 section 5.5.1
641 /* Bring controller out of reset */
642 azx_writeb(chip
, GCTL
, azx_readb(chip
, GCTL
) | ICH6_GCTL_RESET
);
645 while (! azx_readb(chip
, GCTL
) && --count
)
648 /* Brent Chartrand said to wait >= 540us for codecs to intialize */
651 /* check to see if controller is ready */
652 if (! azx_readb(chip
, GCTL
)) {
653 snd_printd("azx_reset: controller not ready!\n");
657 /* Accept unsolicited responses */
658 azx_writel(chip
, GCTL
, azx_readl(chip
, GCTL
) | ICH6_GCTL_UREN
);
661 if (! chip
->codec_mask
) {
662 chip
->codec_mask
= azx_readw(chip
, STATESTS
);
663 snd_printdd("codec_mask = 0x%x\n", chip
->codec_mask
);
674 /* enable interrupts */
675 static void azx_int_enable(struct azx
*chip
)
677 /* enable controller CIE and GIE */
678 azx_writel(chip
, INTCTL
, azx_readl(chip
, INTCTL
) |
679 ICH6_INT_CTRL_EN
| ICH6_INT_GLOBAL_EN
);
682 /* disable interrupts */
683 static void azx_int_disable(struct azx
*chip
)
687 /* disable interrupts in stream descriptor */
688 for (i
= 0; i
< chip
->num_streams
; i
++) {
689 struct azx_dev
*azx_dev
= &chip
->azx_dev
[i
];
690 azx_sd_writeb(azx_dev
, SD_CTL
,
691 azx_sd_readb(azx_dev
, SD_CTL
) & ~SD_INT_MASK
);
694 /* disable SIE for all streams */
695 azx_writeb(chip
, INTCTL
, 0);
697 /* disable controller CIE and GIE */
698 azx_writel(chip
, INTCTL
, azx_readl(chip
, INTCTL
) &
699 ~(ICH6_INT_CTRL_EN
| ICH6_INT_GLOBAL_EN
));
702 /* clear interrupts */
703 static void azx_int_clear(struct azx
*chip
)
707 /* clear stream status */
708 for (i
= 0; i
< chip
->num_streams
; i
++) {
709 struct azx_dev
*azx_dev
= &chip
->azx_dev
[i
];
710 azx_sd_writeb(azx_dev
, SD_STS
, SD_INT_MASK
);
714 azx_writeb(chip
, STATESTS
, STATESTS_INT_MASK
);
716 /* clear rirb status */
717 azx_writeb(chip
, RIRBSTS
, RIRB_INT_MASK
);
719 /* clear int status */
720 azx_writel(chip
, INTSTS
, ICH6_INT_CTRL_EN
| ICH6_INT_ALL_STREAM
);
724 static void azx_stream_start(struct azx
*chip
, struct azx_dev
*azx_dev
)
727 azx_writeb(chip
, INTCTL
,
728 azx_readb(chip
, INTCTL
) | (1 << azx_dev
->index
));
729 /* set DMA start and interrupt mask */
730 azx_sd_writeb(azx_dev
, SD_CTL
, azx_sd_readb(azx_dev
, SD_CTL
) |
731 SD_CTL_DMA_START
| SD_INT_MASK
);
735 static void azx_stream_stop(struct azx
*chip
, struct azx_dev
*azx_dev
)
738 azx_sd_writeb(azx_dev
, SD_CTL
, azx_sd_readb(azx_dev
, SD_CTL
) &
739 ~(SD_CTL_DMA_START
| SD_INT_MASK
));
740 azx_sd_writeb(azx_dev
, SD_STS
, SD_INT_MASK
); /* to be sure */
742 azx_writeb(chip
, INTCTL
,
743 azx_readb(chip
, INTCTL
) & ~(1 << azx_dev
->index
));
748 * initialize the chip
750 static void azx_init_chip(struct azx
*chip
)
754 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
755 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
756 * Ensuring these bits are 0 clears playback static on some HD Audio codecs
758 pci_read_config_byte (chip
->pci
, ICH6_PCIREG_TCSEL
, ®
);
759 pci_write_config_byte(chip
->pci
, ICH6_PCIREG_TCSEL
, reg
& 0xf8);
761 /* reset controller */
764 /* initialize interrupts */
766 azx_int_enable(chip
);
768 /* initialize the codec command I/O */
769 if (! chip
->single_cmd
)
770 azx_init_cmd_io(chip
);
772 /* program the position buffer */
773 azx_writel(chip
, DPLBASE
, (u32
)chip
->posbuf
.addr
);
774 azx_writel(chip
, DPUBASE
, upper_32bit(chip
->posbuf
.addr
));
776 switch (chip
->driver_type
) {
778 /* For ATI SB450 azalia HD audio, we need to enable snoop */
779 pci_read_config_byte(chip
->pci
, ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR
,
781 pci_write_config_byte(chip
->pci
, ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR
,
782 (reg
& 0xf8) | ATI_SB450_HDAUDIO_ENABLE_SNOOP
);
784 case AZX_DRIVER_NVIDIA
:
785 /* For NVIDIA HDA, enable snoop */
786 pci_read_config_byte(chip
->pci
,NVIDIA_HDA_TRANSREG_ADDR
, ®
);
787 pci_write_config_byte(chip
->pci
,NVIDIA_HDA_TRANSREG_ADDR
,
788 (reg
& 0xf0) | NVIDIA_HDA_ENABLE_COHBITS
);
797 static irqreturn_t
azx_interrupt(int irq
, void* dev_id
, struct pt_regs
*regs
)
799 struct azx
*chip
= dev_id
;
800 struct azx_dev
*azx_dev
;
804 spin_lock(&chip
->reg_lock
);
806 status
= azx_readl(chip
, INTSTS
);
808 spin_unlock(&chip
->reg_lock
);
812 for (i
= 0; i
< chip
->num_streams
; i
++) {
813 azx_dev
= &chip
->azx_dev
[i
];
814 if (status
& azx_dev
->sd_int_sta_mask
) {
815 azx_sd_writeb(azx_dev
, SD_STS
, SD_INT_MASK
);
816 if (azx_dev
->substream
&& azx_dev
->running
) {
817 azx_dev
->period_intr
++;
818 spin_unlock(&chip
->reg_lock
);
819 snd_pcm_period_elapsed(azx_dev
->substream
);
820 spin_lock(&chip
->reg_lock
);
826 status
= azx_readb(chip
, RIRBSTS
);
827 if (status
& RIRB_INT_MASK
) {
828 if (! chip
->single_cmd
&& (status
& RIRB_INT_RESPONSE
))
829 azx_update_rirb(chip
);
830 azx_writeb(chip
, RIRBSTS
, RIRB_INT_MASK
);
834 /* clear state status int */
835 if (azx_readb(chip
, STATESTS
) & 0x04)
836 azx_writeb(chip
, STATESTS
, 0x04);
838 spin_unlock(&chip
->reg_lock
);
847 static void azx_setup_periods(struct azx_dev
*azx_dev
)
849 u32
*bdl
= azx_dev
->bdl
;
850 dma_addr_t dma_addr
= azx_dev
->substream
->runtime
->dma_addr
;
853 /* reset BDL address */
854 azx_sd_writel(azx_dev
, SD_BDLPL
, 0);
855 azx_sd_writel(azx_dev
, SD_BDLPU
, 0);
857 /* program the initial BDL entries */
858 for (idx
= 0; idx
< azx_dev
->frags
; idx
++) {
859 unsigned int off
= idx
<< 2; /* 4 dword step */
860 dma_addr_t addr
= dma_addr
+ idx
* azx_dev
->fragsize
;
861 /* program the address field of the BDL entry */
862 bdl
[off
] = cpu_to_le32((u32
)addr
);
863 bdl
[off
+1] = cpu_to_le32(upper_32bit(addr
));
865 /* program the size field of the BDL entry */
866 bdl
[off
+2] = cpu_to_le32(azx_dev
->fragsize
);
868 /* program the IOC to enable interrupt when buffer completes */
869 bdl
[off
+3] = cpu_to_le32(0x01);
874 * set up the SD for streaming
876 static int azx_setup_controller(struct azx
*chip
, struct azx_dev
*azx_dev
)
881 /* make sure the run bit is zero for SD */
882 azx_sd_writeb(azx_dev
, SD_CTL
, azx_sd_readb(azx_dev
, SD_CTL
) & ~SD_CTL_DMA_START
);
884 azx_sd_writeb(azx_dev
, SD_CTL
, azx_sd_readb(azx_dev
, SD_CTL
) | SD_CTL_STREAM_RESET
);
887 while (!((val
= azx_sd_readb(azx_dev
, SD_CTL
)) & SD_CTL_STREAM_RESET
) &&
890 val
&= ~SD_CTL_STREAM_RESET
;
891 azx_sd_writeb(azx_dev
, SD_CTL
, val
);
895 /* waiting for hardware to report that the stream is out of reset */
896 while (((val
= azx_sd_readb(azx_dev
, SD_CTL
)) & SD_CTL_STREAM_RESET
) &&
900 /* program the stream_tag */
901 azx_sd_writel(azx_dev
, SD_CTL
,
902 (azx_sd_readl(azx_dev
, SD_CTL
) & ~SD_CTL_STREAM_TAG_MASK
) |
903 (azx_dev
->stream_tag
<< SD_CTL_STREAM_TAG_SHIFT
));
905 /* program the length of samples in cyclic buffer */
906 azx_sd_writel(azx_dev
, SD_CBL
, azx_dev
->bufsize
);
908 /* program the stream format */
909 /* this value needs to be the same as the one programmed */
910 azx_sd_writew(azx_dev
, SD_FORMAT
, azx_dev
->format_val
);
912 /* program the stream LVI (last valid index) of the BDL */
913 azx_sd_writew(azx_dev
, SD_LVI
, azx_dev
->frags
- 1);
915 /* program the BDL address */
916 /* lower BDL address */
917 azx_sd_writel(azx_dev
, SD_BDLPL
, (u32
)azx_dev
->bdl_addr
);
918 /* upper BDL address */
919 azx_sd_writel(azx_dev
, SD_BDLPU
, upper_32bit(azx_dev
->bdl_addr
));
921 /* enable the position buffer */
922 if (! (azx_readl(chip
, DPLBASE
) & ICH6_DPLBASE_ENABLE
))
923 azx_writel(chip
, DPLBASE
, (u32
)chip
->posbuf
.addr
| ICH6_DPLBASE_ENABLE
);
925 /* set the interrupt enable bits in the descriptor control register */
926 azx_sd_writel(azx_dev
, SD_CTL
, azx_sd_readl(azx_dev
, SD_CTL
) | SD_INT_MASK
);
933 * Codec initialization
936 static int __devinit
azx_codec_create(struct azx
*chip
, const char *model
)
938 struct hda_bus_template bus_temp
;
941 memset(&bus_temp
, 0, sizeof(bus_temp
));
942 bus_temp
.private_data
= chip
;
943 bus_temp
.modelname
= model
;
944 bus_temp
.pci
= chip
->pci
;
945 bus_temp
.ops
.command
= azx_send_cmd
;
946 bus_temp
.ops
.get_response
= azx_get_response
;
948 if ((err
= snd_hda_bus_new(chip
->card
, &bus_temp
, &chip
->bus
)) < 0)
952 for (c
= 0; c
< AZX_MAX_CODECS
; c
++) {
953 if ((chip
->codec_mask
& (1 << c
)) & probe_mask
) {
954 err
= snd_hda_codec_new(chip
->bus
, c
, NULL
);
961 snd_printk(KERN_ERR SFX
"no codecs initialized\n");
973 /* assign a stream for the PCM */
974 static inline struct azx_dev
*azx_assign_device(struct azx
*chip
, int stream
)
977 if (stream
== SNDRV_PCM_STREAM_PLAYBACK
) {
978 dev
= chip
->playback_index_offset
;
979 nums
= chip
->playback_streams
;
981 dev
= chip
->capture_index_offset
;
982 nums
= chip
->capture_streams
;
984 for (i
= 0; i
< nums
; i
++, dev
++)
985 if (! chip
->azx_dev
[dev
].opened
) {
986 chip
->azx_dev
[dev
].opened
= 1;
987 return &chip
->azx_dev
[dev
];
992 /* release the assigned stream */
993 static inline void azx_release_device(struct azx_dev
*azx_dev
)
998 static struct snd_pcm_hardware azx_pcm_hw
= {
999 .info
= (SNDRV_PCM_INFO_MMAP
| SNDRV_PCM_INFO_INTERLEAVED
|
1000 SNDRV_PCM_INFO_BLOCK_TRANSFER
|
1001 SNDRV_PCM_INFO_MMAP_VALID
|
1002 SNDRV_PCM_INFO_PAUSE
/*|*/
1003 /*SNDRV_PCM_INFO_RESUME*/),
1004 .formats
= SNDRV_PCM_FMTBIT_S16_LE
,
1005 .rates
= SNDRV_PCM_RATE_48000
,
1010 .buffer_bytes_max
= AZX_MAX_BUF_SIZE
,
1011 .period_bytes_min
= 128,
1012 .period_bytes_max
= AZX_MAX_BUF_SIZE
/ 2,
1014 .periods_max
= AZX_MAX_FRAG
,
1020 struct hda_codec
*codec
;
1021 struct hda_pcm_stream
*hinfo
[2];
1024 static int azx_pcm_open(struct snd_pcm_substream
*substream
)
1026 struct azx_pcm
*apcm
= snd_pcm_substream_chip(substream
);
1027 struct hda_pcm_stream
*hinfo
= apcm
->hinfo
[substream
->stream
];
1028 struct azx
*chip
= apcm
->chip
;
1029 struct azx_dev
*azx_dev
;
1030 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
1031 unsigned long flags
;
1034 mutex_lock(&chip
->open_mutex
);
1035 azx_dev
= azx_assign_device(chip
, substream
->stream
);
1036 if (azx_dev
== NULL
) {
1037 mutex_unlock(&chip
->open_mutex
);
1040 runtime
->hw
= azx_pcm_hw
;
1041 runtime
->hw
.channels_min
= hinfo
->channels_min
;
1042 runtime
->hw
.channels_max
= hinfo
->channels_max
;
1043 runtime
->hw
.formats
= hinfo
->formats
;
1044 runtime
->hw
.rates
= hinfo
->rates
;
1045 snd_pcm_limit_hw_rates(runtime
);
1046 snd_pcm_hw_constraint_integer(runtime
, SNDRV_PCM_HW_PARAM_PERIODS
);
1047 if ((err
= hinfo
->ops
.open(hinfo
, apcm
->codec
, substream
)) < 0) {
1048 azx_release_device(azx_dev
);
1049 mutex_unlock(&chip
->open_mutex
);
1052 spin_lock_irqsave(&chip
->reg_lock
, flags
);
1053 azx_dev
->substream
= substream
;
1054 azx_dev
->running
= 0;
1055 spin_unlock_irqrestore(&chip
->reg_lock
, flags
);
1057 runtime
->private_data
= azx_dev
;
1058 mutex_unlock(&chip
->open_mutex
);
1062 static int azx_pcm_close(struct snd_pcm_substream
*substream
)
1064 struct azx_pcm
*apcm
= snd_pcm_substream_chip(substream
);
1065 struct hda_pcm_stream
*hinfo
= apcm
->hinfo
[substream
->stream
];
1066 struct azx
*chip
= apcm
->chip
;
1067 struct azx_dev
*azx_dev
= get_azx_dev(substream
);
1068 unsigned long flags
;
1070 mutex_lock(&chip
->open_mutex
);
1071 spin_lock_irqsave(&chip
->reg_lock
, flags
);
1072 azx_dev
->substream
= NULL
;
1073 azx_dev
->running
= 0;
1074 spin_unlock_irqrestore(&chip
->reg_lock
, flags
);
1075 azx_release_device(azx_dev
);
1076 hinfo
->ops
.close(hinfo
, apcm
->codec
, substream
);
1077 mutex_unlock(&chip
->open_mutex
);
1081 static int azx_pcm_hw_params(struct snd_pcm_substream
*substream
, struct snd_pcm_hw_params
*hw_params
)
1083 return snd_pcm_lib_malloc_pages(substream
, params_buffer_bytes(hw_params
));
1086 static int azx_pcm_hw_free(struct snd_pcm_substream
*substream
)
1088 struct azx_pcm
*apcm
= snd_pcm_substream_chip(substream
);
1089 struct azx_dev
*azx_dev
= get_azx_dev(substream
);
1090 struct hda_pcm_stream
*hinfo
= apcm
->hinfo
[substream
->stream
];
1092 /* reset BDL address */
1093 azx_sd_writel(azx_dev
, SD_BDLPL
, 0);
1094 azx_sd_writel(azx_dev
, SD_BDLPU
, 0);
1095 azx_sd_writel(azx_dev
, SD_CTL
, 0);
1097 hinfo
->ops
.cleanup(hinfo
, apcm
->codec
, substream
);
1099 return snd_pcm_lib_free_pages(substream
);
1102 static int azx_pcm_prepare(struct snd_pcm_substream
*substream
)
1104 struct azx_pcm
*apcm
= snd_pcm_substream_chip(substream
);
1105 struct azx
*chip
= apcm
->chip
;
1106 struct azx_dev
*azx_dev
= get_azx_dev(substream
);
1107 struct hda_pcm_stream
*hinfo
= apcm
->hinfo
[substream
->stream
];
1108 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
1110 azx_dev
->bufsize
= snd_pcm_lib_buffer_bytes(substream
);
1111 azx_dev
->fragsize
= snd_pcm_lib_period_bytes(substream
);
1112 azx_dev
->frags
= azx_dev
->bufsize
/ azx_dev
->fragsize
;
1113 azx_dev
->format_val
= snd_hda_calc_stream_format(runtime
->rate
,
1117 if (! azx_dev
->format_val
) {
1118 snd_printk(KERN_ERR SFX
"invalid format_val, rate=%d, ch=%d, format=%d\n",
1119 runtime
->rate
, runtime
->channels
, runtime
->format
);
1123 snd_printdd("azx_pcm_prepare: bufsize=0x%x, fragsize=0x%x, format=0x%x\n",
1124 azx_dev
->bufsize
, azx_dev
->fragsize
, azx_dev
->format_val
);
1125 azx_setup_periods(azx_dev
);
1126 azx_setup_controller(chip
, azx_dev
);
1127 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
)
1128 azx_dev
->fifo_size
= azx_sd_readw(azx_dev
, SD_FIFOSIZE
) + 1;
1130 azx_dev
->fifo_size
= 0;
1132 return hinfo
->ops
.prepare(hinfo
, apcm
->codec
, azx_dev
->stream_tag
,
1133 azx_dev
->format_val
, substream
);
1136 static int azx_pcm_trigger(struct snd_pcm_substream
*substream
, int cmd
)
1138 struct azx_pcm
*apcm
= snd_pcm_substream_chip(substream
);
1139 struct azx_dev
*azx_dev
= get_azx_dev(substream
);
1140 struct azx
*chip
= apcm
->chip
;
1143 spin_lock(&chip
->reg_lock
);
1145 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE
:
1146 case SNDRV_PCM_TRIGGER_RESUME
:
1147 case SNDRV_PCM_TRIGGER_START
:
1148 azx_stream_start(chip
, azx_dev
);
1149 azx_dev
->running
= 1;
1151 case SNDRV_PCM_TRIGGER_PAUSE_PUSH
:
1152 case SNDRV_PCM_TRIGGER_SUSPEND
:
1153 case SNDRV_PCM_TRIGGER_STOP
:
1154 azx_stream_stop(chip
, azx_dev
);
1155 azx_dev
->running
= 0;
1160 spin_unlock(&chip
->reg_lock
);
1161 if (cmd
== SNDRV_PCM_TRIGGER_PAUSE_PUSH
||
1162 cmd
== SNDRV_PCM_TRIGGER_SUSPEND
||
1163 cmd
== SNDRV_PCM_TRIGGER_STOP
) {
1165 while (azx_sd_readb(azx_dev
, SD_CTL
) & SD_CTL_DMA_START
&& --timeout
)
1171 static snd_pcm_uframes_t
azx_pcm_pointer(struct snd_pcm_substream
*substream
)
1173 struct azx_pcm
*apcm
= snd_pcm_substream_chip(substream
);
1174 struct azx
*chip
= apcm
->chip
;
1175 struct azx_dev
*azx_dev
= get_azx_dev(substream
);
1178 if (chip
->position_fix
== POS_FIX_POSBUF
||
1179 chip
->position_fix
== POS_FIX_AUTO
) {
1180 /* use the position buffer */
1181 pos
= *azx_dev
->posbuf
;
1182 if (chip
->position_fix
== POS_FIX_AUTO
&&
1183 azx_dev
->period_intr
== 1 && ! pos
) {
1185 "hda-intel: Invalid position buffer, "
1186 "using LPIB read method instead.\n");
1187 chip
->position_fix
= POS_FIX_NONE
;
1193 pos
= azx_sd_readl(azx_dev
, SD_LPIB
);
1194 if (chip
->position_fix
== POS_FIX_FIFO
)
1195 pos
+= azx_dev
->fifo_size
;
1197 if (pos
>= azx_dev
->bufsize
)
1199 return bytes_to_frames(substream
->runtime
, pos
);
1202 static struct snd_pcm_ops azx_pcm_ops
= {
1203 .open
= azx_pcm_open
,
1204 .close
= azx_pcm_close
,
1205 .ioctl
= snd_pcm_lib_ioctl
,
1206 .hw_params
= azx_pcm_hw_params
,
1207 .hw_free
= azx_pcm_hw_free
,
1208 .prepare
= azx_pcm_prepare
,
1209 .trigger
= azx_pcm_trigger
,
1210 .pointer
= azx_pcm_pointer
,
1213 static void azx_pcm_free(struct snd_pcm
*pcm
)
1215 kfree(pcm
->private_data
);
1218 static int __devinit
create_codec_pcm(struct azx
*chip
, struct hda_codec
*codec
,
1219 struct hda_pcm
*cpcm
, int pcm_dev
)
1222 struct snd_pcm
*pcm
;
1223 struct azx_pcm
*apcm
;
1225 snd_assert(cpcm
->stream
[0].substreams
|| cpcm
->stream
[1].substreams
, return -EINVAL
);
1226 snd_assert(cpcm
->name
, return -EINVAL
);
1228 err
= snd_pcm_new(chip
->card
, cpcm
->name
, pcm_dev
,
1229 cpcm
->stream
[0].substreams
, cpcm
->stream
[1].substreams
,
1233 strcpy(pcm
->name
, cpcm
->name
);
1234 apcm
= kmalloc(sizeof(*apcm
), GFP_KERNEL
);
1238 apcm
->codec
= codec
;
1239 apcm
->hinfo
[0] = &cpcm
->stream
[0];
1240 apcm
->hinfo
[1] = &cpcm
->stream
[1];
1241 pcm
->private_data
= apcm
;
1242 pcm
->private_free
= azx_pcm_free
;
1243 if (cpcm
->stream
[0].substreams
)
1244 snd_pcm_set_ops(pcm
, SNDRV_PCM_STREAM_PLAYBACK
, &azx_pcm_ops
);
1245 if (cpcm
->stream
[1].substreams
)
1246 snd_pcm_set_ops(pcm
, SNDRV_PCM_STREAM_CAPTURE
, &azx_pcm_ops
);
1247 snd_pcm_lib_preallocate_pages_for_all(pcm
, SNDRV_DMA_TYPE_DEV
,
1248 snd_dma_pci_data(chip
->pci
),
1249 1024 * 64, 1024 * 128);
1250 chip
->pcm
[pcm_dev
] = pcm
;
1251 chip
->pcm_devs
= pcm_dev
+ 1;
1256 static int __devinit
azx_pcm_create(struct azx
*chip
)
1258 struct list_head
*p
;
1259 struct hda_codec
*codec
;
1263 if ((err
= snd_hda_build_pcms(chip
->bus
)) < 0)
1266 /* create audio PCMs */
1268 list_for_each(p
, &chip
->bus
->codec_list
) {
1269 codec
= list_entry(p
, struct hda_codec
, list
);
1270 for (c
= 0; c
< codec
->num_pcms
; c
++) {
1271 if (codec
->pcm_info
[c
].is_modem
)
1272 continue; /* create later */
1273 if (pcm_dev
>= AZX_MAX_AUDIO_PCMS
) {
1274 snd_printk(KERN_ERR SFX
"Too many audio PCMs\n");
1277 err
= create_codec_pcm(chip
, codec
, &codec
->pcm_info
[c
], pcm_dev
);
1284 /* create modem PCMs */
1285 pcm_dev
= AZX_MAX_AUDIO_PCMS
;
1286 list_for_each(p
, &chip
->bus
->codec_list
) {
1287 codec
= list_entry(p
, struct hda_codec
, list
);
1288 for (c
= 0; c
< codec
->num_pcms
; c
++) {
1289 if (! codec
->pcm_info
[c
].is_modem
)
1290 continue; /* already created */
1291 if (pcm_dev
>= AZX_MAX_PCMS
) {
1292 snd_printk(KERN_ERR SFX
"Too many modem PCMs\n");
1295 err
= create_codec_pcm(chip
, codec
, &codec
->pcm_info
[c
], pcm_dev
);
1298 chip
->pcm
[pcm_dev
]->dev_class
= SNDRV_PCM_CLASS_MODEM
;
1306 * mixer creation - all stuff is implemented in hda module
1308 static int __devinit
azx_mixer_create(struct azx
*chip
)
1310 return snd_hda_build_controls(chip
->bus
);
1315 * initialize SD streams
1317 static int __devinit
azx_init_stream(struct azx
*chip
)
1321 /* initialize each stream (aka device)
1322 * assign the starting bdl address to each stream (device) and initialize
1324 for (i
= 0; i
< chip
->num_streams
; i
++) {
1325 unsigned int off
= sizeof(u32
) * (i
* AZX_MAX_FRAG
* 4);
1326 struct azx_dev
*azx_dev
= &chip
->azx_dev
[i
];
1327 azx_dev
->bdl
= (u32
*)(chip
->bdl
.area
+ off
);
1328 azx_dev
->bdl_addr
= chip
->bdl
.addr
+ off
;
1329 azx_dev
->posbuf
= (volatile u32
*)(chip
->posbuf
.area
+ i
* 8);
1330 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
1331 azx_dev
->sd_addr
= chip
->remap_addr
+ (0x20 * i
+ 0x80);
1332 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
1333 azx_dev
->sd_int_sta_mask
= 1 << i
;
1334 /* stream tag: must be non-zero and unique */
1336 azx_dev
->stream_tag
= i
+ 1;
1347 static int azx_suspend(struct pci_dev
*pci
, pm_message_t state
)
1349 struct snd_card
*card
= pci_get_drvdata(pci
);
1350 struct azx
*chip
= card
->private_data
;
1353 snd_power_change_state(card
, SNDRV_CTL_POWER_D3hot
);
1354 for (i
= 0; i
< chip
->pcm_devs
; i
++)
1355 snd_pcm_suspend_all(chip
->pcm
[i
]);
1356 snd_hda_suspend(chip
->bus
, state
);
1357 azx_free_cmd_io(chip
);
1358 pci_disable_device(pci
);
1359 pci_save_state(pci
);
1363 static int azx_resume(struct pci_dev
*pci
)
1365 struct snd_card
*card
= pci_get_drvdata(pci
);
1366 struct azx
*chip
= card
->private_data
;
1368 pci_restore_state(pci
);
1369 pci_enable_device(pci
);
1370 pci_set_master(pci
);
1371 azx_init_chip(chip
);
1372 snd_hda_resume(chip
->bus
);
1373 snd_power_change_state(card
, SNDRV_CTL_POWER_D0
);
1376 #endif /* CONFIG_PM */
1382 static int azx_free(struct azx
*chip
)
1384 if (chip
->initialized
) {
1387 for (i
= 0; i
< chip
->num_streams
; i
++)
1388 azx_stream_stop(chip
, &chip
->azx_dev
[i
]);
1390 /* disable interrupts */
1391 azx_int_disable(chip
);
1392 azx_int_clear(chip
);
1394 /* disable CORB/RIRB */
1395 azx_free_cmd_io(chip
);
1397 /* disable position buffer */
1398 azx_writel(chip
, DPLBASE
, 0);
1399 azx_writel(chip
, DPUBASE
, 0);
1401 /* wait a little for interrupts to finish */
1406 free_irq(chip
->irq
, (void*)chip
);
1407 if (chip
->remap_addr
)
1408 iounmap(chip
->remap_addr
);
1411 snd_dma_free_pages(&chip
->bdl
);
1413 snd_dma_free_pages(&chip
->rb
);
1414 if (chip
->posbuf
.area
)
1415 snd_dma_free_pages(&chip
->posbuf
);
1416 pci_release_regions(chip
->pci
);
1417 pci_disable_device(chip
->pci
);
1418 kfree(chip
->azx_dev
);
1424 static int azx_dev_free(struct snd_device
*device
)
1426 return azx_free(device
->device_data
);
1432 static int __devinit
azx_create(struct snd_card
*card
, struct pci_dev
*pci
,
1438 static struct snd_device_ops ops
= {
1439 .dev_free
= azx_dev_free
,
1444 if ((err
= pci_enable_device(pci
)) < 0)
1447 chip
= kzalloc(sizeof(*chip
), GFP_KERNEL
);
1450 snd_printk(KERN_ERR SFX
"cannot allocate chip\n");
1451 pci_disable_device(pci
);
1455 spin_lock_init(&chip
->reg_lock
);
1456 mutex_init(&chip
->open_mutex
);
1460 chip
->driver_type
= driver_type
;
1462 chip
->position_fix
= position_fix
;
1463 chip
->single_cmd
= single_cmd
;
1465 #if BITS_PER_LONG != 64
1466 /* Fix up base address on ULI M5461 */
1467 if (chip
->driver_type
== AZX_DRIVER_ULI
) {
1469 pci_read_config_word(pci
, 0x40, &tmp3
);
1470 pci_write_config_word(pci
, 0x40, tmp3
| 0x10);
1471 pci_write_config_dword(pci
, PCI_BASE_ADDRESS_1
, 0);
1475 if ((err
= pci_request_regions(pci
, "ICH HD audio")) < 0) {
1477 pci_disable_device(pci
);
1481 chip
->addr
= pci_resource_start(pci
,0);
1482 chip
->remap_addr
= ioremap_nocache(chip
->addr
, pci_resource_len(pci
,0));
1483 if (chip
->remap_addr
== NULL
) {
1484 snd_printk(KERN_ERR SFX
"ioremap error\n");
1489 if (request_irq(pci
->irq
, azx_interrupt
, IRQF_DISABLED
|IRQF_SHARED
,
1490 "HDA Intel", (void*)chip
)) {
1491 snd_printk(KERN_ERR SFX
"unable to grab IRQ %d\n", pci
->irq
);
1495 chip
->irq
= pci
->irq
;
1497 pci_set_master(pci
);
1498 synchronize_irq(chip
->irq
);
1500 switch (chip
->driver_type
) {
1501 case AZX_DRIVER_ULI
:
1502 chip
->playback_streams
= ULI_NUM_PLAYBACK
;
1503 chip
->capture_streams
= ULI_NUM_CAPTURE
;
1504 chip
->playback_index_offset
= ULI_PLAYBACK_INDEX
;
1505 chip
->capture_index_offset
= ULI_CAPTURE_INDEX
;
1507 case AZX_DRIVER_ATIHDMI
:
1508 chip
->playback_streams
= ATIHDMI_NUM_PLAYBACK
;
1509 chip
->capture_streams
= ATIHDMI_NUM_CAPTURE
;
1510 chip
->playback_index_offset
= ATIHDMI_PLAYBACK_INDEX
;
1511 chip
->capture_index_offset
= ATIHDMI_CAPTURE_INDEX
;
1514 chip
->playback_streams
= ICH6_NUM_PLAYBACK
;
1515 chip
->capture_streams
= ICH6_NUM_CAPTURE
;
1516 chip
->playback_index_offset
= ICH6_PLAYBACK_INDEX
;
1517 chip
->capture_index_offset
= ICH6_CAPTURE_INDEX
;
1520 chip
->num_streams
= chip
->playback_streams
+ chip
->capture_streams
;
1521 chip
->azx_dev
= kcalloc(chip
->num_streams
, sizeof(*chip
->azx_dev
), GFP_KERNEL
);
1522 if (! chip
->azx_dev
) {
1523 snd_printk(KERN_ERR
"cannot malloc azx_dev\n");
1527 /* allocate memory for the BDL for each stream */
1528 if ((err
= snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV
, snd_dma_pci_data(chip
->pci
),
1529 BDL_SIZE
, &chip
->bdl
)) < 0) {
1530 snd_printk(KERN_ERR SFX
"cannot allocate BDL\n");
1533 /* allocate memory for the position buffer */
1534 if ((err
= snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV
, snd_dma_pci_data(chip
->pci
),
1535 chip
->num_streams
* 8, &chip
->posbuf
)) < 0) {
1536 snd_printk(KERN_ERR SFX
"cannot allocate posbuf\n");
1539 /* allocate CORB/RIRB */
1540 if (! chip
->single_cmd
)
1541 if ((err
= azx_alloc_cmd_io(chip
)) < 0)
1544 /* initialize streams */
1545 azx_init_stream(chip
);
1547 /* initialize chip */
1548 azx_init_chip(chip
);
1550 chip
->initialized
= 1;
1552 /* codec detection */
1553 if (! chip
->codec_mask
) {
1554 snd_printk(KERN_ERR SFX
"no codecs found!\n");
1559 if ((err
= snd_device_new(card
, SNDRV_DEV_LOWLEVEL
, chip
, &ops
)) <0) {
1560 snd_printk(KERN_ERR SFX
"Error creating device [card]!\n");
1564 strcpy(card
->driver
, "HDA-Intel");
1565 strcpy(card
->shortname
, driver_short_names
[chip
->driver_type
]);
1566 sprintf(card
->longname
, "%s at 0x%lx irq %i", card
->shortname
, chip
->addr
, chip
->irq
);
1576 static int __devinit
azx_probe(struct pci_dev
*pci
, const struct pci_device_id
*pci_id
)
1578 struct snd_card
*card
;
1582 card
= snd_card_new(index
, id
, THIS_MODULE
, 0);
1584 snd_printk(KERN_ERR SFX
"Error creating card!\n");
1588 if ((err
= azx_create(card
, pci
, pci_id
->driver_data
,
1590 snd_card_free(card
);
1593 card
->private_data
= chip
;
1595 /* create codec instances */
1596 if ((err
= azx_codec_create(chip
, model
)) < 0) {
1597 snd_card_free(card
);
1601 /* create PCM streams */
1602 if ((err
= azx_pcm_create(chip
)) < 0) {
1603 snd_card_free(card
);
1607 /* create mixer controls */
1608 if ((err
= azx_mixer_create(chip
)) < 0) {
1609 snd_card_free(card
);
1613 snd_card_set_dev(card
, &pci
->dev
);
1615 if ((err
= snd_card_register(card
)) < 0) {
1616 snd_card_free(card
);
1620 pci_set_drvdata(pci
, card
);
1625 static void __devexit
azx_remove(struct pci_dev
*pci
)
1627 snd_card_free(pci_get_drvdata(pci
));
1628 pci_set_drvdata(pci
, NULL
);
1632 static struct pci_device_id azx_ids
[] __devinitdata
= {
1633 { 0x8086, 0x2668, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, AZX_DRIVER_ICH
}, /* ICH6 */
1634 { 0x8086, 0x27d8, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, AZX_DRIVER_ICH
}, /* ICH7 */
1635 { 0x8086, 0x269a, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, AZX_DRIVER_ICH
}, /* ESB2 */
1636 { 0x8086, 0x284b, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, AZX_DRIVER_ICH
}, /* ICH8 */
1637 { 0x1002, 0x437b, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, AZX_DRIVER_ATI
}, /* ATI SB450 */
1638 { 0x1002, 0x4383, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, AZX_DRIVER_ATI
}, /* ATI SB600 */
1639 { 0x1002, 0x793b, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, AZX_DRIVER_ATIHDMI
}, /* ATI RS600 HDMI */
1640 { 0x1106, 0x3288, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, AZX_DRIVER_VIA
}, /* VIA VT8251/VT8237A */
1641 { 0x1039, 0x7502, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, AZX_DRIVER_SIS
}, /* SIS966 */
1642 { 0x10b9, 0x5461, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, AZX_DRIVER_ULI
}, /* ULI M5461 */
1643 { 0x10de, 0x026c, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, AZX_DRIVER_NVIDIA
}, /* NVIDIA 026c */
1644 { 0x10de, 0x0371, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, AZX_DRIVER_NVIDIA
}, /* NVIDIA 0371 */
1647 MODULE_DEVICE_TABLE(pci
, azx_ids
);
1649 /* pci_driver definition */
1650 static struct pci_driver driver
= {
1651 .name
= "HDA Intel",
1652 .id_table
= azx_ids
,
1654 .remove
= __devexit_p(azx_remove
),
1656 .suspend
= azx_suspend
,
1657 .resume
= azx_resume
,
1661 static int __init
alsa_card_azx_init(void)
1663 return pci_register_driver(&driver
);
1666 static void __exit
alsa_card_azx_exit(void)
1668 pci_unregister_driver(&driver
);
1671 module_init(alsa_card_azx_init
)
1672 module_exit(alsa_card_azx_exit
)