1 #ifndef _ASM_GENERIC_PGTABLE_H
2 #define _ASM_GENERIC_PGTABLE_H
6 #ifndef __HAVE_ARCH_PTEP_ESTABLISH
8 * Establish a new mapping:
10 * - update the page tables
11 * - inform the TLB about the new one
13 * We hold the mm semaphore for reading, and the pte lock.
15 * Note: the old pte is known to not be writable, so we don't need to
16 * worry about dirty bits etc getting lost.
18 #define ptep_establish(__vma, __address, __ptep, __entry) \
20 set_pte_at((__vma)->vm_mm, (__address), __ptep, __entry); \
21 flush_tlb_page(__vma, __address); \
25 #ifndef __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
27 * Largely same as above, but only sets the access flags (dirty,
28 * accessed, and writable). Furthermore, we know it always gets set
29 * to a "more permissive" setting, which allows most architectures
30 * to optimize this. We return whether the PTE actually changed, which
31 * in turn instructs the caller to do things like update__mmu_cache.
32 * This used to be done in the caller, but sparc needs minor faults to
33 * force that call on sun4c so we changed this macro slightly
35 #define ptep_set_access_flags(__vma, __address, __ptep, __entry, __dirty) \
37 int __changed = !pte_same(*(__ptep), __entry); \
39 set_pte_at((__vma)->vm_mm, (__address), __ptep, __entry); \
40 flush_tlb_page(__vma, __address); \
46 #ifndef __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
47 #define ptep_test_and_clear_young(__vma, __address, __ptep) \
49 pte_t __pte = *(__ptep); \
51 if (!pte_young(__pte)) \
54 set_pte_at((__vma)->vm_mm, (__address), \
55 (__ptep), pte_mkold(__pte)); \
60 #ifndef __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH
61 #define ptep_clear_flush_young(__vma, __address, __ptep) \
64 __young = ptep_test_and_clear_young(__vma, __address, __ptep); \
66 flush_tlb_page(__vma, __address); \
71 #ifndef __HAVE_ARCH_PTEP_TEST_AND_CLEAR_DIRTY
72 #define ptep_test_and_clear_dirty(__vma, __address, __ptep) \
74 pte_t __pte = *__ptep; \
76 if (!pte_dirty(__pte)) \
79 set_pte_at((__vma)->vm_mm, (__address), (__ptep), \
80 pte_mkclean(__pte)); \
85 #ifndef __HAVE_ARCH_PTEP_CLEAR_DIRTY_FLUSH
86 #define ptep_clear_flush_dirty(__vma, __address, __ptep) \
89 __dirty = ptep_test_and_clear_dirty(__vma, __address, __ptep); \
91 flush_tlb_page(__vma, __address); \
96 #ifndef __HAVE_ARCH_PTEP_GET_AND_CLEAR
97 #define ptep_get_and_clear(__mm, __address, __ptep) \
99 pte_t __pte = *(__ptep); \
100 pte_clear((__mm), (__address), (__ptep)); \
105 #ifndef __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL
106 #define ptep_get_and_clear_full(__mm, __address, __ptep, __full) \
109 __pte = ptep_get_and_clear((__mm), (__address), (__ptep)); \
115 * Some architectures may be able to avoid expensive synchronization
116 * primitives when modifications are made to PTE's which are already
117 * not present, or in the process of an address space destruction.
119 #ifndef __HAVE_ARCH_PTE_CLEAR_NOT_PRESENT_FULL
120 #define pte_clear_not_present_full(__mm, __address, __ptep, __full) \
122 pte_clear((__mm), (__address), (__ptep)); \
126 #ifndef __HAVE_ARCH_PTEP_CLEAR_FLUSH
127 #define ptep_clear_flush(__vma, __address, __ptep) \
130 __pte = ptep_get_and_clear((__vma)->vm_mm, __address, __ptep); \
131 flush_tlb_page(__vma, __address); \
136 #ifndef __HAVE_ARCH_PTEP_SET_WRPROTECT
138 static inline void ptep_set_wrprotect(struct mm_struct
*mm
, unsigned long address
, pte_t
*ptep
)
140 pte_t old_pte
= *ptep
;
141 set_pte_at(mm
, address
, ptep
, pte_wrprotect(old_pte
));
145 #ifndef __HAVE_ARCH_PTE_SAME
146 #define pte_same(A,B) (pte_val(A) == pte_val(B))
149 #ifndef __HAVE_ARCH_PAGE_TEST_DIRTY
150 #define page_test_dirty(page) (0)
153 #ifndef __HAVE_ARCH_PAGE_CLEAR_DIRTY
154 #define page_clear_dirty(page) do { } while (0)
157 #ifndef __HAVE_ARCH_PAGE_TEST_DIRTY
158 #define pte_maybe_dirty(pte) pte_dirty(pte)
160 #define pte_maybe_dirty(pte) (1)
163 #ifndef __HAVE_ARCH_PAGE_TEST_AND_CLEAR_YOUNG
164 #define page_test_and_clear_young(page) (0)
167 #ifndef __HAVE_ARCH_PGD_OFFSET_GATE
168 #define pgd_offset_gate(mm, addr) pgd_offset(mm, addr)
171 #ifndef __HAVE_ARCH_LAZY_MMU_PROT_UPDATE
172 #define lazy_mmu_prot_update(pte) do { } while (0)
175 #ifndef __HAVE_ARCH_MOVE_PTE
176 #define move_pte(pte, prot, old_addr, new_addr) (pte)
180 * A facility to provide lazy MMU batching. This allows PTE updates and
181 * page invalidations to be delayed until a call to leave lazy MMU mode
182 * is issued. Some architectures may benefit from doing this, and it is
183 * beneficial for both shadow and direct mode hypervisors, which may batch
184 * the PTE updates which happen during this window. Note that using this
185 * interface requires that read hazards be removed from the code. A read
186 * hazard could result in the direct mode hypervisor case, since the actual
187 * write to the page tables may not yet have taken place, so reads though
188 * a raw PTE pointer after it has been modified are not guaranteed to be
189 * up to date. This mode can only be entered and left under the protection of
190 * the page table locks for all page tables which may be modified. In the UP
191 * case, this is required so that preemption is disabled, and in the SMP case,
192 * it must synchronize the delayed page table writes properly on other CPUs.
194 #ifndef __HAVE_ARCH_ENTER_LAZY_MMU_MODE
195 #define arch_enter_lazy_mmu_mode() do {} while (0)
196 #define arch_leave_lazy_mmu_mode() do {} while (0)
197 #define arch_flush_lazy_mmu_mode() do {} while (0)
201 * A facility to provide batching of the reload of page tables with the
202 * actual context switch code for paravirtualized guests. By convention,
203 * only one of the lazy modes (CPU, MMU) should be active at any given
204 * time, entry should never be nested, and entry and exits should always
205 * be paired. This is for sanity of maintaining and reasoning about the
208 #ifndef __HAVE_ARCH_ENTER_LAZY_CPU_MODE
209 #define arch_enter_lazy_cpu_mode() do {} while (0)
210 #define arch_leave_lazy_cpu_mode() do {} while (0)
211 #define arch_flush_lazy_cpu_mode() do {} while (0)
215 * When walking page tables, get the address of the next boundary,
216 * or the end address of the range if that comes earlier. Although no
217 * vma end wraps to 0, rounded up __boundary may wrap to 0 throughout.
220 #define pgd_addr_end(addr, end) \
221 ({ unsigned long __boundary = ((addr) + PGDIR_SIZE) & PGDIR_MASK; \
222 (__boundary - 1 < (end) - 1)? __boundary: (end); \
226 #define pud_addr_end(addr, end) \
227 ({ unsigned long __boundary = ((addr) + PUD_SIZE) & PUD_MASK; \
228 (__boundary - 1 < (end) - 1)? __boundary: (end); \
233 #define pmd_addr_end(addr, end) \
234 ({ unsigned long __boundary = ((addr) + PMD_SIZE) & PMD_MASK; \
235 (__boundary - 1 < (end) - 1)? __boundary: (end); \
240 * When walking page tables, we usually want to skip any p?d_none entries;
241 * and any p?d_bad entries - reporting the error before resetting to none.
242 * Do the tests inline, but report and clear the bad entry in mm/memory.c.
244 void pgd_clear_bad(pgd_t
*);
245 void pud_clear_bad(pud_t
*);
246 void pmd_clear_bad(pmd_t
*);
248 static inline int pgd_none_or_clear_bad(pgd_t
*pgd
)
252 if (unlikely(pgd_bad(*pgd
))) {
259 static inline int pud_none_or_clear_bad(pud_t
*pud
)
263 if (unlikely(pud_bad(*pud
))) {
270 static inline int pmd_none_or_clear_bad(pmd_t
*pmd
)
274 if (unlikely(pmd_bad(*pmd
))) {
280 #endif /* !__ASSEMBLY__ */
282 #endif /* _ASM_GENERIC_PGTABLE_H */