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agp: balance ioremap checks
[usb.git] / drivers / char / agp / intel-agp.c
blob2c9ca2c64628dd178ca6ae489e5d129e5139f119
1 /*
2 * Intel AGPGART routines.
3 */
4
5 #include <linux/module.h>
6 #include <linux/pci.h>
7 #include <linux/init.h>
8 #include <linux/kernel.h>
9 #include <linux/pagemap.h>
10 #include <linux/agp_backend.h>
11 #include "agp.h"
12
13 #define PCI_DEVICE_ID_INTEL_82946GZ_HB 0x2970
14 #define PCI_DEVICE_ID_INTEL_82946GZ_IG 0x2972
15 #define PCI_DEVICE_ID_INTEL_82965G_1_HB 0x2980
16 #define PCI_DEVICE_ID_INTEL_82965G_1_IG 0x2982
17 #define PCI_DEVICE_ID_INTEL_82965Q_HB 0x2990
18 #define PCI_DEVICE_ID_INTEL_82965Q_IG 0x2992
19 #define PCI_DEVICE_ID_INTEL_82965G_HB 0x29A0
20 #define PCI_DEVICE_ID_INTEL_82965G_IG 0x29A2
21 #define PCI_DEVICE_ID_INTEL_82965GM_HB 0x2A00
22 #define PCI_DEVICE_ID_INTEL_82965GM_IG 0x2A02
23 #define PCI_DEVICE_ID_INTEL_82965GME_HB 0x2A10
24 #define PCI_DEVICE_ID_INTEL_82965GME_IG 0x2A12
25 #define PCI_DEVICE_ID_INTEL_82945GME_HB 0x27AC
26 #define PCI_DEVICE_ID_INTEL_82945GME_IG 0x27AE
27 #define PCI_DEVICE_ID_INTEL_G33_HB 0x29C0
28 #define PCI_DEVICE_ID_INTEL_G33_IG 0x29C2
29 #define PCI_DEVICE_ID_INTEL_Q35_HB 0x29B0
30 #define PCI_DEVICE_ID_INTEL_Q35_IG 0x29B2
31 #define PCI_DEVICE_ID_INTEL_Q33_HB 0x29D0
32 #define PCI_DEVICE_ID_INTEL_Q33_IG 0x29D2
33
34 #define IS_I965 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82946GZ_HB || \
35 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965G_1_HB || \
36 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965Q_HB || \
37 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965G_HB || \
38 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GM_HB || \
39 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GME_HB)
40
41 #define IS_G33 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G33_HB || \
42 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q35_HB || \
43 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q33_HB)
44
45 extern int agp_memory_reserved;
46
47
48 /* Intel 815 register */
49 #define INTEL_815_APCONT 0x51
50 #define INTEL_815_ATTBASE_MASK ~0x1FFFFFFF
51
52 /* Intel i820 registers */
53 #define INTEL_I820_RDCR 0x51
54 #define INTEL_I820_ERRSTS 0xc8
55
56 /* Intel i840 registers */
57 #define INTEL_I840_MCHCFG 0x50
58 #define INTEL_I840_ERRSTS 0xc8
59
60 /* Intel i850 registers */
61 #define INTEL_I850_MCHCFG 0x50
62 #define INTEL_I850_ERRSTS 0xc8
63
64 /* intel 915G registers */
65 #define I915_GMADDR 0x18
66 #define I915_MMADDR 0x10
67 #define I915_PTEADDR 0x1C
68 #define I915_GMCH_GMS_STOLEN_48M (0x6 << 4)
69 #define I915_GMCH_GMS_STOLEN_64M (0x7 << 4)
70 #define G33_GMCH_GMS_STOLEN_128M (0x8 << 4)
71 #define G33_GMCH_GMS_STOLEN_256M (0x9 << 4)
72
73 /* Intel 965G registers */
74 #define I965_MSAC 0x62
75
76 /* Intel 7505 registers */
77 #define INTEL_I7505_APSIZE 0x74
78 #define INTEL_I7505_NCAPID 0x60
79 #define INTEL_I7505_NISTAT 0x6c
80 #define INTEL_I7505_ATTBASE 0x78
81 #define INTEL_I7505_ERRSTS 0x42
82 #define INTEL_I7505_AGPCTRL 0x70
83 #define INTEL_I7505_MCHCFG 0x50
84
85 static const struct aper_size_info_fixed intel_i810_sizes[] =
86 {
87 {64, 16384, 4},
88 /* The 32M mode still requires a 64k gatt */
89 {32, 8192, 4}
90 };
91
92 #define AGP_DCACHE_MEMORY 1
93 #define AGP_PHYS_MEMORY 2
94 #define INTEL_AGP_CACHED_MEMORY 3
95
96 static struct gatt_mask intel_i810_masks[] =
97 {
98 {.mask = I810_PTE_VALID, .type = 0},
99 {.mask = (I810_PTE_VALID | I810_PTE_LOCAL), .type = AGP_DCACHE_MEMORY},
100 {.mask = I810_PTE_VALID, .type = 0},
101 {.mask = I810_PTE_VALID | I830_PTE_SYSTEM_CACHED,
102 .type = INTEL_AGP_CACHED_MEMORY}
103 };
104
105 static struct _intel_private {
106 struct pci_dev *pcidev; /* device one */
107 u8 __iomem *registers;
108 u32 __iomem *gtt; /* I915G */
109 int num_dcache_entries;
110 /* gtt_entries is the number of gtt entries that are already mapped
111 * to stolen memory. Stolen memory is larger than the memory mapped
112 * through gtt_entries, as it includes some reserved space for the BIOS
113 * popup and for the GTT.
114 */
115 int gtt_entries; /* i830+ */
116 } intel_private;
117
118 static int intel_i810_fetch_size(void)
119 {
120 u32 smram_miscc;
121 struct aper_size_info_fixed *values;
122
123 pci_read_config_dword(agp_bridge->dev, I810_SMRAM_MISCC, &smram_miscc);
124 values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
125
126 if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) {
127 printk(KERN_WARNING PFX "i810 is disabled\n");
128 return 0;
129 }
130 if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) {
131 agp_bridge->previous_size =
132 agp_bridge->current_size = (void *) (values + 1);
133 agp_bridge->aperture_size_idx = 1;
134 return values[1].size;
135 } else {
136 agp_bridge->previous_size =
137 agp_bridge->current_size = (void *) (values);
138 agp_bridge->aperture_size_idx = 0;
139 return values[0].size;
140 }
141
142 return 0;
143 }
144
145 static int intel_i810_configure(void)
146 {
147 struct aper_size_info_fixed *current_size;
148 u32 temp;
149 int i;
150
151 current_size = A_SIZE_FIX(agp_bridge->current_size);
152
153 if (!intel_private.registers) {
154 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp);
155 temp &= 0xfff80000;
156
157 intel_private.registers = ioremap(temp, 128 * 4096);
158 if (!intel_private.registers) {
159 printk(KERN_ERR PFX "Unable to remap memory.\n");
160 return -ENOMEM;
161 }
162 }
163
164 if ((readl(intel_private.registers+I810_DRAM_CTL)
165 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) {
166 /* This will need to be dynamically assigned */
167 printk(KERN_INFO PFX "detected 4MB dedicated video ram.\n");
168 intel_private.num_dcache_entries = 1024;
169 }
170 pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp);
171 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
172 writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
173 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
174
175 if (agp_bridge->driver->needs_scratch_page) {
176 for (i = 0; i < current_size->num_entries; i++) {
177 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
178 readl(intel_private.registers+I810_PTE_BASE+(i*4)); /* PCI posting. */
179 }
180 }
181 global_cache_flush();
182 return 0;
183 }
184
185 static void intel_i810_cleanup(void)
186 {
187 writel(0, intel_private.registers+I810_PGETBL_CTL);
188 readl(intel_private.registers); /* PCI Posting. */
189 iounmap(intel_private.registers);
190 }
191
192 static void intel_i810_tlbflush(struct agp_memory *mem)
193 {
194 return;
195 }
196
197 static void intel_i810_agp_enable(struct agp_bridge_data *bridge, u32 mode)
198 {
199 return;
200 }
201
202 /* Exists to support ARGB cursors */
203 static void *i8xx_alloc_pages(void)
204 {
205 struct page * page;
206
207 page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2);
208 if (page == NULL)
209 return NULL;
210
211 if (change_page_attr(page, 4, PAGE_KERNEL_NOCACHE) < 0) {
212 change_page_attr(page, 4, PAGE_KERNEL);
213 global_flush_tlb();
214 __free_pages(page, 2);
215 return NULL;
216 }
217 global_flush_tlb();
218 get_page(page);
219 atomic_inc(&agp_bridge->current_memory_agp);
220 return page_address(page);
221 }
222
223 static void i8xx_destroy_pages(void *addr)
224 {
225 struct page *page;
226
227 if (addr == NULL)
228 return;
229
230 page = virt_to_page(addr);
231 change_page_attr(page, 4, PAGE_KERNEL);
232 global_flush_tlb();
233 put_page(page);
234 __free_pages(page, 2);
235 atomic_dec(&agp_bridge->current_memory_agp);
236 }
237
238 static int intel_i830_type_to_mask_type(struct agp_bridge_data *bridge,
239 int type)
240 {
241 if (type < AGP_USER_TYPES)
242 return type;
243 else if (type == AGP_USER_CACHED_MEMORY)
244 return INTEL_AGP_CACHED_MEMORY;
245 else
246 return 0;
247 }
248
249 static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start,
250 int type)
251 {
252 int i, j, num_entries;
253 void *temp;
254 int ret = -EINVAL;
255 int mask_type;
256
257 if (mem->page_count == 0)
258 goto out;
259
260 temp = agp_bridge->current_size;
261 num_entries = A_SIZE_FIX(temp)->num_entries;
262
263 if ((pg_start + mem->page_count) > num_entries)
264 goto out_err;
265
266
267 for (j = pg_start; j < (pg_start + mem->page_count); j++) {
268 if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j))) {
269 ret = -EBUSY;
270 goto out_err;
271 }
272 }
273
274 if (type != mem->type)
275 goto out_err;
276
277 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
278
279 switch (mask_type) {
280 case AGP_DCACHE_MEMORY:
281 if (!mem->is_flushed)
282 global_cache_flush();
283 for (i = pg_start; i < (pg_start + mem->page_count); i++) {
284 writel((i*4096)|I810_PTE_LOCAL|I810_PTE_VALID,
285 intel_private.registers+I810_PTE_BASE+(i*4));
286 }
287 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
288 break;
289 case AGP_PHYS_MEMORY:
290 case AGP_NORMAL_MEMORY:
291 if (!mem->is_flushed)
292 global_cache_flush();
293 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
294 writel(agp_bridge->driver->mask_memory(agp_bridge,
295 mem->memory[i],
296 mask_type),
297 intel_private.registers+I810_PTE_BASE+(j*4));
298 }
299 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
300 break;
301 default:
302 goto out_err;
303 }
304
305 agp_bridge->driver->tlb_flush(mem);
306 out:
307 ret = 0;
308 out_err:
309 mem->is_flushed = 1;
310 return ret;
311 }
312
313 static int intel_i810_remove_entries(struct agp_memory *mem, off_t pg_start,
314 int type)
315 {
316 int i;
317
318 if (mem->page_count == 0)
319 return 0;
320
321 for (i = pg_start; i < (mem->page_count + pg_start); i++) {
322 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
323 }
324 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
325
326 agp_bridge->driver->tlb_flush(mem);
327 return 0;
328 }
329
330 /*
331 * The i810/i830 requires a physical address to program its mouse
332 * pointer into hardware.
333 * However the Xserver still writes to it through the agp aperture.
334 */
335 static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type)
336 {
337 struct agp_memory *new;
338 void *addr;
339
340 switch (pg_count) {
341 case 1: addr = agp_bridge->driver->agp_alloc_page(agp_bridge);
342 global_flush_tlb();
343 break;
344 case 4:
345 /* kludge to get 4 physical pages for ARGB cursor */
346 addr = i8xx_alloc_pages();
347 break;
348 default:
349 return NULL;
350 }
351
352 if (addr == NULL)
353 return NULL;
354
355 new = agp_create_memory(pg_count);
356 if (new == NULL)
357 return NULL;
358
359 new->memory[0] = virt_to_gart(addr);
360 if (pg_count == 4) {
361 /* kludge to get 4 physical pages for ARGB cursor */
362 new->memory[1] = new->memory[0] + PAGE_SIZE;
363 new->memory[2] = new->memory[1] + PAGE_SIZE;
364 new->memory[3] = new->memory[2] + PAGE_SIZE;
365 }
366 new->page_count = pg_count;
367 new->num_scratch_pages = pg_count;
368 new->type = AGP_PHYS_MEMORY;
369 new->physical = new->memory[0];
370 return new;
371 }
372
373 static struct agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type)
374 {
375 struct agp_memory *new;
376
377 if (type == AGP_DCACHE_MEMORY) {
378 if (pg_count != intel_private.num_dcache_entries)
379 return NULL;
380
381 new = agp_create_memory(1);
382 if (new == NULL)
383 return NULL;
384
385 new->type = AGP_DCACHE_MEMORY;
386 new->page_count = pg_count;
387 new->num_scratch_pages = 0;
388 agp_free_page_array(new);
389 return new;
390 }
391 if (type == AGP_PHYS_MEMORY)
392 return alloc_agpphysmem_i8xx(pg_count, type);
393 return NULL;
394 }
395
396 static void intel_i810_free_by_type(struct agp_memory *curr)
397 {
398 agp_free_key(curr->key);
399 if (curr->type == AGP_PHYS_MEMORY) {
400 if (curr->page_count == 4)
401 i8xx_destroy_pages(gart_to_virt(curr->memory[0]));
402 else {
403 agp_bridge->driver->agp_destroy_page(
404 gart_to_virt(curr->memory[0]));
405 global_flush_tlb();
406 }
407 agp_free_page_array(curr);
408 }
409 kfree(curr);
410 }
411
412 static unsigned long intel_i810_mask_memory(struct agp_bridge_data *bridge,
413 unsigned long addr, int type)
414 {
415 /* Type checking must be done elsewhere */
416 return addr | bridge->driver->masks[type].mask;
417 }
418
419 static struct aper_size_info_fixed intel_i830_sizes[] =
420 {
421 {128, 32768, 5},
422 /* The 64M mode still requires a 128k gatt */
423 {64, 16384, 5},
424 {256, 65536, 6},
425 {512, 131072, 7},
426 };
427
428 static void intel_i830_init_gtt_entries(void)
429 {
430 u16 gmch_ctrl;
431 int gtt_entries;
432 u8 rdct;
433 int local = 0;
434 static const int ddt[4] = { 0, 16, 32, 64 };
435 int size; /* reserved space (in kb) at the top of stolen memory */
436
437 pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
438
439 if (IS_I965) {
440 u32 pgetbl_ctl;
441 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
442
443 /* The 965 has a field telling us the size of the GTT,
444 * which may be larger than what is necessary to map the
445 * aperture.
446 */
447 switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) {
448 case I965_PGETBL_SIZE_128KB:
449 size = 128;
450 break;
451 case I965_PGETBL_SIZE_256KB:
452 size = 256;
453 break;
454 case I965_PGETBL_SIZE_512KB:
455 size = 512;
456 break;
457 default:
458 printk(KERN_INFO PFX "Unknown page table size, "
459 "assuming 512KB\n");
460 size = 512;
461 }
462 size += 4; /* add in BIOS popup space */
463 } else if (IS_G33) {
464 /* G33's GTT size defined in gmch_ctrl */
465 switch (gmch_ctrl & G33_PGETBL_SIZE_MASK) {
466 case G33_PGETBL_SIZE_1M:
467 size = 1024;
468 break;
469 case G33_PGETBL_SIZE_2M:
470 size = 2048;
471 break;
472 default:
473 printk(KERN_INFO PFX "Unknown page table size 0x%x, "
474 "assuming 512KB\n",
475 (gmch_ctrl & G33_PGETBL_SIZE_MASK));
476 size = 512;
477 }
478 size += 4;
479 } else {
480 /* On previous hardware, the GTT size was just what was
481 * required to map the aperture.
482 */
483 size = agp_bridge->driver->fetch_size() + 4;
484 }
485
486 if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82830_HB ||
487 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) {
488 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
489 case I830_GMCH_GMS_STOLEN_512:
490 gtt_entries = KB(512) - KB(size);
491 break;
492 case I830_GMCH_GMS_STOLEN_1024:
493 gtt_entries = MB(1) - KB(size);
494 break;
495 case I830_GMCH_GMS_STOLEN_8192:
496 gtt_entries = MB(8) - KB(size);
497 break;
498 case I830_GMCH_GMS_LOCAL:
499 rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE);
500 gtt_entries = (I830_RDRAM_ND(rdct) + 1) *
501 MB(ddt[I830_RDRAM_DDT(rdct)]);
502 local = 1;
503 break;
504 default:
505 gtt_entries = 0;
506 break;
507 }
508 } else {
509 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
510 case I855_GMCH_GMS_STOLEN_1M:
511 gtt_entries = MB(1) - KB(size);
512 break;
513 case I855_GMCH_GMS_STOLEN_4M:
514 gtt_entries = MB(4) - KB(size);
515 break;
516 case I855_GMCH_GMS_STOLEN_8M:
517 gtt_entries = MB(8) - KB(size);
518 break;
519 case I855_GMCH_GMS_STOLEN_16M:
520 gtt_entries = MB(16) - KB(size);
521 break;
522 case I855_GMCH_GMS_STOLEN_32M:
523 gtt_entries = MB(32) - KB(size);
524 break;
525 case I915_GMCH_GMS_STOLEN_48M:
526 /* Check it's really I915G */
527 if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB ||
528 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB ||
529 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB ||
530 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB ||
531 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GME_HB ||
532 IS_I965 || IS_G33)
533 gtt_entries = MB(48) - KB(size);
534 else
535 gtt_entries = 0;
536 break;
537 case I915_GMCH_GMS_STOLEN_64M:
538 /* Check it's really I915G */
539 if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB ||
540 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB ||
541 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB ||
542 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB ||
543 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GME_HB ||
544 IS_I965 || IS_G33)
545 gtt_entries = MB(64) - KB(size);
546 else
547 gtt_entries = 0;
548 break;
549 case G33_GMCH_GMS_STOLEN_128M:
550 if (IS_G33)
551 gtt_entries = MB(128) - KB(size);
552 else
553 gtt_entries = 0;
554 break;
555 case G33_GMCH_GMS_STOLEN_256M:
556 if (IS_G33)
557 gtt_entries = MB(256) - KB(size);
558 else
559 gtt_entries = 0;
560 break;
561 default:
562 gtt_entries = 0;
563 break;
564 }
565 }
566 if (gtt_entries > 0)
567 printk(KERN_INFO PFX "Detected %dK %s memory.\n",
568 gtt_entries / KB(1), local ? "local" : "stolen");
569 else
570 printk(KERN_INFO PFX
571 "No pre-allocated video memory detected.\n");
572 gtt_entries /= KB(4);
573
574 intel_private.gtt_entries = gtt_entries;
575 }
576
577 /* The intel i830 automatically initializes the agp aperture during POST.
578 * Use the memory already set aside for in the GTT.
579 */
580 static int intel_i830_create_gatt_table(struct agp_bridge_data *bridge)
581 {
582 int page_order;
583 struct aper_size_info_fixed *size;
584 int num_entries;
585 u32 temp;
586
587 size = agp_bridge->current_size;
588 page_order = size->page_order;
589 num_entries = size->num_entries;
590 agp_bridge->gatt_table_real = NULL;
591
592 pci_read_config_dword(intel_private.pcidev,I810_MMADDR,&temp);
593 temp &= 0xfff80000;
594
595 intel_private.registers = ioremap(temp,128 * 4096);
596 if (!intel_private.registers)
597 return -ENOMEM;
598
599 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
600 global_cache_flush(); /* FIXME: ?? */
601
602 /* we have to call this as early as possible after the MMIO base address is known */
603 intel_i830_init_gtt_entries();
604
605 agp_bridge->gatt_table = NULL;
606
607 agp_bridge->gatt_bus_addr = temp;
608
609 return 0;
610 }
611
612 /* Return the gatt table to a sane state. Use the top of stolen
613 * memory for the GTT.
614 */
615 static int intel_i830_free_gatt_table(struct agp_bridge_data *bridge)
616 {
617 return 0;
618 }
619
620 static int intel_i830_fetch_size(void)
621 {
622 u16 gmch_ctrl;
623 struct aper_size_info_fixed *values;
624
625 values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
626
627 if (agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82830_HB &&
628 agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82845G_HB) {
629 /* 855GM/852GM/865G has 128MB aperture size */
630 agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
631 agp_bridge->aperture_size_idx = 0;
632 return values[0].size;
633 }
634
635 pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
636
637 if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_128M) {
638 agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
639 agp_bridge->aperture_size_idx = 0;
640 return values[0].size;
641 } else {
642 agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + 1);
643 agp_bridge->aperture_size_idx = 1;
644 return values[1].size;
645 }
646
647 return 0;
648 }
649
650 static int intel_i830_configure(void)
651 {
652 struct aper_size_info_fixed *current_size;
653 u32 temp;
654 u16 gmch_ctrl;
655 int i;
656
657 current_size = A_SIZE_FIX(agp_bridge->current_size);
658
659 pci_read_config_dword(intel_private.pcidev,I810_GMADDR,&temp);
660 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
661
662 pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
663 gmch_ctrl |= I830_GMCH_ENABLED;
664 pci_write_config_word(agp_bridge->dev,I830_GMCH_CTRL,gmch_ctrl);
665
666 writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
667 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
668
669 if (agp_bridge->driver->needs_scratch_page) {
670 for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) {
671 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
672 readl(intel_private.registers+I810_PTE_BASE+(i*4)); /* PCI Posting. */
673 }
674 }
675
676 global_cache_flush();
677 return 0;
678 }
679
680 static void intel_i830_cleanup(void)
681 {
682 iounmap(intel_private.registers);
683 }
684
685 static int intel_i830_insert_entries(struct agp_memory *mem,off_t pg_start, int type)
686 {
687 int i,j,num_entries;
688 void *temp;
689 int ret = -EINVAL;
690 int mask_type;
691
692 if (mem->page_count == 0)
693 goto out;
694
695 temp = agp_bridge->current_size;
696 num_entries = A_SIZE_FIX(temp)->num_entries;
697
698 if (pg_start < intel_private.gtt_entries) {
699 printk (KERN_DEBUG PFX "pg_start == 0x%.8lx,intel_private.gtt_entries == 0x%.8x\n",
700 pg_start,intel_private.gtt_entries);
701
702 printk (KERN_INFO PFX "Trying to insert into local/stolen memory\n");
703 goto out_err;
704 }
705
706 if ((pg_start + mem->page_count) > num_entries)
707 goto out_err;
708
709 /* The i830 can't check the GTT for entries since its read only,
710 * depend on the caller to make the correct offset decisions.
711 */
712
713 if (type != mem->type)
714 goto out_err;
715
716 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
717
718 if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
719 mask_type != INTEL_AGP_CACHED_MEMORY)
720 goto out_err;
721
722 if (!mem->is_flushed)
723 global_cache_flush();
724
725 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
726 writel(agp_bridge->driver->mask_memory(agp_bridge,
727 mem->memory[i], mask_type),
728 intel_private.registers+I810_PTE_BASE+(j*4));
729 }
730 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
731 agp_bridge->driver->tlb_flush(mem);
732
733 out:
734 ret = 0;
735 out_err:
736 mem->is_flushed = 1;
737 return ret;
738 }
739
740 static int intel_i830_remove_entries(struct agp_memory *mem,off_t pg_start,
741 int type)
742 {
743 int i;
744
745 if (mem->page_count == 0)
746 return 0;
747
748 if (pg_start < intel_private.gtt_entries) {
749 printk (KERN_INFO PFX "Trying to disable local/stolen memory\n");
750 return -EINVAL;
751 }
752
753 for (i = pg_start; i < (mem->page_count + pg_start); i++) {
754 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
755 }
756 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
757
758 agp_bridge->driver->tlb_flush(mem);
759 return 0;
760 }
761
762 static struct agp_memory *intel_i830_alloc_by_type(size_t pg_count,int type)
763 {
764 if (type == AGP_PHYS_MEMORY)
765 return alloc_agpphysmem_i8xx(pg_count, type);
766 /* always return NULL for other allocation types for now */
767 return NULL;
768 }
769
770 static int intel_i915_configure(void)
771 {
772 struct aper_size_info_fixed *current_size;
773 u32 temp;
774 u16 gmch_ctrl;
775 int i;
776
777 current_size = A_SIZE_FIX(agp_bridge->current_size);
778
779 pci_read_config_dword(intel_private.pcidev, I915_GMADDR, &temp);
780
781 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
782
783 pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
784 gmch_ctrl |= I830_GMCH_ENABLED;
785 pci_write_config_word(agp_bridge->dev,I830_GMCH_CTRL,gmch_ctrl);
786
787 writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
788 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
789
790 if (agp_bridge->driver->needs_scratch_page) {
791 for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) {
792 writel(agp_bridge->scratch_page, intel_private.gtt+i);
793 readl(intel_private.gtt+i); /* PCI Posting. */
794 }
795 }
796
797 global_cache_flush();
798 return 0;
799 }
800
801 static void intel_i915_cleanup(void)
802 {
803 iounmap(intel_private.gtt);
804 iounmap(intel_private.registers);
805 }
806
807 static int intel_i915_insert_entries(struct agp_memory *mem,off_t pg_start,
808 int type)
809 {
810 int i,j,num_entries;
811 void *temp;
812 int ret = -EINVAL;
813 int mask_type;
814
815 if (mem->page_count == 0)
816 goto out;
817
818 temp = agp_bridge->current_size;
819 num_entries = A_SIZE_FIX(temp)->num_entries;
820
821 if (pg_start < intel_private.gtt_entries) {
822 printk (KERN_DEBUG PFX "pg_start == 0x%.8lx,intel_private.gtt_entries == 0x%.8x\n",
823 pg_start,intel_private.gtt_entries);
824
825 printk (KERN_INFO PFX "Trying to insert into local/stolen memory\n");
826 goto out_err;
827 }
828
829 if ((pg_start + mem->page_count) > num_entries)
830 goto out_err;
831
832 /* The i915 can't check the GTT for entries since its read only,
833 * depend on the caller to make the correct offset decisions.
834 */
835
836 if (type != mem->type)
837 goto out_err;
838
839 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
840
841 if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
842 mask_type != INTEL_AGP_CACHED_MEMORY)
843 goto out_err;
844
845 if (!mem->is_flushed)
846 global_cache_flush();
847
848 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
849 writel(agp_bridge->driver->mask_memory(agp_bridge,
850 mem->memory[i], mask_type), intel_private.gtt+j);
851 }
852
853 readl(intel_private.gtt+j-1);
854 agp_bridge->driver->tlb_flush(mem);
855
856 out:
857 ret = 0;
858 out_err:
859 mem->is_flushed = 1;
860 return ret;
861 }
862
863 static int intel_i915_remove_entries(struct agp_memory *mem,off_t pg_start,
864 int type)
865 {
866 int i;
867
868 if (mem->page_count == 0)
869 return 0;
870
871 if (pg_start < intel_private.gtt_entries) {
872 printk (KERN_INFO PFX "Trying to disable local/stolen memory\n");
873 return -EINVAL;
874 }
875
876 for (i = pg_start; i < (mem->page_count + pg_start); i++) {
877 writel(agp_bridge->scratch_page, intel_private.gtt+i);
878 }
879 readl(intel_private.gtt+i-1);
880
881 agp_bridge->driver->tlb_flush(mem);
882 return 0;
883 }
884
885 /* Return the aperture size by just checking the resource length. The effect
886 * described in the spec of the MSAC registers is just changing of the
887 * resource size.
888 */
889 static int intel_i9xx_fetch_size(void)
890 {
891 int num_sizes = ARRAY_SIZE(intel_i830_sizes);
892 int aper_size; /* size in megabytes */
893 int i;
894
895 aper_size = pci_resource_len(intel_private.pcidev, 2) / MB(1);
896
897 for (i = 0; i < num_sizes; i++) {
898 if (aper_size == intel_i830_sizes[i].size) {
899 agp_bridge->current_size = intel_i830_sizes + i;
900 agp_bridge->previous_size = agp_bridge->current_size;
901 return aper_size;
902 }
903 }
904
905 return 0;
906 }
907
908 /* The intel i915 automatically initializes the agp aperture during POST.
909 * Use the memory already set aside for in the GTT.
910 */
911 static int intel_i915_create_gatt_table(struct agp_bridge_data *bridge)
912 {
913 int page_order;
914 struct aper_size_info_fixed *size;
915 int num_entries;
916 u32 temp, temp2;
917
918 size = agp_bridge->current_size;
919 page_order = size->page_order;
920 num_entries = size->num_entries;
921 agp_bridge->gatt_table_real = NULL;
922
923 pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
924 pci_read_config_dword(intel_private.pcidev, I915_PTEADDR,&temp2);
925
926 intel_private.gtt = ioremap(temp2, 256 * 1024);
927 if (!intel_private.gtt)
928 return -ENOMEM;
929
930 temp &= 0xfff80000;
931
932 intel_private.registers = ioremap(temp,128 * 4096);
933 if (!intel_private.registers) {
934 iounmap(intel_private.gtt);
935 return -ENOMEM;
936 }
937
938 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
939 global_cache_flush(); /* FIXME: ? */
940
941 /* we have to call this as early as possible after the MMIO base address is known */
942 intel_i830_init_gtt_entries();
943
944 agp_bridge->gatt_table = NULL;
945
946 agp_bridge->gatt_bus_addr = temp;
947
948 return 0;
949 }
950
951 /*
952 * The i965 supports 36-bit physical addresses, but to keep
953 * the format of the GTT the same, the bits that don't fit
954 * in a 32-bit word are shifted down to bits 4..7.
955 *
956 * Gcc is smart enough to notice that "(addr >> 28) & 0xf0"
957 * is always zero on 32-bit architectures, so no need to make
958 * this conditional.
959 */
960 static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge,
961 unsigned long addr, int type)
962 {
963 /* Shift high bits down */
964 addr |= (addr >> 28) & 0xf0;
965
966 /* Type checking must be done elsewhere */
967 return addr | bridge->driver->masks[type].mask;
968 }
969
970 /* The intel i965 automatically initializes the agp aperture during POST.
971 * Use the memory already set aside for in the GTT.
972 */
973 static int intel_i965_create_gatt_table(struct agp_bridge_data *bridge)
974 {
975 int page_order;
976 struct aper_size_info_fixed *size;
977 int num_entries;
978 u32 temp;
979
980 size = agp_bridge->current_size;
981 page_order = size->page_order;
982 num_entries = size->num_entries;
983 agp_bridge->gatt_table_real = NULL;
984
985 pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
986
987 temp &= 0xfff00000;
988 intel_private.gtt = ioremap((temp + (512 * 1024)) , 512 * 1024);
989
990 if (!intel_private.gtt)
991 return -ENOMEM;
992
993
994 intel_private.registers = ioremap(temp,128 * 4096);
995 if (!intel_private.registers) {
996 iounmap(intel_private.gtt);
997 return -ENOMEM;
998 }
999
1000 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
1001 global_cache_flush(); /* FIXME: ? */
1002
1003 /* we have to call this as early as possible after the MMIO base address is known */
1004 intel_i830_init_gtt_entries();
1005
1006 agp_bridge->gatt_table = NULL;
1007
1008 agp_bridge->gatt_bus_addr = temp;
1009
1010 return 0;
1011 }
1012
1013
1014 static int intel_fetch_size(void)
1015 {
1016 int i;
1017 u16 temp;
1018 struct aper_size_info_16 *values;
1019
1020 pci_read_config_word(agp_bridge->dev, INTEL_APSIZE, &temp);
1021 values = A_SIZE_16(agp_bridge->driver->aperture_sizes);
1022
1023 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
1024 if (temp == values[i].size_value) {
1025 agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + i);
1026 agp_bridge->aperture_size_idx = i;
1027 return values[i].size;
1028 }
1029 }
1030
1031 return 0;
1032 }
1033
1034 static int __intel_8xx_fetch_size(u8 temp)
1035 {
1036 int i;
1037 struct aper_size_info_8 *values;
1038
1039 values = A_SIZE_8(agp_bridge->driver->aperture_sizes);
1040
1041 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
1042 if (temp == values[i].size_value) {
1043 agp_bridge->previous_size =
1044 agp_bridge->current_size = (void *) (values + i);
1045 agp_bridge->aperture_size_idx = i;
1046 return values[i].size;
1047 }
1048 }
1049 return 0;
1050 }
1051
1052 static int intel_8xx_fetch_size(void)
1053 {
1054 u8 temp;
1055
1056 pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
1057 return __intel_8xx_fetch_size(temp);
1058 }
1059
1060 static int intel_815_fetch_size(void)
1061 {
1062 u8 temp;
1063
1064 /* Intel 815 chipsets have a _weird_ APSIZE register with only
1065 * one non-reserved bit, so mask the others out ... */
1066 pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
1067 temp &= (1 << 3);
1068
1069 return __intel_8xx_fetch_size(temp);
1070 }
1071
1072 static void intel_tlbflush(struct agp_memory *mem)
1073 {
1074 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2200);
1075 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
1076 }
1077
1078
1079 static void intel_8xx_tlbflush(struct agp_memory *mem)
1080 {
1081 u32 temp;
1082 pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
1083 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp & ~(1 << 7));
1084 pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
1085 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp | (1 << 7));
1086 }
1087
1088
1089 static void intel_cleanup(void)
1090 {
1091 u16 temp;
1092 struct aper_size_info_16 *previous_size;
1093
1094 previous_size = A_SIZE_16(agp_bridge->previous_size);
1095 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
1096 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
1097 pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
1098 }
1099
1100
1101 static void intel_8xx_cleanup(void)
1102 {
1103 u16 temp;
1104 struct aper_size_info_8 *previous_size;
1105
1106 previous_size = A_SIZE_8(agp_bridge->previous_size);
1107 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
1108 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
1109 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
1110 }
1111
1112
1113 static int intel_configure(void)
1114 {
1115 u32 temp;
1116 u16 temp2;
1117 struct aper_size_info_16 *current_size;
1118
1119 current_size = A_SIZE_16(agp_bridge->current_size);
1120
1121 /* aperture size */
1122 pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1123
1124 /* address to map to */
1125 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1126 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1127
1128 /* attbase - aperture base */
1129 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1130
1131 /* agpctrl */
1132 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
1133
1134 /* paccfg/nbxcfg */
1135 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
1136 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG,
1137 (temp2 & ~(1 << 10)) | (1 << 9));
1138 /* clear any possible error conditions */
1139 pci_write_config_byte(agp_bridge->dev, INTEL_ERRSTS + 1, 7);
1140 return 0;
1141 }
1142
1143 static int intel_815_configure(void)
1144 {
1145 u32 temp, addr;
1146 u8 temp2;
1147 struct aper_size_info_8 *current_size;
1148
1149 /* attbase - aperture base */
1150 /* the Intel 815 chipset spec. says that bits 29-31 in the
1151 * ATTBASE register are reserved -> try not to write them */
1152 if (agp_bridge->gatt_bus_addr & INTEL_815_ATTBASE_MASK) {
1153 printk (KERN_EMERG PFX "gatt bus addr too high");
1154 return -EINVAL;
1155 }
1156
1157 current_size = A_SIZE_8(agp_bridge->current_size);
1158
1159 /* aperture size */
1160 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
1161 current_size->size_value);
1162
1163 /* address to map to */
1164 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1165 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1166
1167 pci_read_config_dword(agp_bridge->dev, INTEL_ATTBASE, &addr);
1168 addr &= INTEL_815_ATTBASE_MASK;
1169 addr |= agp_bridge->gatt_bus_addr;
1170 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, addr);
1171
1172 /* agpctrl */
1173 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1174
1175 /* apcont */
1176 pci_read_config_byte(agp_bridge->dev, INTEL_815_APCONT, &temp2);
1177 pci_write_config_byte(agp_bridge->dev, INTEL_815_APCONT, temp2 | (1 << 1));
1178
1179 /* clear any possible error conditions */
1180 /* Oddness : this chipset seems to have no ERRSTS register ! */
1181 return 0;
1182 }
1183
1184 static void intel_820_tlbflush(struct agp_memory *mem)
1185 {
1186 return;
1187 }
1188
1189 static void intel_820_cleanup(void)
1190 {
1191 u8 temp;
1192 struct aper_size_info_8 *previous_size;
1193
1194 previous_size = A_SIZE_8(agp_bridge->previous_size);
1195 pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp);
1196 pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR,
1197 temp & ~(1 << 1));
1198 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
1199 previous_size->size_value);
1200 }
1201
1202
1203 static int intel_820_configure(void)
1204 {
1205 u32 temp;
1206 u8 temp2;
1207 struct aper_size_info_8 *current_size;
1208
1209 current_size = A_SIZE_8(agp_bridge->current_size);
1210
1211 /* aperture size */
1212 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1213
1214 /* address to map to */
1215 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1216 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1217
1218 /* attbase - aperture base */
1219 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1220
1221 /* agpctrl */
1222 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1223
1224 /* global enable aperture access */
1225 /* This flag is not accessed through MCHCFG register as in */
1226 /* i850 chipset. */
1227 pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp2);
1228 pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, temp2 | (1 << 1));
1229 /* clear any possible AGP-related error conditions */
1230 pci_write_config_word(agp_bridge->dev, INTEL_I820_ERRSTS, 0x001c);
1231 return 0;
1232 }
1233
1234 static int intel_840_configure(void)
1235 {
1236 u32 temp;
1237 u16 temp2;
1238 struct aper_size_info_8 *current_size;
1239
1240 current_size = A_SIZE_8(agp_bridge->current_size);
1241
1242 /* aperture size */
1243 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1244
1245 /* address to map to */
1246 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1247 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1248
1249 /* attbase - aperture base */
1250 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1251
1252 /* agpctrl */
1253 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1254
1255 /* mcgcfg */
1256 pci_read_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, &temp2);
1257 pci_write_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, temp2 | (1 << 9));
1258 /* clear any possible error conditions */
1259 pci_write_config_word(agp_bridge->dev, INTEL_I840_ERRSTS, 0xc000);
1260 return 0;
1261 }
1262
1263 static int intel_845_configure(void)
1264 {
1265 u32 temp;
1266 u8 temp2;
1267 struct aper_size_info_8 *current_size;
1268
1269 current_size = A_SIZE_8(agp_bridge->current_size);
1270
1271 /* aperture size */
1272 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1273
1274 if (agp_bridge->apbase_config != 0) {
1275 pci_write_config_dword(agp_bridge->dev, AGP_APBASE,
1276 agp_bridge->apbase_config);
1277 } else {
1278 /* address to map to */
1279 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1280 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1281 agp_bridge->apbase_config = temp;
1282 }
1283
1284 /* attbase - aperture base */
1285 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1286
1287 /* agpctrl */
1288 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1289
1290 /* agpm */
1291 pci_read_config_byte(agp_bridge->dev, INTEL_I845_AGPM, &temp2);
1292 pci_write_config_byte(agp_bridge->dev, INTEL_I845_AGPM, temp2 | (1 << 1));
1293 /* clear any possible error conditions */
1294 pci_write_config_word(agp_bridge->dev, INTEL_I845_ERRSTS, 0x001c);
1295 return 0;
1296 }
1297
1298 static int intel_850_configure(void)
1299 {
1300 u32 temp;
1301 u16 temp2;
1302 struct aper_size_info_8 *current_size;
1303
1304 current_size = A_SIZE_8(agp_bridge->current_size);
1305
1306 /* aperture size */
1307 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1308
1309 /* address to map to */
1310 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1311 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1312
1313 /* attbase - aperture base */
1314 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1315
1316 /* agpctrl */
1317 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1318
1319 /* mcgcfg */
1320 pci_read_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, &temp2);
1321 pci_write_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, temp2 | (1 << 9));
1322 /* clear any possible AGP-related error conditions */
1323 pci_write_config_word(agp_bridge->dev, INTEL_I850_ERRSTS, 0x001c);
1324 return 0;
1325 }
1326
1327 static int intel_860_configure(void)
1328 {
1329 u32 temp;
1330 u16 temp2;
1331 struct aper_size_info_8 *current_size;
1332
1333 current_size = A_SIZE_8(agp_bridge->current_size);
1334
1335 /* aperture size */
1336 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1337
1338 /* address to map to */
1339 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1340 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1341
1342 /* attbase - aperture base */
1343 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1344
1345 /* agpctrl */
1346 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1347
1348 /* mcgcfg */
1349 pci_read_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, &temp2);
1350 pci_write_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, temp2 | (1 << 9));
1351 /* clear any possible AGP-related error conditions */
1352 pci_write_config_word(agp_bridge->dev, INTEL_I860_ERRSTS, 0xf700);
1353 return 0;
1354 }
1355
1356 static int intel_830mp_configure(void)
1357 {
1358 u32 temp;
1359 u16 temp2;
1360 struct aper_size_info_8 *current_size;
1361
1362 current_size = A_SIZE_8(agp_bridge->current_size);
1363
1364 /* aperture size */
1365 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1366
1367 /* address to map to */
1368 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1369 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1370
1371 /* attbase - aperture base */
1372 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1373
1374 /* agpctrl */
1375 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1376
1377 /* gmch */
1378 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
1379 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp2 | (1 << 9));
1380 /* clear any possible AGP-related error conditions */
1381 pci_write_config_word(agp_bridge->dev, INTEL_I830_ERRSTS, 0x1c);
1382 return 0;
1383 }
1384
1385 static int intel_7505_configure(void)
1386 {
1387 u32 temp;
1388 u16 temp2;
1389 struct aper_size_info_8 *current_size;
1390
1391 current_size = A_SIZE_8(agp_bridge->current_size);
1392
1393 /* aperture size */
1394 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1395
1396 /* address to map to */
1397 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1398 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1399
1400 /* attbase - aperture base */
1401 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1402
1403 /* agpctrl */
1404 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1405
1406 /* mchcfg */
1407 pci_read_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, &temp2);
1408 pci_write_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, temp2 | (1 << 9));
1409
1410 return 0;
1411 }
1412
1413 /* Setup function */
1414 static const struct gatt_mask intel_generic_masks[] =
1415 {
1416 {.mask = 0x00000017, .type = 0}
1417 };
1418
1419 static const struct aper_size_info_8 intel_815_sizes[2] =
1420 {
1421 {64, 16384, 4, 0},
1422 {32, 8192, 3, 8},
1423 };
1424
1425 static const struct aper_size_info_8 intel_8xx_sizes[7] =
1426 {
1427 {256, 65536, 6, 0},
1428 {128, 32768, 5, 32},
1429 {64, 16384, 4, 48},
1430 {32, 8192, 3, 56},
1431 {16, 4096, 2, 60},
1432 {8, 2048, 1, 62},
1433 {4, 1024, 0, 63}
1434 };
1435
1436 static const struct aper_size_info_16 intel_generic_sizes[7] =
1437 {
1438 {256, 65536, 6, 0},
1439 {128, 32768, 5, 32},
1440 {64, 16384, 4, 48},
1441 {32, 8192, 3, 56},
1442 {16, 4096, 2, 60},
1443 {8, 2048, 1, 62},
1444 {4, 1024, 0, 63}
1445 };
1446
1447 static const struct aper_size_info_8 intel_830mp_sizes[4] =
1448 {
1449 {256, 65536, 6, 0},
1450 {128, 32768, 5, 32},
1451 {64, 16384, 4, 48},
1452 {32, 8192, 3, 56}
1453 };
1454
1455 static const struct agp_bridge_driver intel_generic_driver = {
1456 .owner = THIS_MODULE,
1457 .aperture_sizes = intel_generic_sizes,
1458 .size_type = U16_APER_SIZE,
1459 .num_aperture_sizes = 7,
1460 .configure = intel_configure,
1461 .fetch_size = intel_fetch_size,
1462 .cleanup = intel_cleanup,
1463 .tlb_flush = intel_tlbflush,
1464 .mask_memory = agp_generic_mask_memory,
1465 .masks = intel_generic_masks,
1466 .agp_enable = agp_generic_enable,
1467 .cache_flush = global_cache_flush,
1468 .create_gatt_table = agp_generic_create_gatt_table,
1469 .free_gatt_table = agp_generic_free_gatt_table,
1470 .insert_memory = agp_generic_insert_memory,
1471 .remove_memory = agp_generic_remove_memory,
1472 .alloc_by_type = agp_generic_alloc_by_type,
1473 .free_by_type = agp_generic_free_by_type,
1474 .agp_alloc_page = agp_generic_alloc_page,
1475 .agp_destroy_page = agp_generic_destroy_page,
1476 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1477 };
1478
1479 static const struct agp_bridge_driver intel_810_driver = {
1480 .owner = THIS_MODULE,
1481 .aperture_sizes = intel_i810_sizes,
1482 .size_type = FIXED_APER_SIZE,
1483 .num_aperture_sizes = 2,
1484 .needs_scratch_page = TRUE,
1485 .configure = intel_i810_configure,
1486 .fetch_size = intel_i810_fetch_size,
1487 .cleanup = intel_i810_cleanup,
1488 .tlb_flush = intel_i810_tlbflush,
1489 .mask_memory = intel_i810_mask_memory,
1490 .masks = intel_i810_masks,
1491 .agp_enable = intel_i810_agp_enable,
1492 .cache_flush = global_cache_flush,
1493 .create_gatt_table = agp_generic_create_gatt_table,
1494 .free_gatt_table = agp_generic_free_gatt_table,
1495 .insert_memory = intel_i810_insert_entries,
1496 .remove_memory = intel_i810_remove_entries,
1497 .alloc_by_type = intel_i810_alloc_by_type,
1498 .free_by_type = intel_i810_free_by_type,
1499 .agp_alloc_page = agp_generic_alloc_page,
1500 .agp_destroy_page = agp_generic_destroy_page,
1501 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1502 };
1503
1504 static const struct agp_bridge_driver intel_815_driver = {
1505 .owner = THIS_MODULE,
1506 .aperture_sizes = intel_815_sizes,
1507 .size_type = U8_APER_SIZE,
1508 .num_aperture_sizes = 2,
1509 .configure = intel_815_configure,
1510 .fetch_size = intel_815_fetch_size,
1511 .cleanup = intel_8xx_cleanup,
1512 .tlb_flush = intel_8xx_tlbflush,
1513 .mask_memory = agp_generic_mask_memory,
1514 .masks = intel_generic_masks,
1515 .agp_enable = agp_generic_enable,
1516 .cache_flush = global_cache_flush,
1517 .create_gatt_table = agp_generic_create_gatt_table,
1518 .free_gatt_table = agp_generic_free_gatt_table,
1519 .insert_memory = agp_generic_insert_memory,
1520 .remove_memory = agp_generic_remove_memory,
1521 .alloc_by_type = agp_generic_alloc_by_type,
1522 .free_by_type = agp_generic_free_by_type,
1523 .agp_alloc_page = agp_generic_alloc_page,
1524 .agp_destroy_page = agp_generic_destroy_page,
1525 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1526 };
1527
1528 static const struct agp_bridge_driver intel_830_driver = {
1529 .owner = THIS_MODULE,
1530 .aperture_sizes = intel_i830_sizes,
1531 .size_type = FIXED_APER_SIZE,
1532 .num_aperture_sizes = 4,
1533 .needs_scratch_page = TRUE,
1534 .configure = intel_i830_configure,
1535 .fetch_size = intel_i830_fetch_size,
1536 .cleanup = intel_i830_cleanup,
1537 .tlb_flush = intel_i810_tlbflush,
1538 .mask_memory = intel_i810_mask_memory,
1539 .masks = intel_i810_masks,
1540 .agp_enable = intel_i810_agp_enable,
1541 .cache_flush = global_cache_flush,
1542 .create_gatt_table = intel_i830_create_gatt_table,
1543 .free_gatt_table = intel_i830_free_gatt_table,
1544 .insert_memory = intel_i830_insert_entries,
1545 .remove_memory = intel_i830_remove_entries,
1546 .alloc_by_type = intel_i830_alloc_by_type,
1547 .free_by_type = intel_i810_free_by_type,
1548 .agp_alloc_page = agp_generic_alloc_page,
1549 .agp_destroy_page = agp_generic_destroy_page,
1550 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
1551 };
1552
1553 static const struct agp_bridge_driver intel_820_driver = {
1554 .owner = THIS_MODULE,
1555 .aperture_sizes = intel_8xx_sizes,
1556 .size_type = U8_APER_SIZE,
1557 .num_aperture_sizes = 7,
1558 .configure = intel_820_configure,
1559 .fetch_size = intel_8xx_fetch_size,
1560 .cleanup = intel_820_cleanup,
1561 .tlb_flush = intel_820_tlbflush,
1562 .mask_memory = agp_generic_mask_memory,
1563 .masks = intel_generic_masks,
1564 .agp_enable = agp_generic_enable,
1565 .cache_flush = global_cache_flush,
1566 .create_gatt_table = agp_generic_create_gatt_table,
1567 .free_gatt_table = agp_generic_free_gatt_table,
1568 .insert_memory = agp_generic_insert_memory,
1569 .remove_memory = agp_generic_remove_memory,
1570 .alloc_by_type = agp_generic_alloc_by_type,
1571 .free_by_type = agp_generic_free_by_type,
1572 .agp_alloc_page = agp_generic_alloc_page,
1573 .agp_destroy_page = agp_generic_destroy_page,
1574 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1575 };
1576
1577 static const struct agp_bridge_driver intel_830mp_driver = {
1578 .owner = THIS_MODULE,
1579 .aperture_sizes = intel_830mp_sizes,
1580 .size_type = U8_APER_SIZE,
1581 .num_aperture_sizes = 4,
1582 .configure = intel_830mp_configure,
1583 .fetch_size = intel_8xx_fetch_size,
1584 .cleanup = intel_8xx_cleanup,
1585 .tlb_flush = intel_8xx_tlbflush,
1586 .mask_memory = agp_generic_mask_memory,
1587 .masks = intel_generic_masks,
1588 .agp_enable = agp_generic_enable,
1589 .cache_flush = global_cache_flush,
1590 .create_gatt_table = agp_generic_create_gatt_table,
1591 .free_gatt_table = agp_generic_free_gatt_table,
1592 .insert_memory = agp_generic_insert_memory,
1593 .remove_memory = agp_generic_remove_memory,
1594 .alloc_by_type = agp_generic_alloc_by_type,
1595 .free_by_type = agp_generic_free_by_type,
1596 .agp_alloc_page = agp_generic_alloc_page,
1597 .agp_destroy_page = agp_generic_destroy_page,
1598 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1599 };
1600
1601 static const struct agp_bridge_driver intel_840_driver = {
1602 .owner = THIS_MODULE,
1603 .aperture_sizes = intel_8xx_sizes,
1604 .size_type = U8_APER_SIZE,
1605 .num_aperture_sizes = 7,
1606 .configure = intel_840_configure,
1607 .fetch_size = intel_8xx_fetch_size,
1608 .cleanup = intel_8xx_cleanup,
1609 .tlb_flush = intel_8xx_tlbflush,
1610 .mask_memory = agp_generic_mask_memory,
1611 .masks = intel_generic_masks,
1612 .agp_enable = agp_generic_enable,
1613 .cache_flush = global_cache_flush,
1614 .create_gatt_table = agp_generic_create_gatt_table,
1615 .free_gatt_table = agp_generic_free_gatt_table,
1616 .insert_memory = agp_generic_insert_memory,
1617 .remove_memory = agp_generic_remove_memory,
1618 .alloc_by_type = agp_generic_alloc_by_type,
1619 .free_by_type = agp_generic_free_by_type,
1620 .agp_alloc_page = agp_generic_alloc_page,
1621 .agp_destroy_page = agp_generic_destroy_page,
1622 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1623 };
1624
1625 static const struct agp_bridge_driver intel_845_driver = {
1626 .owner = THIS_MODULE,
1627 .aperture_sizes = intel_8xx_sizes,
1628 .size_type = U8_APER_SIZE,
1629 .num_aperture_sizes = 7,
1630 .configure = intel_845_configure,
1631 .fetch_size = intel_8xx_fetch_size,
1632 .cleanup = intel_8xx_cleanup,
1633 .tlb_flush = intel_8xx_tlbflush,
1634 .mask_memory = agp_generic_mask_memory,
1635 .masks = intel_generic_masks,
1636 .agp_enable = agp_generic_enable,
1637 .cache_flush = global_cache_flush,
1638 .create_gatt_table = agp_generic_create_gatt_table,
1639 .free_gatt_table = agp_generic_free_gatt_table,
1640 .insert_memory = agp_generic_insert_memory,
1641 .remove_memory = agp_generic_remove_memory,
1642 .alloc_by_type = agp_generic_alloc_by_type,
1643 .free_by_type = agp_generic_free_by_type,
1644 .agp_alloc_page = agp_generic_alloc_page,
1645 .agp_destroy_page = agp_generic_destroy_page,
1646 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1647 };
1648
1649 static const struct agp_bridge_driver intel_850_driver = {
1650 .owner = THIS_MODULE,
1651 .aperture_sizes = intel_8xx_sizes,
1652 .size_type = U8_APER_SIZE,
1653 .num_aperture_sizes = 7,
1654 .configure = intel_850_configure,
1655 .fetch_size = intel_8xx_fetch_size,
1656 .cleanup = intel_8xx_cleanup,
1657 .tlb_flush = intel_8xx_tlbflush,
1658 .mask_memory = agp_generic_mask_memory,
1659 .masks = intel_generic_masks,
1660 .agp_enable = agp_generic_enable,
1661 .cache_flush = global_cache_flush,
1662 .create_gatt_table = agp_generic_create_gatt_table,
1663 .free_gatt_table = agp_generic_free_gatt_table,
1664 .insert_memory = agp_generic_insert_memory,
1665 .remove_memory = agp_generic_remove_memory,
1666 .alloc_by_type = agp_generic_alloc_by_type,
1667 .free_by_type = agp_generic_free_by_type,
1668 .agp_alloc_page = agp_generic_alloc_page,
1669 .agp_destroy_page = agp_generic_destroy_page,
1670 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1671 };
1672
1673 static const struct agp_bridge_driver intel_860_driver = {
1674 .owner = THIS_MODULE,
1675 .aperture_sizes = intel_8xx_sizes,
1676 .size_type = U8_APER_SIZE,
1677 .num_aperture_sizes = 7,
1678 .configure = intel_860_configure,
1679 .fetch_size = intel_8xx_fetch_size,
1680 .cleanup = intel_8xx_cleanup,
1681 .tlb_flush = intel_8xx_tlbflush,
1682 .mask_memory = agp_generic_mask_memory,
1683 .masks = intel_generic_masks,
1684 .agp_enable = agp_generic_enable,
1685 .cache_flush = global_cache_flush,
1686 .create_gatt_table = agp_generic_create_gatt_table,
1687 .free_gatt_table = agp_generic_free_gatt_table,
1688 .insert_memory = agp_generic_insert_memory,
1689 .remove_memory = agp_generic_remove_memory,
1690 .alloc_by_type = agp_generic_alloc_by_type,
1691 .free_by_type = agp_generic_free_by_type,
1692 .agp_alloc_page = agp_generic_alloc_page,
1693 .agp_destroy_page = agp_generic_destroy_page,
1694 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1695 };
1696
1697 static const struct agp_bridge_driver intel_915_driver = {
1698 .owner = THIS_MODULE,
1699 .aperture_sizes = intel_i830_sizes,
1700 .size_type = FIXED_APER_SIZE,
1701 .num_aperture_sizes = 4,
1702 .needs_scratch_page = TRUE,
1703 .configure = intel_i915_configure,
1704 .fetch_size = intel_i9xx_fetch_size,
1705 .cleanup = intel_i915_cleanup,
1706 .tlb_flush = intel_i810_tlbflush,
1707 .mask_memory = intel_i810_mask_memory,
1708 .masks = intel_i810_masks,
1709 .agp_enable = intel_i810_agp_enable,
1710 .cache_flush = global_cache_flush,
1711 .create_gatt_table = intel_i915_create_gatt_table,
1712 .free_gatt_table = intel_i830_free_gatt_table,
1713 .insert_memory = intel_i915_insert_entries,
1714 .remove_memory = intel_i915_remove_entries,
1715 .alloc_by_type = intel_i830_alloc_by_type,
1716 .free_by_type = intel_i810_free_by_type,
1717 .agp_alloc_page = agp_generic_alloc_page,
1718 .agp_destroy_page = agp_generic_destroy_page,
1719 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
1720 };
1721
1722 static const struct agp_bridge_driver intel_i965_driver = {
1723 .owner = THIS_MODULE,
1724 .aperture_sizes = intel_i830_sizes,
1725 .size_type = FIXED_APER_SIZE,
1726 .num_aperture_sizes = 4,
1727 .needs_scratch_page = TRUE,
1728 .configure = intel_i915_configure,
1729 .fetch_size = intel_i9xx_fetch_size,
1730 .cleanup = intel_i915_cleanup,
1731 .tlb_flush = intel_i810_tlbflush,
1732 .mask_memory = intel_i965_mask_memory,
1733 .masks = intel_i810_masks,
1734 .agp_enable = intel_i810_agp_enable,
1735 .cache_flush = global_cache_flush,
1736 .create_gatt_table = intel_i965_create_gatt_table,
1737 .free_gatt_table = intel_i830_free_gatt_table,
1738 .insert_memory = intel_i915_insert_entries,
1739 .remove_memory = intel_i915_remove_entries,
1740 .alloc_by_type = intel_i830_alloc_by_type,
1741 .free_by_type = intel_i810_free_by_type,
1742 .agp_alloc_page = agp_generic_alloc_page,
1743 .agp_destroy_page = agp_generic_destroy_page,
1744 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
1745 };
1746
1747 static const struct agp_bridge_driver intel_7505_driver = {
1748 .owner = THIS_MODULE,
1749 .aperture_sizes = intel_8xx_sizes,
1750 .size_type = U8_APER_SIZE,
1751 .num_aperture_sizes = 7,
1752 .configure = intel_7505_configure,
1753 .fetch_size = intel_8xx_fetch_size,
1754 .cleanup = intel_8xx_cleanup,
1755 .tlb_flush = intel_8xx_tlbflush,
1756 .mask_memory = agp_generic_mask_memory,
1757 .masks = intel_generic_masks,
1758 .agp_enable = agp_generic_enable,
1759 .cache_flush = global_cache_flush,
1760 .create_gatt_table = agp_generic_create_gatt_table,
1761 .free_gatt_table = agp_generic_free_gatt_table,
1762 .insert_memory = agp_generic_insert_memory,
1763 .remove_memory = agp_generic_remove_memory,
1764 .alloc_by_type = agp_generic_alloc_by_type,
1765 .free_by_type = agp_generic_free_by_type,
1766 .agp_alloc_page = agp_generic_alloc_page,
1767 .agp_destroy_page = agp_generic_destroy_page,
1768 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1769 };
1770
1771 static const struct agp_bridge_driver intel_g33_driver = {
1772 .owner = THIS_MODULE,
1773 .aperture_sizes = intel_i830_sizes,
1774 .size_type = FIXED_APER_SIZE,
1775 .num_aperture_sizes = 4,
1776 .needs_scratch_page = TRUE,
1777 .configure = intel_i915_configure,
1778 .fetch_size = intel_i9xx_fetch_size,
1779 .cleanup = intel_i915_cleanup,
1780 .tlb_flush = intel_i810_tlbflush,
1781 .mask_memory = intel_i965_mask_memory,
1782 .masks = intel_i810_masks,
1783 .agp_enable = intel_i810_agp_enable,
1784 .cache_flush = global_cache_flush,
1785 .create_gatt_table = intel_i915_create_gatt_table,
1786 .free_gatt_table = intel_i830_free_gatt_table,
1787 .insert_memory = intel_i915_insert_entries,
1788 .remove_memory = intel_i915_remove_entries,
1789 .alloc_by_type = intel_i830_alloc_by_type,
1790 .free_by_type = intel_i810_free_by_type,
1791 .agp_alloc_page = agp_generic_alloc_page,
1792 .agp_destroy_page = agp_generic_destroy_page,
1793 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
1794 };
1795
1796 static int find_gmch(u16 device)
1797 {
1798 struct pci_dev *gmch_device;
1799
1800 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL);
1801 if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) {
1802 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL,
1803 device, gmch_device);
1804 }
1805
1806 if (!gmch_device)
1807 return 0;
1808
1809 intel_private.pcidev = gmch_device;
1810 return 1;
1811 }
1812
1813 /* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of
1814 * driver and gmch_driver must be non-null, and find_gmch will determine
1815 * which one should be used if a gmch_chip_id is present.
1816 */
1817 static const struct intel_driver_description {
1818 unsigned int chip_id;
1819 unsigned int gmch_chip_id;
1820 unsigned int multi_gmch_chip; /* if we have more gfx chip type on this HB. */
1821 char *name;
1822 const struct agp_bridge_driver *driver;
1823 const struct agp_bridge_driver *gmch_driver;
1824 } intel_agp_chipsets[] = {
1825 { PCI_DEVICE_ID_INTEL_82443LX_0, 0, 0, "440LX", &intel_generic_driver, NULL },
1826 { PCI_DEVICE_ID_INTEL_82443BX_0, 0, 0, "440BX", &intel_generic_driver, NULL },
1827 { PCI_DEVICE_ID_INTEL_82443GX_0, 0, 0, "440GX", &intel_generic_driver, NULL },
1828 { PCI_DEVICE_ID_INTEL_82810_MC1, PCI_DEVICE_ID_INTEL_82810_IG1, 0, "i810",
1829 NULL, &intel_810_driver },
1830 { PCI_DEVICE_ID_INTEL_82810_MC3, PCI_DEVICE_ID_INTEL_82810_IG3, 0, "i810",
1831 NULL, &intel_810_driver },
1832 { PCI_DEVICE_ID_INTEL_82810E_MC, PCI_DEVICE_ID_INTEL_82810E_IG, 0, "i810",
1833 NULL, &intel_810_driver },
1834 { PCI_DEVICE_ID_INTEL_82815_MC, PCI_DEVICE_ID_INTEL_82815_CGC, 0, "i815",
1835 &intel_815_driver, &intel_810_driver },
1836 { PCI_DEVICE_ID_INTEL_82820_HB, 0, 0, "i820", &intel_820_driver, NULL },
1837 { PCI_DEVICE_ID_INTEL_82820_UP_HB, 0, 0, "i820", &intel_820_driver, NULL },
1838 { PCI_DEVICE_ID_INTEL_82830_HB, PCI_DEVICE_ID_INTEL_82830_CGC, 0, "830M",
1839 &intel_830mp_driver, &intel_830_driver },
1840 { PCI_DEVICE_ID_INTEL_82840_HB, 0, 0, "i840", &intel_840_driver, NULL },
1841 { PCI_DEVICE_ID_INTEL_82845_HB, 0, 0, "845G", &intel_845_driver, NULL },
1842 { PCI_DEVICE_ID_INTEL_82845G_HB, PCI_DEVICE_ID_INTEL_82845G_IG, 0, "830M",
1843 &intel_845_driver, &intel_830_driver },
1844 { PCI_DEVICE_ID_INTEL_82850_HB, 0, 0, "i850", &intel_850_driver, NULL },
1845 { PCI_DEVICE_ID_INTEL_82855PM_HB, 0, 0, "855PM", &intel_845_driver, NULL },
1846 { PCI_DEVICE_ID_INTEL_82855GM_HB, PCI_DEVICE_ID_INTEL_82855GM_IG, 0, "855GM",
1847 &intel_845_driver, &intel_830_driver },
1848 { PCI_DEVICE_ID_INTEL_82860_HB, 0, 0, "i860", &intel_860_driver, NULL },
1849 { PCI_DEVICE_ID_INTEL_82865_HB, PCI_DEVICE_ID_INTEL_82865_IG, 0, "865",
1850 &intel_845_driver, &intel_830_driver },
1851 { PCI_DEVICE_ID_INTEL_82875_HB, 0, 0, "i875", &intel_845_driver, NULL },
1852 { PCI_DEVICE_ID_INTEL_82915G_HB, PCI_DEVICE_ID_INTEL_82915G_IG, 0, "915G",
1853 NULL, &intel_915_driver },
1854 { PCI_DEVICE_ID_INTEL_82915GM_HB, PCI_DEVICE_ID_INTEL_82915GM_IG, 0, "915GM",
1855 NULL, &intel_915_driver },
1856 { PCI_DEVICE_ID_INTEL_82945G_HB, PCI_DEVICE_ID_INTEL_82945G_IG, 0, "945G",
1857 NULL, &intel_915_driver },
1858 { PCI_DEVICE_ID_INTEL_82945GM_HB, PCI_DEVICE_ID_INTEL_82945GM_IG, 0, "945GM",
1859 NULL, &intel_915_driver },
1860 { PCI_DEVICE_ID_INTEL_82945GME_HB, PCI_DEVICE_ID_INTEL_82945GME_IG, 0, "945GME",
1861 NULL, &intel_915_driver },
1862 { PCI_DEVICE_ID_INTEL_82946GZ_HB, PCI_DEVICE_ID_INTEL_82946GZ_IG, 0, "946GZ",
1863 NULL, &intel_i965_driver },
1864 { PCI_DEVICE_ID_INTEL_82965G_1_HB, PCI_DEVICE_ID_INTEL_82965G_1_IG, 0, "965G",
1865 NULL, &intel_i965_driver },
1866 { PCI_DEVICE_ID_INTEL_82965Q_HB, PCI_DEVICE_ID_INTEL_82965Q_IG, 0, "965Q",
1867 NULL, &intel_i965_driver },
1868 { PCI_DEVICE_ID_INTEL_82965G_HB, PCI_DEVICE_ID_INTEL_82965G_IG, 0, "965G",
1869 NULL, &intel_i965_driver },
1870 { PCI_DEVICE_ID_INTEL_82965GM_HB, PCI_DEVICE_ID_INTEL_82965GM_IG, 0, "965GM",
1871 NULL, &intel_i965_driver },
1872 { PCI_DEVICE_ID_INTEL_82965GME_HB, PCI_DEVICE_ID_INTEL_82965GME_IG, 0, "965GME/GLE",
1873 NULL, &intel_i965_driver },
1874 { PCI_DEVICE_ID_INTEL_7505_0, 0, 0, "E7505", &intel_7505_driver, NULL },
1875 { PCI_DEVICE_ID_INTEL_7205_0, 0, 0, "E7205", &intel_7505_driver, NULL },
1876 { PCI_DEVICE_ID_INTEL_G33_HB, PCI_DEVICE_ID_INTEL_G33_IG, 0, "G33",
1877 NULL, &intel_g33_driver },
1878 { PCI_DEVICE_ID_INTEL_Q35_HB, PCI_DEVICE_ID_INTEL_Q35_IG, 0, "Q35",
1879 NULL, &intel_g33_driver },
1880 { PCI_DEVICE_ID_INTEL_Q33_HB, PCI_DEVICE_ID_INTEL_Q33_IG, 0, "Q33",
1881 NULL, &intel_g33_driver },
1882 { 0, 0, 0, NULL, NULL, NULL }
1883 };
1884
1885 static int __devinit agp_intel_probe(struct pci_dev *pdev,
1886 const struct pci_device_id *ent)
1887 {
1888 struct agp_bridge_data *bridge;
1889 u8 cap_ptr = 0;
1890 struct resource *r;
1891 int i;
1892
1893 cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
1894
1895 bridge = agp_alloc_bridge();
1896 if (!bridge)
1897 return -ENOMEM;
1898
1899 for (i = 0; intel_agp_chipsets[i].name != NULL; i++) {
1900 /* In case that multiple models of gfx chip may
1901 stand on same host bridge type, this can be
1902 sure we detect the right IGD. */
1903 if (pdev->device == intel_agp_chipsets[i].chip_id) {
1904 if ((intel_agp_chipsets[i].gmch_chip_id != 0) &&
1905 find_gmch(intel_agp_chipsets[i].gmch_chip_id)) {
1906 bridge->driver =
1907 intel_agp_chipsets[i].gmch_driver;
1908 break;
1909 } else if (intel_agp_chipsets[i].multi_gmch_chip) {
1910 continue;
1911 } else {
1912 bridge->driver = intel_agp_chipsets[i].driver;
1913 break;
1914 }
1915 }
1916 }
1917
1918 if (intel_agp_chipsets[i].name == NULL) {
1919 if (cap_ptr)
1920 printk(KERN_WARNING PFX "Unsupported Intel chipset"
1921 "(device id: %04x)\n", pdev->device);
1922 agp_put_bridge(bridge);
1923 return -ENODEV;
1924 }
1925
1926 if (bridge->driver == NULL) {
1927 /* bridge has no AGP and no IGD detected */
1928 if (cap_ptr)
1929 printk(KERN_WARNING PFX "Failed to find bridge device "
1930 "(chip_id: %04x)\n",
1931 intel_agp_chipsets[i].gmch_chip_id);
1932 agp_put_bridge(bridge);
1933 return -ENODEV;
1934 }
1935
1936 bridge->dev = pdev;
1937 bridge->capndx = cap_ptr;
1938 bridge->dev_private_data = &intel_private;
1939
1940 printk(KERN_INFO PFX "Detected an Intel %s Chipset.\n",
1941 intel_agp_chipsets[i].name);
1942
1943 /*
1944 * The following fixes the case where the BIOS has "forgotten" to
1945 * provide an address range for the GART.
1946 * 20030610 - hamish@zot.org
1947 */
1948 r = &pdev->resource[0];
1949 if (!r->start && r->end) {
1950 if (pci_assign_resource(pdev, 0)) {
1951 printk(KERN_ERR PFX "could not assign resource 0\n");
1952 agp_put_bridge(bridge);
1953 return -ENODEV;
1954 }
1955 }
1956
1957 /*
1958 * If the device has not been properly setup, the following will catch
1959 * the problem and should stop the system from crashing.
1960 * 20030610 - hamish@zot.org
1961 */
1962 if (pci_enable_device(pdev)) {
1963 printk(KERN_ERR PFX "Unable to Enable PCI device\n");
1964 agp_put_bridge(bridge);
1965 return -ENODEV;
1966 }
1967
1968 /* Fill in the mode register */
1969 if (cap_ptr) {
1970 pci_read_config_dword(pdev,
1971 bridge->capndx+PCI_AGP_STATUS,
1972 &bridge->mode);
1973 }
1974
1975 pci_set_drvdata(pdev, bridge);
1976 return agp_add_bridge(bridge);
1977 }
1978
1979 static void __devexit agp_intel_remove(struct pci_dev *pdev)
1980 {
1981 struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
1982
1983 agp_remove_bridge(bridge);
1984
1985 if (intel_private.pcidev)
1986 pci_dev_put(intel_private.pcidev);
1987
1988 agp_put_bridge(bridge);
1989 }
1990
1991 #ifdef CONFIG_PM
1992 static int agp_intel_resume(struct pci_dev *pdev)
1993 {
1994 struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
1995
1996 pci_restore_state(pdev);
1997
1998 /* We should restore our graphics device's config space,
1999 * as host bridge (00:00) resumes before graphics device (02:00),
2000 * then our access to its pci space can work right.
2001 */
2002 if (intel_private.pcidev)
2003 pci_restore_state(intel_private.pcidev);
2004
2005 if (bridge->driver == &intel_generic_driver)
2006 intel_configure();
2007 else if (bridge->driver == &intel_850_driver)
2008 intel_850_configure();
2009 else if (bridge->driver == &intel_845_driver)
2010 intel_845_configure();
2011 else if (bridge->driver == &intel_830mp_driver)
2012 intel_830mp_configure();
2013 else if (bridge->driver == &intel_915_driver)
2014 intel_i915_configure();
2015 else if (bridge->driver == &intel_830_driver)
2016 intel_i830_configure();
2017 else if (bridge->driver == &intel_810_driver)
2018 intel_i810_configure();
2019 else if (bridge->driver == &intel_i965_driver)
2020 intel_i915_configure();
2021
2022 return 0;
2023 }
2024 #endif
2025
2026 static struct pci_device_id agp_intel_pci_table[] = {
2027 #define ID(x) \
2028 { \
2029 .class = (PCI_CLASS_BRIDGE_HOST << 8), \
2030 .class_mask = ~0, \
2031 .vendor = PCI_VENDOR_ID_INTEL, \
2032 .device = x, \
2033 .subvendor = PCI_ANY_ID, \
2034 .subdevice = PCI_ANY_ID, \
2035 }
2036 ID(PCI_DEVICE_ID_INTEL_82443LX_0),
2037 ID(PCI_DEVICE_ID_INTEL_82443BX_0),
2038 ID(PCI_DEVICE_ID_INTEL_82443GX_0),
2039 ID(PCI_DEVICE_ID_INTEL_82810_MC1),
2040 ID(PCI_DEVICE_ID_INTEL_82810_MC3),
2041 ID(PCI_DEVICE_ID_INTEL_82810E_MC),
2042 ID(PCI_DEVICE_ID_INTEL_82815_MC),
2043 ID(PCI_DEVICE_ID_INTEL_82820_HB),
2044 ID(PCI_DEVICE_ID_INTEL_82820_UP_HB),
2045 ID(PCI_DEVICE_ID_INTEL_82830_HB),
2046 ID(PCI_DEVICE_ID_INTEL_82840_HB),
2047 ID(PCI_DEVICE_ID_INTEL_82845_HB),
2048 ID(PCI_DEVICE_ID_INTEL_82845G_HB),
2049 ID(PCI_DEVICE_ID_INTEL_82850_HB),
2050 ID(PCI_DEVICE_ID_INTEL_82855PM_HB),
2051 ID(PCI_DEVICE_ID_INTEL_82855GM_HB),
2052 ID(PCI_DEVICE_ID_INTEL_82860_HB),
2053 ID(PCI_DEVICE_ID_INTEL_82865_HB),
2054 ID(PCI_DEVICE_ID_INTEL_82875_HB),
2055 ID(PCI_DEVICE_ID_INTEL_7505_0),
2056 ID(PCI_DEVICE_ID_INTEL_7205_0),
2057 ID(PCI_DEVICE_ID_INTEL_82915G_HB),
2058 ID(PCI_DEVICE_ID_INTEL_82915GM_HB),
2059 ID(PCI_DEVICE_ID_INTEL_82945G_HB),
2060 ID(PCI_DEVICE_ID_INTEL_82945GM_HB),
2061 ID(PCI_DEVICE_ID_INTEL_82945GME_HB),
2062 ID(PCI_DEVICE_ID_INTEL_82946GZ_HB),
2063 ID(PCI_DEVICE_ID_INTEL_82965G_1_HB),
2064 ID(PCI_DEVICE_ID_INTEL_82965Q_HB),
2065 ID(PCI_DEVICE_ID_INTEL_82965G_HB),
2066 ID(PCI_DEVICE_ID_INTEL_82965GM_HB),
2067 ID(PCI_DEVICE_ID_INTEL_82965GME_HB),
2068 ID(PCI_DEVICE_ID_INTEL_G33_HB),
2069 ID(PCI_DEVICE_ID_INTEL_Q35_HB),
2070 ID(PCI_DEVICE_ID_INTEL_Q33_HB),
2071 { }
2072 };
2073
2074 MODULE_DEVICE_TABLE(pci, agp_intel_pci_table);
2075
2076 static struct pci_driver agp_intel_pci_driver = {
2077 .name = "agpgart-intel",
2078 .id_table = agp_intel_pci_table,
2079 .probe = agp_intel_probe,
2080 .remove = __devexit_p(agp_intel_remove),
2081 #ifdef CONFIG_PM
2082 .resume = agp_intel_resume,
2083 #endif
2084 };
2085
2086 static int __init agp_intel_init(void)
2087 {
2088 if (agp_off)
2089 return -EINVAL;
2090 return pci_register_driver(&agp_intel_pci_driver);
2091 }
2092
2093 static void __exit agp_intel_cleanup(void)
2094 {
2095 pci_unregister_driver(&agp_intel_pci_driver);
2096 }
2097
2098 module_init(agp_intel_init);
2099 module_exit(agp_intel_cleanup);
2100
2101 MODULE_AUTHOR("Dave Jones <davej@codemonkey.org.uk>");
2102 MODULE_LICENSE("GPL and additional rights");
USB Experimental Work