3 * hda_intel.c - Implementation of primary alsa driver code base for Intel HD Audio.
5 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
8 * PeiSen Hou <pshou@realtek.com.tw>
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the Free
12 * Software Foundation; either version 2 of the License, or (at your option)
15 * This program is distributed in the hope that it will be useful, but WITHOUT
16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
20 * You should have received a copy of the GNU General Public License along with
21 * this program; if not, write to the Free Software Foundation, Inc., 59
22 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
26 * Matt Jared matt.jared@intel.com
27 * Andy Kopp andy.kopp@intel.com
28 * Dan Kogan dan.d.kogan@intel.com
32 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
36 #include <sound/driver.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/kernel.h>
41 #include <linux/module.h>
42 #include <linux/moduleparam.h>
43 #include <linux/init.h>
44 #include <linux/slab.h>
45 #include <linux/pci.h>
46 #include <linux/mutex.h>
47 #include <sound/core.h>
48 #include <sound/initval.h>
49 #include "hda_codec.h"
52 static int index
= SNDRV_DEFAULT_IDX1
;
53 static char *id
= SNDRV_DEFAULT_STR1
;
55 static int position_fix
;
56 static int probe_mask
= -1;
57 static int single_cmd
;
58 static int enable_msi
;
60 module_param(index
, int, 0444);
61 MODULE_PARM_DESC(index
, "Index value for Intel HD audio interface.");
62 module_param(id
, charp
, 0444);
63 MODULE_PARM_DESC(id
, "ID string for Intel HD audio interface.");
64 module_param(model
, charp
, 0444);
65 MODULE_PARM_DESC(model
, "Use the given board model.");
66 module_param(position_fix
, int, 0444);
67 MODULE_PARM_DESC(position_fix
, "Fix DMA pointer (0 = auto, 1 = none, 2 = POSBUF, 3 = FIFO size).");
68 module_param(probe_mask
, int, 0444);
69 MODULE_PARM_DESC(probe_mask
, "Bitmask to probe codecs (default = -1).");
70 module_param(single_cmd
, bool, 0444);
71 MODULE_PARM_DESC(single_cmd
, "Use single command to communicate with codecs (for debugging only).");
72 module_param(enable_msi
, int, 0);
73 MODULE_PARM_DESC(enable_msi
, "Enable Message Signaled Interrupt (MSI)");
76 /* just for backward compatibility */
78 module_param(enable
, bool, 0444);
80 MODULE_LICENSE("GPL");
81 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
94 MODULE_DESCRIPTION("Intel HDA driver");
96 #define SFX "hda-intel: "
101 #define ICH6_REG_GCAP 0x00
102 #define ICH6_REG_VMIN 0x02
103 #define ICH6_REG_VMAJ 0x03
104 #define ICH6_REG_OUTPAY 0x04
105 #define ICH6_REG_INPAY 0x06
106 #define ICH6_REG_GCTL 0x08
107 #define ICH6_REG_WAKEEN 0x0c
108 #define ICH6_REG_STATESTS 0x0e
109 #define ICH6_REG_GSTS 0x10
110 #define ICH6_REG_INTCTL 0x20
111 #define ICH6_REG_INTSTS 0x24
112 #define ICH6_REG_WALCLK 0x30
113 #define ICH6_REG_SYNC 0x34
114 #define ICH6_REG_CORBLBASE 0x40
115 #define ICH6_REG_CORBUBASE 0x44
116 #define ICH6_REG_CORBWP 0x48
117 #define ICH6_REG_CORBRP 0x4A
118 #define ICH6_REG_CORBCTL 0x4c
119 #define ICH6_REG_CORBSTS 0x4d
120 #define ICH6_REG_CORBSIZE 0x4e
122 #define ICH6_REG_RIRBLBASE 0x50
123 #define ICH6_REG_RIRBUBASE 0x54
124 #define ICH6_REG_RIRBWP 0x58
125 #define ICH6_REG_RINTCNT 0x5a
126 #define ICH6_REG_RIRBCTL 0x5c
127 #define ICH6_REG_RIRBSTS 0x5d
128 #define ICH6_REG_RIRBSIZE 0x5e
130 #define ICH6_REG_IC 0x60
131 #define ICH6_REG_IR 0x64
132 #define ICH6_REG_IRS 0x68
133 #define ICH6_IRS_VALID (1<<1)
134 #define ICH6_IRS_BUSY (1<<0)
136 #define ICH6_REG_DPLBASE 0x70
137 #define ICH6_REG_DPUBASE 0x74
138 #define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
140 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
141 enum { SDI0
, SDI1
, SDI2
, SDI3
, SDO0
, SDO1
, SDO2
, SDO3
};
143 /* stream register offsets from stream base */
144 #define ICH6_REG_SD_CTL 0x00
145 #define ICH6_REG_SD_STS 0x03
146 #define ICH6_REG_SD_LPIB 0x04
147 #define ICH6_REG_SD_CBL 0x08
148 #define ICH6_REG_SD_LVI 0x0c
149 #define ICH6_REG_SD_FIFOW 0x0e
150 #define ICH6_REG_SD_FIFOSIZE 0x10
151 #define ICH6_REG_SD_FORMAT 0x12
152 #define ICH6_REG_SD_BDLPL 0x18
153 #define ICH6_REG_SD_BDLPU 0x1c
156 #define ICH6_PCIREG_TCSEL 0x44
162 /* max number of SDs */
163 /* ICH, ATI and VIA have 4 playback and 4 capture */
164 #define ICH6_CAPTURE_INDEX 0
165 #define ICH6_NUM_CAPTURE 4
166 #define ICH6_PLAYBACK_INDEX 4
167 #define ICH6_NUM_PLAYBACK 4
169 /* ULI has 6 playback and 5 capture */
170 #define ULI_CAPTURE_INDEX 0
171 #define ULI_NUM_CAPTURE 5
172 #define ULI_PLAYBACK_INDEX 5
173 #define ULI_NUM_PLAYBACK 6
175 /* ATI HDMI has 1 playback and 0 capture */
176 #define ATIHDMI_CAPTURE_INDEX 0
177 #define ATIHDMI_NUM_CAPTURE 0
178 #define ATIHDMI_PLAYBACK_INDEX 0
179 #define ATIHDMI_NUM_PLAYBACK 1
181 /* this number is statically defined for simplicity */
182 #define MAX_AZX_DEV 16
184 /* max number of fragments - we may use more if allocating more pages for BDL */
185 #define BDL_SIZE PAGE_ALIGN(8192)
186 #define AZX_MAX_FRAG (BDL_SIZE / (MAX_AZX_DEV * 16))
187 /* max buffer size - no h/w limit, you can increase as you like */
188 #define AZX_MAX_BUF_SIZE (1024*1024*1024)
189 /* max number of PCM devics per card */
190 #define AZX_MAX_AUDIO_PCMS 6
191 #define AZX_MAX_MODEM_PCMS 2
192 #define AZX_MAX_PCMS (AZX_MAX_AUDIO_PCMS + AZX_MAX_MODEM_PCMS)
194 /* RIRB int mask: overrun[2], response[0] */
195 #define RIRB_INT_RESPONSE 0x01
196 #define RIRB_INT_OVERRUN 0x04
197 #define RIRB_INT_MASK 0x05
199 /* STATESTS int mask: SD2,SD1,SD0 */
200 #define STATESTS_INT_MASK 0x07
201 #define AZX_MAX_CODECS 4
204 #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
205 #define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
206 #define SD_CTL_STREAM_TAG_MASK (0xf << 20)
207 #define SD_CTL_STREAM_TAG_SHIFT 20
209 /* SD_CTL and SD_STS */
210 #define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
211 #define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
212 #define SD_INT_COMPLETE 0x04 /* completion interrupt */
213 #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|SD_INT_COMPLETE)
216 #define SD_STS_FIFO_READY 0x20 /* FIFO ready */
218 /* INTCTL and INTSTS */
219 #define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
220 #define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
221 #define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
223 /* GCTL unsolicited response enable bit */
224 #define ICH6_GCTL_UREN (1<<8)
227 #define ICH6_GCTL_RESET (1<<0)
229 /* CORB/RIRB control, read/write pointer */
230 #define ICH6_RBCTL_DMA_EN 0x02 /* enable DMA */
231 #define ICH6_RBCTL_IRQ_EN 0x01 /* enable IRQ */
232 #define ICH6_RBRWP_CLR 0x8000 /* read/write pointer clear */
233 /* below are so far hardcoded - should read registers in future */
234 #define ICH6_MAX_CORB_ENTRIES 256
235 #define ICH6_MAX_RIRB_ENTRIES 256
237 /* position fix mode */
245 /* Defines for ATI HD Audio support in SB450 south bridge */
246 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
247 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
249 /* Defines for Nvidia HDA support */
250 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
251 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
257 u32
*bdl
; /* virtual address of the BDL */
258 dma_addr_t bdl_addr
; /* physical address of the BDL */
259 u32
*posbuf
; /* position buffer pointer */
261 unsigned int bufsize
; /* size of the play buffer in bytes */
262 unsigned int fragsize
; /* size of each period in bytes */
263 unsigned int frags
; /* number for period in the play buffer */
264 unsigned int fifo_size
; /* FIFO size */
266 void __iomem
*sd_addr
; /* stream descriptor pointer */
268 u32 sd_int_sta_mask
; /* stream int status mask */
271 struct snd_pcm_substream
*substream
; /* assigned substream, set in PCM open */
272 unsigned int format_val
; /* format value to be set in the controller and the codec */
273 unsigned char stream_tag
; /* assigned stream */
274 unsigned char index
; /* stream index */
275 /* for sanity check of position buffer */
276 unsigned int period_intr
;
278 unsigned int opened
:1;
279 unsigned int running
:1;
284 u32
*buf
; /* CORB/RIRB buffer
285 * Each CORB entry is 4byte, RIRB is 8byte
287 dma_addr_t addr
; /* physical address of CORB/RIRB buffer */
289 unsigned short rp
, wp
; /* read/write pointers */
290 int cmds
; /* number of pending requests */
291 u32 res
; /* last read value */
295 struct snd_card
*card
;
298 /* chip type specific */
300 int playback_streams
;
301 int playback_index_offset
;
303 int capture_index_offset
;
308 void __iomem
*remap_addr
;
313 struct mutex open_mutex
;
315 /* streams (x num_streams) */
316 struct azx_dev
*azx_dev
;
319 unsigned int pcm_devs
;
320 struct snd_pcm
*pcm
[AZX_MAX_PCMS
];
323 unsigned short codec_mask
;
330 /* BDL, CORB/RIRB and position buffers */
331 struct snd_dma_buffer bdl
;
332 struct snd_dma_buffer rb
;
333 struct snd_dma_buffer posbuf
;
337 unsigned int initialized
:1;
338 unsigned int single_cmd
:1;
339 unsigned int polling_mode
:1;
354 static char *driver_short_names
[] __devinitdata
= {
355 [AZX_DRIVER_ICH
] = "HDA Intel",
356 [AZX_DRIVER_ATI
] = "HDA ATI SB",
357 [AZX_DRIVER_ATIHDMI
] = "HDA ATI HDMI",
358 [AZX_DRIVER_VIA
] = "HDA VIA VT82xx",
359 [AZX_DRIVER_SIS
] = "HDA SIS966",
360 [AZX_DRIVER_ULI
] = "HDA ULI M5461",
361 [AZX_DRIVER_NVIDIA
] = "HDA NVidia",
365 * macros for easy use
367 #define azx_writel(chip,reg,value) \
368 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
369 #define azx_readl(chip,reg) \
370 readl((chip)->remap_addr + ICH6_REG_##reg)
371 #define azx_writew(chip,reg,value) \
372 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
373 #define azx_readw(chip,reg) \
374 readw((chip)->remap_addr + ICH6_REG_##reg)
375 #define azx_writeb(chip,reg,value) \
376 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
377 #define azx_readb(chip,reg) \
378 readb((chip)->remap_addr + ICH6_REG_##reg)
380 #define azx_sd_writel(dev,reg,value) \
381 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
382 #define azx_sd_readl(dev,reg) \
383 readl((dev)->sd_addr + ICH6_REG_##reg)
384 #define azx_sd_writew(dev,reg,value) \
385 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
386 #define azx_sd_readw(dev,reg) \
387 readw((dev)->sd_addr + ICH6_REG_##reg)
388 #define azx_sd_writeb(dev,reg,value) \
389 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
390 #define azx_sd_readb(dev,reg) \
391 readb((dev)->sd_addr + ICH6_REG_##reg)
393 /* for pcm support */
394 #define get_azx_dev(substream) (substream->runtime->private_data)
396 /* Get the upper 32bit of the given dma_addr_t
397 * Compiler should optimize and eliminate the code if dma_addr_t is 32bit
399 #define upper_32bit(addr) (sizeof(addr) > 4 ? (u32)((addr) >> 32) : (u32)0)
401 static int azx_acquire_irq(struct azx
*chip
, int do_disconnect
);
404 * Interface for HD codec
408 * CORB / RIRB interface
410 static int azx_alloc_cmd_io(struct azx
*chip
)
414 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
415 err
= snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV
, snd_dma_pci_data(chip
->pci
),
416 PAGE_SIZE
, &chip
->rb
);
418 snd_printk(KERN_ERR SFX
"cannot allocate CORB/RIRB\n");
424 static void azx_init_cmd_io(struct azx
*chip
)
427 chip
->corb
.addr
= chip
->rb
.addr
;
428 chip
->corb
.buf
= (u32
*)chip
->rb
.area
;
429 azx_writel(chip
, CORBLBASE
, (u32
)chip
->corb
.addr
);
430 azx_writel(chip
, CORBUBASE
, upper_32bit(chip
->corb
.addr
));
432 /* set the corb size to 256 entries (ULI requires explicitly) */
433 azx_writeb(chip
, CORBSIZE
, 0x02);
434 /* set the corb write pointer to 0 */
435 azx_writew(chip
, CORBWP
, 0);
436 /* reset the corb hw read pointer */
437 azx_writew(chip
, CORBRP
, ICH6_RBRWP_CLR
);
438 /* enable corb dma */
439 azx_writeb(chip
, CORBCTL
, ICH6_RBCTL_DMA_EN
);
442 chip
->rirb
.addr
= chip
->rb
.addr
+ 2048;
443 chip
->rirb
.buf
= (u32
*)(chip
->rb
.area
+ 2048);
444 azx_writel(chip
, RIRBLBASE
, (u32
)chip
->rirb
.addr
);
445 azx_writel(chip
, RIRBUBASE
, upper_32bit(chip
->rirb
.addr
));
447 /* set the rirb size to 256 entries (ULI requires explicitly) */
448 azx_writeb(chip
, RIRBSIZE
, 0x02);
449 /* reset the rirb hw write pointer */
450 azx_writew(chip
, RIRBWP
, ICH6_RBRWP_CLR
);
451 /* set N=1, get RIRB response interrupt for new entry */
452 azx_writew(chip
, RINTCNT
, 1);
453 /* enable rirb dma and response irq */
454 azx_writeb(chip
, RIRBCTL
, ICH6_RBCTL_DMA_EN
| ICH6_RBCTL_IRQ_EN
);
455 chip
->rirb
.rp
= chip
->rirb
.cmds
= 0;
458 static void azx_free_cmd_io(struct azx
*chip
)
460 /* disable ringbuffer DMAs */
461 azx_writeb(chip
, RIRBCTL
, 0);
462 azx_writeb(chip
, CORBCTL
, 0);
466 static int azx_corb_send_cmd(struct hda_codec
*codec
, hda_nid_t nid
, int direct
,
467 unsigned int verb
, unsigned int para
)
469 struct azx
*chip
= codec
->bus
->private_data
;
473 val
= (u32
)(codec
->addr
& 0x0f) << 28;
474 val
|= (u32
)direct
<< 27;
475 val
|= (u32
)nid
<< 20;
479 /* add command to corb */
480 wp
= azx_readb(chip
, CORBWP
);
482 wp
%= ICH6_MAX_CORB_ENTRIES
;
484 spin_lock_irq(&chip
->reg_lock
);
486 chip
->corb
.buf
[wp
] = cpu_to_le32(val
);
487 azx_writel(chip
, CORBWP
, wp
);
488 spin_unlock_irq(&chip
->reg_lock
);
493 #define ICH6_RIRB_EX_UNSOL_EV (1<<4)
495 /* retrieve RIRB entry - called from interrupt handler */
496 static void azx_update_rirb(struct azx
*chip
)
501 wp
= azx_readb(chip
, RIRBWP
);
502 if (wp
== chip
->rirb
.wp
)
506 while (chip
->rirb
.rp
!= wp
) {
508 chip
->rirb
.rp
%= ICH6_MAX_RIRB_ENTRIES
;
510 rp
= chip
->rirb
.rp
<< 1; /* an RIRB entry is 8-bytes */
511 res_ex
= le32_to_cpu(chip
->rirb
.buf
[rp
+ 1]);
512 res
= le32_to_cpu(chip
->rirb
.buf
[rp
]);
513 if (res_ex
& ICH6_RIRB_EX_UNSOL_EV
)
514 snd_hda_queue_unsol_event(chip
->bus
, res
, res_ex
);
515 else if (chip
->rirb
.cmds
) {
517 chip
->rirb
.res
= res
;
522 /* receive a response */
523 static unsigned int azx_rirb_get_response(struct hda_codec
*codec
)
525 struct azx
*chip
= codec
->bus
->private_data
;
526 unsigned long timeout
;
529 timeout
= jiffies
+ msecs_to_jiffies(1000);
531 if (chip
->polling_mode
) {
532 spin_lock_irq(&chip
->reg_lock
);
533 azx_update_rirb(chip
);
534 spin_unlock_irq(&chip
->reg_lock
);
536 if (! chip
->rirb
.cmds
)
537 return chip
->rirb
.res
; /* the last value */
538 schedule_timeout_interruptible(1);
539 } while (time_after_eq(timeout
, jiffies
));
542 snd_printk(KERN_WARNING
"hda_intel: No response from codec, "
543 "disabling MSI...\n");
544 free_irq(chip
->irq
, chip
);
546 pci_disable_msi(chip
->pci
);
548 if (azx_acquire_irq(chip
, 1) < 0)
553 if (!chip
->polling_mode
) {
554 snd_printk(KERN_WARNING
"hda_intel: azx_get_response timeout, "
555 "switching to polling mode...\n");
556 chip
->polling_mode
= 1;
560 snd_printk(KERN_ERR
"hda_intel: azx_get_response timeout, "
561 "switching to single_cmd mode...\n");
562 chip
->rirb
.rp
= azx_readb(chip
, RIRBWP
);
564 /* switch to single_cmd mode */
565 chip
->single_cmd
= 1;
566 azx_free_cmd_io(chip
);
571 * Use the single immediate command instead of CORB/RIRB for simplicity
573 * Note: according to Intel, this is not preferred use. The command was
574 * intended for the BIOS only, and may get confused with unsolicited
575 * responses. So, we shouldn't use it for normal operation from the
577 * I left the codes, however, for debugging/testing purposes.
581 static int azx_single_send_cmd(struct hda_codec
*codec
, hda_nid_t nid
,
582 int direct
, unsigned int verb
,
585 struct azx
*chip
= codec
->bus
->private_data
;
589 val
= (u32
)(codec
->addr
& 0x0f) << 28;
590 val
|= (u32
)direct
<< 27;
591 val
|= (u32
)nid
<< 20;
596 /* check ICB busy bit */
597 if (! (azx_readw(chip
, IRS
) & ICH6_IRS_BUSY
)) {
598 /* Clear IRV valid bit */
599 azx_writew(chip
, IRS
, azx_readw(chip
, IRS
) | ICH6_IRS_VALID
);
600 azx_writel(chip
, IC
, val
);
601 azx_writew(chip
, IRS
, azx_readw(chip
, IRS
) | ICH6_IRS_BUSY
);
606 snd_printd(SFX
"send_cmd timeout: IRS=0x%x, val=0x%x\n", azx_readw(chip
, IRS
), val
);
610 /* receive a response */
611 static unsigned int azx_single_get_response(struct hda_codec
*codec
)
613 struct azx
*chip
= codec
->bus
->private_data
;
617 /* check IRV busy bit */
618 if (azx_readw(chip
, IRS
) & ICH6_IRS_VALID
)
619 return azx_readl(chip
, IR
);
622 snd_printd(SFX
"get_response timeout: IRS=0x%x\n", azx_readw(chip
, IRS
));
623 return (unsigned int)-1;
627 * The below are the main callbacks from hda_codec.
629 * They are just the skeleton to call sub-callbacks according to the
630 * current setting of chip->single_cmd.
634 static int azx_send_cmd(struct hda_codec
*codec
, hda_nid_t nid
,
635 int direct
, unsigned int verb
,
638 struct azx
*chip
= codec
->bus
->private_data
;
639 if (chip
->single_cmd
)
640 return azx_single_send_cmd(codec
, nid
, direct
, verb
, para
);
642 return azx_corb_send_cmd(codec
, nid
, direct
, verb
, para
);
646 static unsigned int azx_get_response(struct hda_codec
*codec
)
648 struct azx
*chip
= codec
->bus
->private_data
;
649 if (chip
->single_cmd
)
650 return azx_single_get_response(codec
);
652 return azx_rirb_get_response(codec
);
656 /* reset codec link */
657 static int azx_reset(struct azx
*chip
)
661 /* reset controller */
662 azx_writel(chip
, GCTL
, azx_readl(chip
, GCTL
) & ~ICH6_GCTL_RESET
);
665 while (azx_readb(chip
, GCTL
) && --count
)
668 /* delay for >= 100us for codec PLL to settle per spec
669 * Rev 0.9 section 5.5.1
673 /* Bring controller out of reset */
674 azx_writeb(chip
, GCTL
, azx_readb(chip
, GCTL
) | ICH6_GCTL_RESET
);
677 while (!azx_readb(chip
, GCTL
) && --count
)
680 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
683 /* check to see if controller is ready */
684 if (!azx_readb(chip
, GCTL
)) {
685 snd_printd("azx_reset: controller not ready!\n");
689 /* Accept unsolicited responses */
690 azx_writel(chip
, GCTL
, azx_readl(chip
, GCTL
) | ICH6_GCTL_UREN
);
693 if (!chip
->codec_mask
) {
694 chip
->codec_mask
= azx_readw(chip
, STATESTS
);
695 snd_printdd("codec_mask = 0x%x\n", chip
->codec_mask
);
706 /* enable interrupts */
707 static void azx_int_enable(struct azx
*chip
)
709 /* enable controller CIE and GIE */
710 azx_writel(chip
, INTCTL
, azx_readl(chip
, INTCTL
) |
711 ICH6_INT_CTRL_EN
| ICH6_INT_GLOBAL_EN
);
714 /* disable interrupts */
715 static void azx_int_disable(struct azx
*chip
)
719 /* disable interrupts in stream descriptor */
720 for (i
= 0; i
< chip
->num_streams
; i
++) {
721 struct azx_dev
*azx_dev
= &chip
->azx_dev
[i
];
722 azx_sd_writeb(azx_dev
, SD_CTL
,
723 azx_sd_readb(azx_dev
, SD_CTL
) & ~SD_INT_MASK
);
726 /* disable SIE for all streams */
727 azx_writeb(chip
, INTCTL
, 0);
729 /* disable controller CIE and GIE */
730 azx_writel(chip
, INTCTL
, azx_readl(chip
, INTCTL
) &
731 ~(ICH6_INT_CTRL_EN
| ICH6_INT_GLOBAL_EN
));
734 /* clear interrupts */
735 static void azx_int_clear(struct azx
*chip
)
739 /* clear stream status */
740 for (i
= 0; i
< chip
->num_streams
; i
++) {
741 struct azx_dev
*azx_dev
= &chip
->azx_dev
[i
];
742 azx_sd_writeb(azx_dev
, SD_STS
, SD_INT_MASK
);
746 azx_writeb(chip
, STATESTS
, STATESTS_INT_MASK
);
748 /* clear rirb status */
749 azx_writeb(chip
, RIRBSTS
, RIRB_INT_MASK
);
751 /* clear int status */
752 azx_writel(chip
, INTSTS
, ICH6_INT_CTRL_EN
| ICH6_INT_ALL_STREAM
);
756 static void azx_stream_start(struct azx
*chip
, struct azx_dev
*azx_dev
)
759 azx_writeb(chip
, INTCTL
,
760 azx_readb(chip
, INTCTL
) | (1 << azx_dev
->index
));
761 /* set DMA start and interrupt mask */
762 azx_sd_writeb(azx_dev
, SD_CTL
, azx_sd_readb(azx_dev
, SD_CTL
) |
763 SD_CTL_DMA_START
| SD_INT_MASK
);
767 static void azx_stream_stop(struct azx
*chip
, struct azx_dev
*azx_dev
)
770 azx_sd_writeb(azx_dev
, SD_CTL
, azx_sd_readb(azx_dev
, SD_CTL
) &
771 ~(SD_CTL_DMA_START
| SD_INT_MASK
));
772 azx_sd_writeb(azx_dev
, SD_STS
, SD_INT_MASK
); /* to be sure */
774 azx_writeb(chip
, INTCTL
,
775 azx_readb(chip
, INTCTL
) & ~(1 << azx_dev
->index
));
780 * initialize the chip
782 static void azx_init_chip(struct azx
*chip
)
786 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
787 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
788 * Ensuring these bits are 0 clears playback static on some HD Audio codecs
790 pci_read_config_byte (chip
->pci
, ICH6_PCIREG_TCSEL
, ®
);
791 pci_write_config_byte(chip
->pci
, ICH6_PCIREG_TCSEL
, reg
& 0xf8);
793 /* reset controller */
796 /* initialize interrupts */
798 azx_int_enable(chip
);
800 /* initialize the codec command I/O */
801 if (!chip
->single_cmd
)
802 azx_init_cmd_io(chip
);
804 /* program the position buffer */
805 azx_writel(chip
, DPLBASE
, (u32
)chip
->posbuf
.addr
);
806 azx_writel(chip
, DPUBASE
, upper_32bit(chip
->posbuf
.addr
));
808 switch (chip
->driver_type
) {
810 /* For ATI SB450 azalia HD audio, we need to enable snoop */
811 pci_read_config_byte(chip
->pci
, ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR
,
813 pci_write_config_byte(chip
->pci
, ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR
,
814 (reg
& 0xf8) | ATI_SB450_HDAUDIO_ENABLE_SNOOP
);
816 case AZX_DRIVER_NVIDIA
:
817 /* For NVIDIA HDA, enable snoop */
818 pci_read_config_byte(chip
->pci
,NVIDIA_HDA_TRANSREG_ADDR
, ®
);
819 pci_write_config_byte(chip
->pci
,NVIDIA_HDA_TRANSREG_ADDR
,
820 (reg
& 0xf0) | NVIDIA_HDA_ENABLE_COHBITS
);
829 static irqreturn_t
azx_interrupt(int irq
, void *dev_id
)
831 struct azx
*chip
= dev_id
;
832 struct azx_dev
*azx_dev
;
836 spin_lock(&chip
->reg_lock
);
838 status
= azx_readl(chip
, INTSTS
);
840 spin_unlock(&chip
->reg_lock
);
844 for (i
= 0; i
< chip
->num_streams
; i
++) {
845 azx_dev
= &chip
->azx_dev
[i
];
846 if (status
& azx_dev
->sd_int_sta_mask
) {
847 azx_sd_writeb(azx_dev
, SD_STS
, SD_INT_MASK
);
848 if (azx_dev
->substream
&& azx_dev
->running
) {
849 azx_dev
->period_intr
++;
850 spin_unlock(&chip
->reg_lock
);
851 snd_pcm_period_elapsed(azx_dev
->substream
);
852 spin_lock(&chip
->reg_lock
);
858 status
= azx_readb(chip
, RIRBSTS
);
859 if (status
& RIRB_INT_MASK
) {
860 if (! chip
->single_cmd
&& (status
& RIRB_INT_RESPONSE
))
861 azx_update_rirb(chip
);
862 azx_writeb(chip
, RIRBSTS
, RIRB_INT_MASK
);
866 /* clear state status int */
867 if (azx_readb(chip
, STATESTS
) & 0x04)
868 azx_writeb(chip
, STATESTS
, 0x04);
870 spin_unlock(&chip
->reg_lock
);
879 static void azx_setup_periods(struct azx_dev
*azx_dev
)
881 u32
*bdl
= azx_dev
->bdl
;
882 dma_addr_t dma_addr
= azx_dev
->substream
->runtime
->dma_addr
;
885 /* reset BDL address */
886 azx_sd_writel(azx_dev
, SD_BDLPL
, 0);
887 azx_sd_writel(azx_dev
, SD_BDLPU
, 0);
889 /* program the initial BDL entries */
890 for (idx
= 0; idx
< azx_dev
->frags
; idx
++) {
891 unsigned int off
= idx
<< 2; /* 4 dword step */
892 dma_addr_t addr
= dma_addr
+ idx
* azx_dev
->fragsize
;
893 /* program the address field of the BDL entry */
894 bdl
[off
] = cpu_to_le32((u32
)addr
);
895 bdl
[off
+1] = cpu_to_le32(upper_32bit(addr
));
897 /* program the size field of the BDL entry */
898 bdl
[off
+2] = cpu_to_le32(azx_dev
->fragsize
);
900 /* program the IOC to enable interrupt when buffer completes */
901 bdl
[off
+3] = cpu_to_le32(0x01);
906 * set up the SD for streaming
908 static int azx_setup_controller(struct azx
*chip
, struct azx_dev
*azx_dev
)
913 /* make sure the run bit is zero for SD */
914 azx_sd_writeb(azx_dev
, SD_CTL
, azx_sd_readb(azx_dev
, SD_CTL
) & ~SD_CTL_DMA_START
);
916 azx_sd_writeb(azx_dev
, SD_CTL
, azx_sd_readb(azx_dev
, SD_CTL
) | SD_CTL_STREAM_RESET
);
919 while (!((val
= azx_sd_readb(azx_dev
, SD_CTL
)) & SD_CTL_STREAM_RESET
) &&
922 val
&= ~SD_CTL_STREAM_RESET
;
923 azx_sd_writeb(azx_dev
, SD_CTL
, val
);
927 /* waiting for hardware to report that the stream is out of reset */
928 while (((val
= azx_sd_readb(azx_dev
, SD_CTL
)) & SD_CTL_STREAM_RESET
) &&
932 /* program the stream_tag */
933 azx_sd_writel(azx_dev
, SD_CTL
,
934 (azx_sd_readl(azx_dev
, SD_CTL
) & ~SD_CTL_STREAM_TAG_MASK
) |
935 (azx_dev
->stream_tag
<< SD_CTL_STREAM_TAG_SHIFT
));
937 /* program the length of samples in cyclic buffer */
938 azx_sd_writel(azx_dev
, SD_CBL
, azx_dev
->bufsize
);
940 /* program the stream format */
941 /* this value needs to be the same as the one programmed */
942 azx_sd_writew(azx_dev
, SD_FORMAT
, azx_dev
->format_val
);
944 /* program the stream LVI (last valid index) of the BDL */
945 azx_sd_writew(azx_dev
, SD_LVI
, azx_dev
->frags
- 1);
947 /* program the BDL address */
948 /* lower BDL address */
949 azx_sd_writel(azx_dev
, SD_BDLPL
, (u32
)azx_dev
->bdl_addr
);
950 /* upper BDL address */
951 azx_sd_writel(azx_dev
, SD_BDLPU
, upper_32bit(azx_dev
->bdl_addr
));
953 /* enable the position buffer */
954 if (! (azx_readl(chip
, DPLBASE
) & ICH6_DPLBASE_ENABLE
))
955 azx_writel(chip
, DPLBASE
, (u32
)chip
->posbuf
.addr
| ICH6_DPLBASE_ENABLE
);
957 /* set the interrupt enable bits in the descriptor control register */
958 azx_sd_writel(azx_dev
, SD_CTL
, azx_sd_readl(azx_dev
, SD_CTL
) | SD_INT_MASK
);
965 * Codec initialization
968 static int __devinit
azx_codec_create(struct azx
*chip
, const char *model
)
970 struct hda_bus_template bus_temp
;
973 memset(&bus_temp
, 0, sizeof(bus_temp
));
974 bus_temp
.private_data
= chip
;
975 bus_temp
.modelname
= model
;
976 bus_temp
.pci
= chip
->pci
;
977 bus_temp
.ops
.command
= azx_send_cmd
;
978 bus_temp
.ops
.get_response
= azx_get_response
;
980 if ((err
= snd_hda_bus_new(chip
->card
, &bus_temp
, &chip
->bus
)) < 0)
984 for (c
= 0; c
< AZX_MAX_CODECS
; c
++) {
985 if ((chip
->codec_mask
& (1 << c
)) & probe_mask
) {
986 err
= snd_hda_codec_new(chip
->bus
, c
, NULL
);
993 snd_printk(KERN_ERR SFX
"no codecs initialized\n");
1005 /* assign a stream for the PCM */
1006 static inline struct azx_dev
*azx_assign_device(struct azx
*chip
, int stream
)
1009 if (stream
== SNDRV_PCM_STREAM_PLAYBACK
) {
1010 dev
= chip
->playback_index_offset
;
1011 nums
= chip
->playback_streams
;
1013 dev
= chip
->capture_index_offset
;
1014 nums
= chip
->capture_streams
;
1016 for (i
= 0; i
< nums
; i
++, dev
++)
1017 if (! chip
->azx_dev
[dev
].opened
) {
1018 chip
->azx_dev
[dev
].opened
= 1;
1019 return &chip
->azx_dev
[dev
];
1024 /* release the assigned stream */
1025 static inline void azx_release_device(struct azx_dev
*azx_dev
)
1027 azx_dev
->opened
= 0;
1030 static struct snd_pcm_hardware azx_pcm_hw
= {
1031 .info
= (SNDRV_PCM_INFO_MMAP
| SNDRV_PCM_INFO_INTERLEAVED
|
1032 SNDRV_PCM_INFO_BLOCK_TRANSFER
|
1033 SNDRV_PCM_INFO_MMAP_VALID
|
1034 /* No full-resume yet implemented */
1035 /* SNDRV_PCM_INFO_RESUME |*/
1036 SNDRV_PCM_INFO_PAUSE
),
1037 .formats
= SNDRV_PCM_FMTBIT_S16_LE
,
1038 .rates
= SNDRV_PCM_RATE_48000
,
1043 .buffer_bytes_max
= AZX_MAX_BUF_SIZE
,
1044 .period_bytes_min
= 128,
1045 .period_bytes_max
= AZX_MAX_BUF_SIZE
/ 2,
1047 .periods_max
= AZX_MAX_FRAG
,
1053 struct hda_codec
*codec
;
1054 struct hda_pcm_stream
*hinfo
[2];
1057 static int azx_pcm_open(struct snd_pcm_substream
*substream
)
1059 struct azx_pcm
*apcm
= snd_pcm_substream_chip(substream
);
1060 struct hda_pcm_stream
*hinfo
= apcm
->hinfo
[substream
->stream
];
1061 struct azx
*chip
= apcm
->chip
;
1062 struct azx_dev
*azx_dev
;
1063 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
1064 unsigned long flags
;
1067 mutex_lock(&chip
->open_mutex
);
1068 azx_dev
= azx_assign_device(chip
, substream
->stream
);
1069 if (azx_dev
== NULL
) {
1070 mutex_unlock(&chip
->open_mutex
);
1073 runtime
->hw
= azx_pcm_hw
;
1074 runtime
->hw
.channels_min
= hinfo
->channels_min
;
1075 runtime
->hw
.channels_max
= hinfo
->channels_max
;
1076 runtime
->hw
.formats
= hinfo
->formats
;
1077 runtime
->hw
.rates
= hinfo
->rates
;
1078 snd_pcm_limit_hw_rates(runtime
);
1079 snd_pcm_hw_constraint_integer(runtime
, SNDRV_PCM_HW_PARAM_PERIODS
);
1080 if ((err
= hinfo
->ops
.open(hinfo
, apcm
->codec
, substream
)) < 0) {
1081 azx_release_device(azx_dev
);
1082 mutex_unlock(&chip
->open_mutex
);
1085 spin_lock_irqsave(&chip
->reg_lock
, flags
);
1086 azx_dev
->substream
= substream
;
1087 azx_dev
->running
= 0;
1088 spin_unlock_irqrestore(&chip
->reg_lock
, flags
);
1090 runtime
->private_data
= azx_dev
;
1091 mutex_unlock(&chip
->open_mutex
);
1095 static int azx_pcm_close(struct snd_pcm_substream
*substream
)
1097 struct azx_pcm
*apcm
= snd_pcm_substream_chip(substream
);
1098 struct hda_pcm_stream
*hinfo
= apcm
->hinfo
[substream
->stream
];
1099 struct azx
*chip
= apcm
->chip
;
1100 struct azx_dev
*azx_dev
= get_azx_dev(substream
);
1101 unsigned long flags
;
1103 mutex_lock(&chip
->open_mutex
);
1104 spin_lock_irqsave(&chip
->reg_lock
, flags
);
1105 azx_dev
->substream
= NULL
;
1106 azx_dev
->running
= 0;
1107 spin_unlock_irqrestore(&chip
->reg_lock
, flags
);
1108 azx_release_device(azx_dev
);
1109 hinfo
->ops
.close(hinfo
, apcm
->codec
, substream
);
1110 mutex_unlock(&chip
->open_mutex
);
1114 static int azx_pcm_hw_params(struct snd_pcm_substream
*substream
, struct snd_pcm_hw_params
*hw_params
)
1116 return snd_pcm_lib_malloc_pages(substream
, params_buffer_bytes(hw_params
));
1119 static int azx_pcm_hw_free(struct snd_pcm_substream
*substream
)
1121 struct azx_pcm
*apcm
= snd_pcm_substream_chip(substream
);
1122 struct azx_dev
*azx_dev
= get_azx_dev(substream
);
1123 struct hda_pcm_stream
*hinfo
= apcm
->hinfo
[substream
->stream
];
1125 /* reset BDL address */
1126 azx_sd_writel(azx_dev
, SD_BDLPL
, 0);
1127 azx_sd_writel(azx_dev
, SD_BDLPU
, 0);
1128 azx_sd_writel(azx_dev
, SD_CTL
, 0);
1130 hinfo
->ops
.cleanup(hinfo
, apcm
->codec
, substream
);
1132 return snd_pcm_lib_free_pages(substream
);
1135 static int azx_pcm_prepare(struct snd_pcm_substream
*substream
)
1137 struct azx_pcm
*apcm
= snd_pcm_substream_chip(substream
);
1138 struct azx
*chip
= apcm
->chip
;
1139 struct azx_dev
*azx_dev
= get_azx_dev(substream
);
1140 struct hda_pcm_stream
*hinfo
= apcm
->hinfo
[substream
->stream
];
1141 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
1143 azx_dev
->bufsize
= snd_pcm_lib_buffer_bytes(substream
);
1144 azx_dev
->fragsize
= snd_pcm_lib_period_bytes(substream
);
1145 azx_dev
->frags
= azx_dev
->bufsize
/ azx_dev
->fragsize
;
1146 azx_dev
->format_val
= snd_hda_calc_stream_format(runtime
->rate
,
1150 if (! azx_dev
->format_val
) {
1151 snd_printk(KERN_ERR SFX
"invalid format_val, rate=%d, ch=%d, format=%d\n",
1152 runtime
->rate
, runtime
->channels
, runtime
->format
);
1156 snd_printdd("azx_pcm_prepare: bufsize=0x%x, fragsize=0x%x, format=0x%x\n",
1157 azx_dev
->bufsize
, azx_dev
->fragsize
, azx_dev
->format_val
);
1158 azx_setup_periods(azx_dev
);
1159 azx_setup_controller(chip
, azx_dev
);
1160 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
)
1161 azx_dev
->fifo_size
= azx_sd_readw(azx_dev
, SD_FIFOSIZE
) + 1;
1163 azx_dev
->fifo_size
= 0;
1165 return hinfo
->ops
.prepare(hinfo
, apcm
->codec
, azx_dev
->stream_tag
,
1166 azx_dev
->format_val
, substream
);
1169 static int azx_pcm_trigger(struct snd_pcm_substream
*substream
, int cmd
)
1171 struct azx_pcm
*apcm
= snd_pcm_substream_chip(substream
);
1172 struct azx_dev
*azx_dev
= get_azx_dev(substream
);
1173 struct azx
*chip
= apcm
->chip
;
1176 spin_lock(&chip
->reg_lock
);
1178 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE
:
1179 case SNDRV_PCM_TRIGGER_RESUME
:
1180 case SNDRV_PCM_TRIGGER_START
:
1181 azx_stream_start(chip
, azx_dev
);
1182 azx_dev
->running
= 1;
1184 case SNDRV_PCM_TRIGGER_PAUSE_PUSH
:
1185 case SNDRV_PCM_TRIGGER_SUSPEND
:
1186 case SNDRV_PCM_TRIGGER_STOP
:
1187 azx_stream_stop(chip
, azx_dev
);
1188 azx_dev
->running
= 0;
1193 spin_unlock(&chip
->reg_lock
);
1194 if (cmd
== SNDRV_PCM_TRIGGER_PAUSE_PUSH
||
1195 cmd
== SNDRV_PCM_TRIGGER_SUSPEND
||
1196 cmd
== SNDRV_PCM_TRIGGER_STOP
) {
1198 while (azx_sd_readb(azx_dev
, SD_CTL
) & SD_CTL_DMA_START
&& --timeout
)
1204 static snd_pcm_uframes_t
azx_pcm_pointer(struct snd_pcm_substream
*substream
)
1206 struct azx_pcm
*apcm
= snd_pcm_substream_chip(substream
);
1207 struct azx
*chip
= apcm
->chip
;
1208 struct azx_dev
*azx_dev
= get_azx_dev(substream
);
1211 if (chip
->position_fix
== POS_FIX_POSBUF
||
1212 chip
->position_fix
== POS_FIX_AUTO
) {
1213 /* use the position buffer */
1214 pos
= le32_to_cpu(*azx_dev
->posbuf
);
1215 if (chip
->position_fix
== POS_FIX_AUTO
&&
1216 azx_dev
->period_intr
== 1 && ! pos
) {
1218 "hda-intel: Invalid position buffer, "
1219 "using LPIB read method instead.\n");
1220 chip
->position_fix
= POS_FIX_NONE
;
1226 pos
= azx_sd_readl(azx_dev
, SD_LPIB
);
1227 if (chip
->position_fix
== POS_FIX_FIFO
)
1228 pos
+= azx_dev
->fifo_size
;
1230 if (pos
>= azx_dev
->bufsize
)
1232 return bytes_to_frames(substream
->runtime
, pos
);
1235 static struct snd_pcm_ops azx_pcm_ops
= {
1236 .open
= azx_pcm_open
,
1237 .close
= azx_pcm_close
,
1238 .ioctl
= snd_pcm_lib_ioctl
,
1239 .hw_params
= azx_pcm_hw_params
,
1240 .hw_free
= azx_pcm_hw_free
,
1241 .prepare
= azx_pcm_prepare
,
1242 .trigger
= azx_pcm_trigger
,
1243 .pointer
= azx_pcm_pointer
,
1246 static void azx_pcm_free(struct snd_pcm
*pcm
)
1248 kfree(pcm
->private_data
);
1251 static int __devinit
create_codec_pcm(struct azx
*chip
, struct hda_codec
*codec
,
1252 struct hda_pcm
*cpcm
, int pcm_dev
)
1255 struct snd_pcm
*pcm
;
1256 struct azx_pcm
*apcm
;
1258 /* if no substreams are defined for both playback and capture,
1259 * it's just a placeholder. ignore it.
1261 if (!cpcm
->stream
[0].substreams
&& !cpcm
->stream
[1].substreams
)
1264 snd_assert(cpcm
->name
, return -EINVAL
);
1266 err
= snd_pcm_new(chip
->card
, cpcm
->name
, pcm_dev
,
1267 cpcm
->stream
[0].substreams
, cpcm
->stream
[1].substreams
,
1271 strcpy(pcm
->name
, cpcm
->name
);
1272 apcm
= kmalloc(sizeof(*apcm
), GFP_KERNEL
);
1276 apcm
->codec
= codec
;
1277 apcm
->hinfo
[0] = &cpcm
->stream
[0];
1278 apcm
->hinfo
[1] = &cpcm
->stream
[1];
1279 pcm
->private_data
= apcm
;
1280 pcm
->private_free
= azx_pcm_free
;
1281 if (cpcm
->stream
[0].substreams
)
1282 snd_pcm_set_ops(pcm
, SNDRV_PCM_STREAM_PLAYBACK
, &azx_pcm_ops
);
1283 if (cpcm
->stream
[1].substreams
)
1284 snd_pcm_set_ops(pcm
, SNDRV_PCM_STREAM_CAPTURE
, &azx_pcm_ops
);
1285 snd_pcm_lib_preallocate_pages_for_all(pcm
, SNDRV_DMA_TYPE_DEV
,
1286 snd_dma_pci_data(chip
->pci
),
1287 1024 * 64, 1024 * 128);
1288 chip
->pcm
[pcm_dev
] = pcm
;
1289 if (chip
->pcm_devs
< pcm_dev
+ 1)
1290 chip
->pcm_devs
= pcm_dev
+ 1;
1295 static int __devinit
azx_pcm_create(struct azx
*chip
)
1297 struct list_head
*p
;
1298 struct hda_codec
*codec
;
1302 if ((err
= snd_hda_build_pcms(chip
->bus
)) < 0)
1305 /* create audio PCMs */
1307 list_for_each(p
, &chip
->bus
->codec_list
) {
1308 codec
= list_entry(p
, struct hda_codec
, list
);
1309 for (c
= 0; c
< codec
->num_pcms
; c
++) {
1310 if (codec
->pcm_info
[c
].is_modem
)
1311 continue; /* create later */
1312 if (pcm_dev
>= AZX_MAX_AUDIO_PCMS
) {
1313 snd_printk(KERN_ERR SFX
"Too many audio PCMs\n");
1316 err
= create_codec_pcm(chip
, codec
, &codec
->pcm_info
[c
], pcm_dev
);
1323 /* create modem PCMs */
1324 pcm_dev
= AZX_MAX_AUDIO_PCMS
;
1325 list_for_each(p
, &chip
->bus
->codec_list
) {
1326 codec
= list_entry(p
, struct hda_codec
, list
);
1327 for (c
= 0; c
< codec
->num_pcms
; c
++) {
1328 if (! codec
->pcm_info
[c
].is_modem
)
1329 continue; /* already created */
1330 if (pcm_dev
>= AZX_MAX_PCMS
) {
1331 snd_printk(KERN_ERR SFX
"Too many modem PCMs\n");
1334 err
= create_codec_pcm(chip
, codec
, &codec
->pcm_info
[c
], pcm_dev
);
1337 chip
->pcm
[pcm_dev
]->dev_class
= SNDRV_PCM_CLASS_MODEM
;
1345 * mixer creation - all stuff is implemented in hda module
1347 static int __devinit
azx_mixer_create(struct azx
*chip
)
1349 return snd_hda_build_controls(chip
->bus
);
1354 * initialize SD streams
1356 static int __devinit
azx_init_stream(struct azx
*chip
)
1360 /* initialize each stream (aka device)
1361 * assign the starting bdl address to each stream (device) and initialize
1363 for (i
= 0; i
< chip
->num_streams
; i
++) {
1364 unsigned int off
= sizeof(u32
) * (i
* AZX_MAX_FRAG
* 4);
1365 struct azx_dev
*azx_dev
= &chip
->azx_dev
[i
];
1366 azx_dev
->bdl
= (u32
*)(chip
->bdl
.area
+ off
);
1367 azx_dev
->bdl_addr
= chip
->bdl
.addr
+ off
;
1368 azx_dev
->posbuf
= (u32 __iomem
*)(chip
->posbuf
.area
+ i
* 8);
1369 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
1370 azx_dev
->sd_addr
= chip
->remap_addr
+ (0x20 * i
+ 0x80);
1371 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
1372 azx_dev
->sd_int_sta_mask
= 1 << i
;
1373 /* stream tag: must be non-zero and unique */
1375 azx_dev
->stream_tag
= i
+ 1;
1381 static int azx_acquire_irq(struct azx
*chip
, int do_disconnect
)
1383 if (request_irq(chip
->pci
->irq
, azx_interrupt
,
1384 chip
->msi
? 0 : IRQF_SHARED
,
1385 "HDA Intel", chip
)) {
1386 printk(KERN_ERR
"hda-intel: unable to grab IRQ %d, "
1387 "disabling device\n", chip
->pci
->irq
);
1389 snd_card_disconnect(chip
->card
);
1392 chip
->irq
= chip
->pci
->irq
;
1401 static int azx_suspend(struct pci_dev
*pci
, pm_message_t state
)
1403 struct snd_card
*card
= pci_get_drvdata(pci
);
1404 struct azx
*chip
= card
->private_data
;
1407 snd_power_change_state(card
, SNDRV_CTL_POWER_D3hot
);
1408 for (i
= 0; i
< chip
->pcm_devs
; i
++)
1409 snd_pcm_suspend_all(chip
->pcm
[i
]);
1410 snd_hda_suspend(chip
->bus
, state
);
1411 azx_free_cmd_io(chip
);
1412 if (chip
->irq
>= 0) {
1413 synchronize_irq(chip
->irq
);
1414 free_irq(chip
->irq
, chip
);
1418 pci_disable_msi(chip
->pci
);
1419 pci_disable_device(pci
);
1420 pci_save_state(pci
);
1421 pci_set_power_state(pci
, pci_choose_state(pci
, state
));
1425 static int azx_resume(struct pci_dev
*pci
)
1427 struct snd_card
*card
= pci_get_drvdata(pci
);
1428 struct azx
*chip
= card
->private_data
;
1430 pci_set_power_state(pci
, PCI_D0
);
1431 pci_restore_state(pci
);
1432 if (pci_enable_device(pci
) < 0) {
1433 printk(KERN_ERR
"hda-intel: pci_enable_device failed, "
1434 "disabling device\n");
1435 snd_card_disconnect(card
);
1438 pci_set_master(pci
);
1440 if (pci_enable_msi(pci
) < 0)
1442 if (azx_acquire_irq(chip
, 1) < 0)
1444 azx_init_chip(chip
);
1445 snd_hda_resume(chip
->bus
);
1446 snd_power_change_state(card
, SNDRV_CTL_POWER_D0
);
1449 #endif /* CONFIG_PM */
1455 static int azx_free(struct azx
*chip
)
1457 if (chip
->initialized
) {
1460 for (i
= 0; i
< chip
->num_streams
; i
++)
1461 azx_stream_stop(chip
, &chip
->azx_dev
[i
]);
1463 /* disable interrupts */
1464 azx_int_disable(chip
);
1465 azx_int_clear(chip
);
1467 /* disable CORB/RIRB */
1468 azx_free_cmd_io(chip
);
1470 /* disable position buffer */
1471 azx_writel(chip
, DPLBASE
, 0);
1472 azx_writel(chip
, DPUBASE
, 0);
1475 if (chip
->irq
>= 0) {
1476 synchronize_irq(chip
->irq
);
1477 free_irq(chip
->irq
, (void*)chip
);
1480 pci_disable_msi(chip
->pci
);
1481 if (chip
->remap_addr
)
1482 iounmap(chip
->remap_addr
);
1485 snd_dma_free_pages(&chip
->bdl
);
1487 snd_dma_free_pages(&chip
->rb
);
1488 if (chip
->posbuf
.area
)
1489 snd_dma_free_pages(&chip
->posbuf
);
1490 pci_release_regions(chip
->pci
);
1491 pci_disable_device(chip
->pci
);
1492 kfree(chip
->azx_dev
);
1498 static int azx_dev_free(struct snd_device
*device
)
1500 return azx_free(device
->device_data
);
1506 static int __devinit
azx_create(struct snd_card
*card
, struct pci_dev
*pci
,
1512 static struct snd_device_ops ops
= {
1513 .dev_free
= azx_dev_free
,
1518 err
= pci_enable_device(pci
);
1522 chip
= kzalloc(sizeof(*chip
), GFP_KERNEL
);
1524 snd_printk(KERN_ERR SFX
"cannot allocate chip\n");
1525 pci_disable_device(pci
);
1529 spin_lock_init(&chip
->reg_lock
);
1530 mutex_init(&chip
->open_mutex
);
1534 chip
->driver_type
= driver_type
;
1535 chip
->msi
= enable_msi
;
1537 chip
->position_fix
= position_fix
;
1538 chip
->single_cmd
= single_cmd
;
1540 #if BITS_PER_LONG != 64
1541 /* Fix up base address on ULI M5461 */
1542 if (chip
->driver_type
== AZX_DRIVER_ULI
) {
1544 pci_read_config_word(pci
, 0x40, &tmp3
);
1545 pci_write_config_word(pci
, 0x40, tmp3
| 0x10);
1546 pci_write_config_dword(pci
, PCI_BASE_ADDRESS_1
, 0);
1550 err
= pci_request_regions(pci
, "ICH HD audio");
1553 pci_disable_device(pci
);
1557 chip
->addr
= pci_resource_start(pci
, 0);
1558 chip
->remap_addr
= ioremap_nocache(chip
->addr
, pci_resource_len(pci
,0));
1559 if (chip
->remap_addr
== NULL
) {
1560 snd_printk(KERN_ERR SFX
"ioremap error\n");
1566 if (pci_enable_msi(pci
) < 0)
1569 if (azx_acquire_irq(chip
, 0) < 0) {
1574 pci_set_master(pci
);
1575 synchronize_irq(chip
->irq
);
1577 switch (chip
->driver_type
) {
1578 case AZX_DRIVER_ULI
:
1579 chip
->playback_streams
= ULI_NUM_PLAYBACK
;
1580 chip
->capture_streams
= ULI_NUM_CAPTURE
;
1581 chip
->playback_index_offset
= ULI_PLAYBACK_INDEX
;
1582 chip
->capture_index_offset
= ULI_CAPTURE_INDEX
;
1584 case AZX_DRIVER_ATIHDMI
:
1585 chip
->playback_streams
= ATIHDMI_NUM_PLAYBACK
;
1586 chip
->capture_streams
= ATIHDMI_NUM_CAPTURE
;
1587 chip
->playback_index_offset
= ATIHDMI_PLAYBACK_INDEX
;
1588 chip
->capture_index_offset
= ATIHDMI_CAPTURE_INDEX
;
1591 chip
->playback_streams
= ICH6_NUM_PLAYBACK
;
1592 chip
->capture_streams
= ICH6_NUM_CAPTURE
;
1593 chip
->playback_index_offset
= ICH6_PLAYBACK_INDEX
;
1594 chip
->capture_index_offset
= ICH6_CAPTURE_INDEX
;
1597 chip
->num_streams
= chip
->playback_streams
+ chip
->capture_streams
;
1598 chip
->azx_dev
= kcalloc(chip
->num_streams
, sizeof(*chip
->azx_dev
), GFP_KERNEL
);
1599 if (!chip
->azx_dev
) {
1600 snd_printk(KERN_ERR
"cannot malloc azx_dev\n");
1604 /* allocate memory for the BDL for each stream */
1605 if ((err
= snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV
, snd_dma_pci_data(chip
->pci
),
1606 BDL_SIZE
, &chip
->bdl
)) < 0) {
1607 snd_printk(KERN_ERR SFX
"cannot allocate BDL\n");
1610 /* allocate memory for the position buffer */
1611 if ((err
= snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV
, snd_dma_pci_data(chip
->pci
),
1612 chip
->num_streams
* 8, &chip
->posbuf
)) < 0) {
1613 snd_printk(KERN_ERR SFX
"cannot allocate posbuf\n");
1616 /* allocate CORB/RIRB */
1617 if (! chip
->single_cmd
)
1618 if ((err
= azx_alloc_cmd_io(chip
)) < 0)
1621 /* initialize streams */
1622 azx_init_stream(chip
);
1624 /* initialize chip */
1625 azx_init_chip(chip
);
1627 chip
->initialized
= 1;
1629 /* codec detection */
1630 if (!chip
->codec_mask
) {
1631 snd_printk(KERN_ERR SFX
"no codecs found!\n");
1636 if ((err
= snd_device_new(card
, SNDRV_DEV_LOWLEVEL
, chip
, &ops
)) <0) {
1637 snd_printk(KERN_ERR SFX
"Error creating device [card]!\n");
1641 strcpy(card
->driver
, "HDA-Intel");
1642 strcpy(card
->shortname
, driver_short_names
[chip
->driver_type
]);
1643 sprintf(card
->longname
, "%s at 0x%lx irq %i", card
->shortname
, chip
->addr
, chip
->irq
);
1653 static int __devinit
azx_probe(struct pci_dev
*pci
, const struct pci_device_id
*pci_id
)
1655 struct snd_card
*card
;
1659 card
= snd_card_new(index
, id
, THIS_MODULE
, 0);
1661 snd_printk(KERN_ERR SFX
"Error creating card!\n");
1665 err
= azx_create(card
, pci
, pci_id
->driver_data
, &chip
);
1667 snd_card_free(card
);
1670 card
->private_data
= chip
;
1672 /* create codec instances */
1673 if ((err
= azx_codec_create(chip
, model
)) < 0) {
1674 snd_card_free(card
);
1678 /* create PCM streams */
1679 if ((err
= azx_pcm_create(chip
)) < 0) {
1680 snd_card_free(card
);
1684 /* create mixer controls */
1685 if ((err
= azx_mixer_create(chip
)) < 0) {
1686 snd_card_free(card
);
1690 snd_card_set_dev(card
, &pci
->dev
);
1692 if ((err
= snd_card_register(card
)) < 0) {
1693 snd_card_free(card
);
1697 pci_set_drvdata(pci
, card
);
1702 static void __devexit
azx_remove(struct pci_dev
*pci
)
1704 snd_card_free(pci_get_drvdata(pci
));
1705 pci_set_drvdata(pci
, NULL
);
1709 static struct pci_device_id azx_ids
[] = {
1710 { 0x8086, 0x2668, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, AZX_DRIVER_ICH
}, /* ICH6 */
1711 { 0x8086, 0x27d8, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, AZX_DRIVER_ICH
}, /* ICH7 */
1712 { 0x8086, 0x269a, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, AZX_DRIVER_ICH
}, /* ESB2 */
1713 { 0x8086, 0x284b, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, AZX_DRIVER_ICH
}, /* ICH8 */
1714 { 0x1002, 0x437b, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, AZX_DRIVER_ATI
}, /* ATI SB450 */
1715 { 0x1002, 0x4383, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, AZX_DRIVER_ATI
}, /* ATI SB600 */
1716 { 0x1002, 0x793b, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, AZX_DRIVER_ATIHDMI
}, /* ATI RS600 HDMI */
1717 { 0x1002, 0x7919, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, AZX_DRIVER_ATIHDMI
}, /* ATI RS690 HDMI */
1718 { 0x1106, 0x3288, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, AZX_DRIVER_VIA
}, /* VIA VT8251/VT8237A */
1719 { 0x1039, 0x7502, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, AZX_DRIVER_SIS
}, /* SIS966 */
1720 { 0x10b9, 0x5461, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, AZX_DRIVER_ULI
}, /* ULI M5461 */
1721 { 0x10de, 0x026c, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, AZX_DRIVER_NVIDIA
}, /* NVIDIA MCP51 */
1722 { 0x10de, 0x0371, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, AZX_DRIVER_NVIDIA
}, /* NVIDIA MCP55 */
1723 { 0x10de, 0x03e4, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, AZX_DRIVER_NVIDIA
}, /* NVIDIA MCP61 */
1724 { 0x10de, 0x03f0, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, AZX_DRIVER_NVIDIA
}, /* NVIDIA MCP61 */
1725 { 0x10de, 0x044a, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, AZX_DRIVER_NVIDIA
}, /* NVIDIA MCP65 */
1726 { 0x10de, 0x044b, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, AZX_DRIVER_NVIDIA
}, /* NVIDIA MCP65 */
1727 { 0x10de, 0x055c, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, AZX_DRIVER_NVIDIA
}, /* NVIDIA MCP67 */
1728 { 0x10de, 0x055d, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, AZX_DRIVER_NVIDIA
}, /* NVIDIA MCP67 */
1731 MODULE_DEVICE_TABLE(pci
, azx_ids
);
1733 /* pci_driver definition */
1734 static struct pci_driver driver
= {
1735 .name
= "HDA Intel",
1736 .id_table
= azx_ids
,
1738 .remove
= __devexit_p(azx_remove
),
1740 .suspend
= azx_suspend
,
1741 .resume
= azx_resume
,
1745 static int __init
alsa_card_azx_init(void)
1747 return pci_register_driver(&driver
);
1750 static void __exit
alsa_card_azx_exit(void)
1752 pci_unregister_driver(&driver
);
1755 module_init(alsa_card_azx_init
)
1756 module_exit(alsa_card_azx_exit
)