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[PATCH] genirq: x86_64 irq: Move msi message composition into io_apic.c
[usb.git] / arch / x86_64 / kernel / io_apic.c
blob437b6f96cc80faf3e9eb8067563db6933da35280
1 /*
2 * Intel IO-APIC support for multi-Pentium hosts.
3 *
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
5 *
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
8 *
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
14 *
15 * Fixes
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
18 * and Rolf G. Tews
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
21 */
22
23 #include <linux/mm.h>
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/smp_lock.h>
29 #include <linux/pci.h>
30 #include <linux/mc146818rtc.h>
31 #include <linux/acpi.h>
32 #include <linux/sysdev.h>
33 #ifdef CONFIG_ACPI
34 #include <acpi/acpi_bus.h>
35 #endif
36
37 #include <asm/io.h>
38 #include <asm/smp.h>
39 #include <asm/desc.h>
40 #include <asm/proto.h>
41 #include <asm/mach_apic.h>
42 #include <asm/acpi.h>
43 #include <asm/dma.h>
44 #include <asm/nmi.h>
45 #include <asm/msidef.h>
46
47 #define __apicdebuginit __init
48
49 int sis_apic_bug; /* not actually supported, dummy for compile */
50
51 static int no_timer_check;
52
53 static int disable_timer_pin_1 __initdata;
54
55 int timer_over_8254 __initdata = 0;
56
57 /* Where if anywhere is the i8259 connect in external int mode */
58 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
59
60 static DEFINE_SPINLOCK(ioapic_lock);
61 static DEFINE_SPINLOCK(vector_lock);
62
63 /*
64 * # of IRQ routing registers
65 */
66 int nr_ioapic_registers[MAX_IO_APICS];
67
68 /*
69 * Rough estimation of how many shared IRQs there are, can
70 * be changed anytime.
71 */
72 #define MAX_PLUS_SHARED_IRQS NR_IRQ_VECTORS
73 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
74
75 /*
76 * This is performance-critical, we want to do it O(1)
77 *
78 * the indexing order of this array favors 1:1 mappings
79 * between pins and IRQs.
80 */
81
82 static struct irq_pin_list {
83 short apic, pin, next;
84 } irq_2_pin[PIN_MAP_SIZE];
85
86 int vector_irq[NR_VECTORS] __read_mostly = { [0 ... NR_VECTORS - 1] = -1};
87 #ifdef CONFIG_PCI_MSI
88 #define vector_to_irq(vector) \
89 (platform_legacy_irq(vector) ? vector : vector_irq[vector])
90 #else
91 #define vector_to_irq(vector) (vector)
92 #endif
93
94 #define __DO_ACTION(R, ACTION, FINAL) \
95 \
96 { \
97 int pin; \
98 struct irq_pin_list *entry = irq_2_pin + irq; \
99 \
100 BUG_ON(irq >= NR_IRQS); \
101 for (;;) { \
102 unsigned int reg; \
103 pin = entry->pin; \
104 if (pin == -1) \
105 break; \
106 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
107 reg ACTION; \
108 io_apic_modify(entry->apic, reg); \
109 if (!entry->next) \
110 break; \
111 entry = irq_2_pin + entry->next; \
112 } \
113 FINAL; \
114 }
115
116 union entry_union {
117 struct { u32 w1, w2; };
118 struct IO_APIC_route_entry entry;
119 };
120
121 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
122 {
123 union entry_union eu;
124 unsigned long flags;
125 spin_lock_irqsave(&ioapic_lock, flags);
126 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
127 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
128 spin_unlock_irqrestore(&ioapic_lock, flags);
129 return eu.entry;
130 }
131
132 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
133 {
134 unsigned long flags;
135 union entry_union eu;
136 eu.entry = e;
137 spin_lock_irqsave(&ioapic_lock, flags);
138 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
139 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
140 spin_unlock_irqrestore(&ioapic_lock, flags);
141 }
142
143 #ifdef CONFIG_SMP
144 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
145 {
146 unsigned long flags;
147 unsigned int dest;
148 cpumask_t tmp;
149
150 cpus_and(tmp, mask, cpu_online_map);
151 if (cpus_empty(tmp))
152 tmp = TARGET_CPUS;
153
154 cpus_and(mask, tmp, CPU_MASK_ALL);
155
156 dest = cpu_mask_to_apicid(mask);
157
158 /*
159 * Only the high 8 bits are valid.
160 */
161 dest = SET_APIC_LOGICAL_ID(dest);
162
163 spin_lock_irqsave(&ioapic_lock, flags);
164 __DO_ACTION(1, = dest, )
165 set_irq_info(irq, mask);
166 spin_unlock_irqrestore(&ioapic_lock, flags);
167 }
168 #endif
169
170 static u8 gsi_2_irq[NR_IRQ_VECTORS] = { [0 ... NR_IRQ_VECTORS-1] = 0xFF };
171
172 /*
173 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
174 * shared ISA-space IRQs, so we have to support them. We are super
175 * fast in the common case, and fast for shared ISA-space IRQs.
176 */
177 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
178 {
179 static int first_free_entry = NR_IRQS;
180 struct irq_pin_list *entry = irq_2_pin + irq;
181
182 BUG_ON(irq >= NR_IRQS);
183 while (entry->next)
184 entry = irq_2_pin + entry->next;
185
186 if (entry->pin != -1) {
187 entry->next = first_free_entry;
188 entry = irq_2_pin + entry->next;
189 if (++first_free_entry >= PIN_MAP_SIZE)
190 panic("io_apic.c: ran out of irq_2_pin entries!");
191 }
192 entry->apic = apic;
193 entry->pin = pin;
194 }
195
196
197 #define DO_ACTION(name,R,ACTION, FINAL) \
198 \
199 static void name##_IO_APIC_irq (unsigned int irq) \
200 __DO_ACTION(R, ACTION, FINAL)
201
202 DO_ACTION( __mask, 0, |= 0x00010000, io_apic_sync(entry->apic) )
203 /* mask = 1 */
204 DO_ACTION( __unmask, 0, &= 0xfffeffff, )
205 /* mask = 0 */
206
207 static void mask_IO_APIC_irq (unsigned int irq)
208 {
209 unsigned long flags;
210
211 spin_lock_irqsave(&ioapic_lock, flags);
212 __mask_IO_APIC_irq(irq);
213 spin_unlock_irqrestore(&ioapic_lock, flags);
214 }
215
216 static void unmask_IO_APIC_irq (unsigned int irq)
217 {
218 unsigned long flags;
219
220 spin_lock_irqsave(&ioapic_lock, flags);
221 __unmask_IO_APIC_irq(irq);
222 spin_unlock_irqrestore(&ioapic_lock, flags);
223 }
224
225 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
226 {
227 struct IO_APIC_route_entry entry;
228
229 /* Check delivery_mode to be sure we're not clearing an SMI pin */
230 entry = ioapic_read_entry(apic, pin);
231 if (entry.delivery_mode == dest_SMI)
232 return;
233 /*
234 * Disable it in the IO-APIC irq-routing table:
235 */
236 memset(&entry, 0, sizeof(entry));
237 entry.mask = 1;
238 ioapic_write_entry(apic, pin, entry);
239 }
240
241 static void clear_IO_APIC (void)
242 {
243 int apic, pin;
244
245 for (apic = 0; apic < nr_ioapics; apic++)
246 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
247 clear_IO_APIC_pin(apic, pin);
248 }
249
250 int skip_ioapic_setup;
251 int ioapic_force;
252
253 /* dummy parsing: see setup.c */
254
255 static int __init disable_ioapic_setup(char *str)
256 {
257 skip_ioapic_setup = 1;
258 return 0;
259 }
260 early_param("noapic", disable_ioapic_setup);
261
262 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
263 static int __init disable_timer_pin_setup(char *arg)
264 {
265 disable_timer_pin_1 = 1;
266 return 1;
267 }
268 __setup("disable_timer_pin_1", disable_timer_pin_setup);
269
270 static int __init setup_disable_8254_timer(char *s)
271 {
272 timer_over_8254 = -1;
273 return 1;
274 }
275 static int __init setup_enable_8254_timer(char *s)
276 {
277 timer_over_8254 = 2;
278 return 1;
279 }
280
281 __setup("disable_8254_timer", setup_disable_8254_timer);
282 __setup("enable_8254_timer", setup_enable_8254_timer);
283
284
285 /*
286 * Find the IRQ entry number of a certain pin.
287 */
288 static int find_irq_entry(int apic, int pin, int type)
289 {
290 int i;
291
292 for (i = 0; i < mp_irq_entries; i++)
293 if (mp_irqs[i].mpc_irqtype == type &&
294 (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
295 mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
296 mp_irqs[i].mpc_dstirq == pin)
297 return i;
298
299 return -1;
300 }
301
302 /*
303 * Find the pin to which IRQ[irq] (ISA) is connected
304 */
305 static int __init find_isa_irq_pin(int irq, int type)
306 {
307 int i;
308
309 for (i = 0; i < mp_irq_entries; i++) {
310 int lbus = mp_irqs[i].mpc_srcbus;
311
312 if (test_bit(lbus, mp_bus_not_pci) &&
313 (mp_irqs[i].mpc_irqtype == type) &&
314 (mp_irqs[i].mpc_srcbusirq == irq))
315
316 return mp_irqs[i].mpc_dstirq;
317 }
318 return -1;
319 }
320
321 static int __init find_isa_irq_apic(int irq, int type)
322 {
323 int i;
324
325 for (i = 0; i < mp_irq_entries; i++) {
326 int lbus = mp_irqs[i].mpc_srcbus;
327
328 if (test_bit(lbus, mp_bus_not_pci) &&
329 (mp_irqs[i].mpc_irqtype == type) &&
330 (mp_irqs[i].mpc_srcbusirq == irq))
331 break;
332 }
333 if (i < mp_irq_entries) {
334 int apic;
335 for(apic = 0; apic < nr_ioapics; apic++) {
336 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
337 return apic;
338 }
339 }
340
341 return -1;
342 }
343
344 /*
345 * Find a specific PCI IRQ entry.
346 * Not an __init, possibly needed by modules
347 */
348 static int pin_2_irq(int idx, int apic, int pin);
349
350 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
351 {
352 int apic, i, best_guess = -1;
353
354 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
355 bus, slot, pin);
356 if (mp_bus_id_to_pci_bus[bus] == -1) {
357 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
358 return -1;
359 }
360 for (i = 0; i < mp_irq_entries; i++) {
361 int lbus = mp_irqs[i].mpc_srcbus;
362
363 for (apic = 0; apic < nr_ioapics; apic++)
364 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
365 mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
366 break;
367
368 if (!test_bit(lbus, mp_bus_not_pci) &&
369 !mp_irqs[i].mpc_irqtype &&
370 (bus == lbus) &&
371 (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
372 int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
373
374 if (!(apic || IO_APIC_IRQ(irq)))
375 continue;
376
377 if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
378 return irq;
379 /*
380 * Use the first all-but-pin matching entry as a
381 * best-guess fuzzy result for broken mptables.
382 */
383 if (best_guess < 0)
384 best_guess = irq;
385 }
386 }
387 BUG_ON(best_guess >= NR_IRQS);
388 return best_guess;
389 }
390
391 /* ISA interrupts are always polarity zero edge triggered,
392 * when listed as conforming in the MP table. */
393
394 #define default_ISA_trigger(idx) (0)
395 #define default_ISA_polarity(idx) (0)
396
397 /* PCI interrupts are always polarity one level triggered,
398 * when listed as conforming in the MP table. */
399
400 #define default_PCI_trigger(idx) (1)
401 #define default_PCI_polarity(idx) (1)
402
403 static int __init MPBIOS_polarity(int idx)
404 {
405 int bus = mp_irqs[idx].mpc_srcbus;
406 int polarity;
407
408 /*
409 * Determine IRQ line polarity (high active or low active):
410 */
411 switch (mp_irqs[idx].mpc_irqflag & 3)
412 {
413 case 0: /* conforms, ie. bus-type dependent polarity */
414 if (test_bit(bus, mp_bus_not_pci))
415 polarity = default_ISA_polarity(idx);
416 else
417 polarity = default_PCI_polarity(idx);
418 break;
419 case 1: /* high active */
420 {
421 polarity = 0;
422 break;
423 }
424 case 2: /* reserved */
425 {
426 printk(KERN_WARNING "broken BIOS!!\n");
427 polarity = 1;
428 break;
429 }
430 case 3: /* low active */
431 {
432 polarity = 1;
433 break;
434 }
435 default: /* invalid */
436 {
437 printk(KERN_WARNING "broken BIOS!!\n");
438 polarity = 1;
439 break;
440 }
441 }
442 return polarity;
443 }
444
445 static int MPBIOS_trigger(int idx)
446 {
447 int bus = mp_irqs[idx].mpc_srcbus;
448 int trigger;
449
450 /*
451 * Determine IRQ trigger mode (edge or level sensitive):
452 */
453 switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
454 {
455 case 0: /* conforms, ie. bus-type dependent */
456 if (test_bit(bus, mp_bus_not_pci))
457 trigger = default_ISA_trigger(idx);
458 else
459 trigger = default_PCI_trigger(idx);
460 break;
461 case 1: /* edge */
462 {
463 trigger = 0;
464 break;
465 }
466 case 2: /* reserved */
467 {
468 printk(KERN_WARNING "broken BIOS!!\n");
469 trigger = 1;
470 break;
471 }
472 case 3: /* level */
473 {
474 trigger = 1;
475 break;
476 }
477 default: /* invalid */
478 {
479 printk(KERN_WARNING "broken BIOS!!\n");
480 trigger = 0;
481 break;
482 }
483 }
484 return trigger;
485 }
486
487 static inline int irq_polarity(int idx)
488 {
489 return MPBIOS_polarity(idx);
490 }
491
492 static inline int irq_trigger(int idx)
493 {
494 return MPBIOS_trigger(idx);
495 }
496
497 static int next_irq = 16;
498
499 /*
500 * gsi_irq_sharing -- Name overload! "irq" can be either a legacy IRQ
501 * in the range 0-15, a linux IRQ in the range 0-223, or a GSI number
502 * from ACPI, which can reach 800 in large boxen.
503 *
504 * Compact the sparse GSI space into a sequential IRQ series and reuse
505 * vectors if possible.
506 */
507 int gsi_irq_sharing(int gsi)
508 {
509 int i, tries, vector;
510
511 BUG_ON(gsi >= NR_IRQ_VECTORS);
512
513 if (platform_legacy_irq(gsi))
514 return gsi;
515
516 if (gsi_2_irq[gsi] != 0xFF)
517 return (int)gsi_2_irq[gsi];
518
519 tries = NR_IRQS;
520 try_again:
521 vector = assign_irq_vector(gsi);
522
523 /*
524 * Sharing vectors means sharing IRQs, so scan irq_vectors for previous
525 * use of vector and if found, return that IRQ. However, we never want
526 * to share legacy IRQs, which usually have a different trigger mode
527 * than PCI.
528 */
529 for (i = 0; i < NR_IRQS; i++)
530 if (IO_APIC_VECTOR(i) == vector)
531 break;
532 if (platform_legacy_irq(i)) {
533 if (--tries >= 0) {
534 IO_APIC_VECTOR(i) = 0;
535 goto try_again;
536 }
537 panic("gsi_irq_sharing: didn't find an IRQ using vector 0x%02X for GSI %d", vector, gsi);
538 }
539 if (i < NR_IRQS) {
540 gsi_2_irq[gsi] = i;
541 printk(KERN_INFO "GSI %d sharing vector 0x%02X and IRQ %d\n",
542 gsi, vector, i);
543 return i;
544 }
545
546 i = next_irq++;
547 BUG_ON(i >= NR_IRQS);
548 gsi_2_irq[gsi] = i;
549 IO_APIC_VECTOR(i) = vector;
550 printk(KERN_INFO "GSI %d assigned vector 0x%02X and IRQ %d\n",
551 gsi, vector, i);
552 return i;
553 }
554
555 static int pin_2_irq(int idx, int apic, int pin)
556 {
557 int irq, i;
558 int bus = mp_irqs[idx].mpc_srcbus;
559
560 /*
561 * Debugging check, we are in big trouble if this message pops up!
562 */
563 if (mp_irqs[idx].mpc_dstirq != pin)
564 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
565
566 if (test_bit(bus, mp_bus_not_pci)) {
567 irq = mp_irqs[idx].mpc_srcbusirq;
568 } else {
569 /*
570 * PCI IRQs are mapped in order
571 */
572 i = irq = 0;
573 while (i < apic)
574 irq += nr_ioapic_registers[i++];
575 irq += pin;
576 irq = gsi_irq_sharing(irq);
577 }
578 BUG_ON(irq >= NR_IRQS);
579 return irq;
580 }
581
582 static inline int IO_APIC_irq_trigger(int irq)
583 {
584 int apic, idx, pin;
585
586 for (apic = 0; apic < nr_ioapics; apic++) {
587 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
588 idx = find_irq_entry(apic,pin,mp_INT);
589 if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
590 return irq_trigger(idx);
591 }
592 }
593 /*
594 * nonexistent IRQs are edge default
595 */
596 return 0;
597 }
598
599 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
600 u8 irq_vector[NR_IRQ_VECTORS] __read_mostly = { FIRST_DEVICE_VECTOR , 0 };
601
602 int assign_irq_vector(int irq)
603 {
604 static int current_vector = FIRST_DEVICE_VECTOR, offset = 0;
605 unsigned long flags;
606 int vector;
607
608 BUG_ON(irq != AUTO_ASSIGN && (unsigned)irq >= NR_IRQ_VECTORS);
609
610 spin_lock_irqsave(&vector_lock, flags);
611
612 if (irq != AUTO_ASSIGN && IO_APIC_VECTOR(irq) > 0) {
613 spin_unlock_irqrestore(&vector_lock, flags);
614 return IO_APIC_VECTOR(irq);
615 }
616 next:
617 current_vector += 8;
618 if (current_vector == IA32_SYSCALL_VECTOR)
619 goto next;
620
621 if (current_vector >= FIRST_SYSTEM_VECTOR) {
622 /* If we run out of vectors on large boxen, must share them. */
623 offset = (offset + 1) % 8;
624 current_vector = FIRST_DEVICE_VECTOR + offset;
625 }
626
627 vector = current_vector;
628 vector_irq[vector] = irq;
629 if (irq != AUTO_ASSIGN)
630 IO_APIC_VECTOR(irq) = vector;
631
632 spin_unlock_irqrestore(&vector_lock, flags);
633
634 return vector;
635 }
636
637 extern void (*interrupt[NR_IRQS])(void);
638
639 static struct irq_chip ioapic_chip;
640
641 #define IOAPIC_AUTO -1
642 #define IOAPIC_EDGE 0
643 #define IOAPIC_LEVEL 1
644
645 static void ioapic_register_intr(int irq, int vector, unsigned long trigger)
646 {
647 unsigned idx;
648
649 idx = use_pci_vector() && !platform_legacy_irq(irq) ? vector : irq;
650
651 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
652 trigger == IOAPIC_LEVEL)
653 set_irq_chip_and_handler(idx, &ioapic_chip,
654 handle_fasteoi_irq);
655 else
656 set_irq_chip_and_handler(idx, &ioapic_chip,
657 handle_edge_irq);
658 set_intr_gate(vector, interrupt[idx]);
659 }
660
661 static void __init setup_IO_APIC_irqs(void)
662 {
663 struct IO_APIC_route_entry entry;
664 int apic, pin, idx, irq, first_notcon = 1, vector;
665 unsigned long flags;
666
667 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
668
669 for (apic = 0; apic < nr_ioapics; apic++) {
670 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
671
672 /*
673 * add it to the IO-APIC irq-routing table:
674 */
675 memset(&entry,0,sizeof(entry));
676
677 entry.delivery_mode = INT_DELIVERY_MODE;
678 entry.dest_mode = INT_DEST_MODE;
679 entry.mask = 0; /* enable IRQ */
680 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
681
682 idx = find_irq_entry(apic,pin,mp_INT);
683 if (idx == -1) {
684 if (first_notcon) {
685 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin);
686 first_notcon = 0;
687 } else
688 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mpc_apicid, pin);
689 continue;
690 }
691
692 entry.trigger = irq_trigger(idx);
693 entry.polarity = irq_polarity(idx);
694
695 if (irq_trigger(idx)) {
696 entry.trigger = 1;
697 entry.mask = 1;
698 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
699 }
700
701 irq = pin_2_irq(idx, apic, pin);
702 add_pin_to_irq(irq, apic, pin);
703
704 if (!apic && !IO_APIC_IRQ(irq))
705 continue;
706
707 if (IO_APIC_IRQ(irq)) {
708 vector = assign_irq_vector(irq);
709 entry.vector = vector;
710
711 ioapic_register_intr(irq, vector, IOAPIC_AUTO);
712 if (!apic && (irq < 16))
713 disable_8259A_irq(irq);
714 }
715 ioapic_write_entry(apic, pin, entry);
716
717 spin_lock_irqsave(&ioapic_lock, flags);
718 set_native_irq_info(irq, TARGET_CPUS);
719 spin_unlock_irqrestore(&ioapic_lock, flags);
720 }
721 }
722
723 if (!first_notcon)
724 apic_printk(APIC_VERBOSE," not connected.\n");
725 }
726
727 /*
728 * Set up the 8259A-master output pin as broadcast to all
729 * CPUs.
730 */
731 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
732 {
733 struct IO_APIC_route_entry entry;
734 unsigned long flags;
735
736 memset(&entry,0,sizeof(entry));
737
738 disable_8259A_irq(0);
739
740 /* mask LVT0 */
741 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
742
743 /*
744 * We use logical delivery to get the timer IRQ
745 * to the first CPU.
746 */
747 entry.dest_mode = INT_DEST_MODE;
748 entry.mask = 0; /* unmask IRQ now */
749 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
750 entry.delivery_mode = INT_DELIVERY_MODE;
751 entry.polarity = 0;
752 entry.trigger = 0;
753 entry.vector = vector;
754
755 /*
756 * The timer IRQ doesn't have to know that behind the
757 * scene we have a 8259A-master in AEOI mode ...
758 */
759 set_irq_chip_and_handler(0, &ioapic_chip, handle_edge_irq);
760
761 /*
762 * Add it to the IO-APIC irq-routing table:
763 */
764 spin_lock_irqsave(&ioapic_lock, flags);
765 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
766 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
767 spin_unlock_irqrestore(&ioapic_lock, flags);
768
769 enable_8259A_irq(0);
770 }
771
772 void __init UNEXPECTED_IO_APIC(void)
773 {
774 }
775
776 void __apicdebuginit print_IO_APIC(void)
777 {
778 int apic, i;
779 union IO_APIC_reg_00 reg_00;
780 union IO_APIC_reg_01 reg_01;
781 union IO_APIC_reg_02 reg_02;
782 unsigned long flags;
783
784 if (apic_verbosity == APIC_QUIET)
785 return;
786
787 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
788 for (i = 0; i < nr_ioapics; i++)
789 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
790 mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
791
792 /*
793 * We are a bit conservative about what we expect. We have to
794 * know about every hardware change ASAP.
795 */
796 printk(KERN_INFO "testing the IO APIC.......................\n");
797
798 for (apic = 0; apic < nr_ioapics; apic++) {
799
800 spin_lock_irqsave(&ioapic_lock, flags);
801 reg_00.raw = io_apic_read(apic, 0);
802 reg_01.raw = io_apic_read(apic, 1);
803 if (reg_01.bits.version >= 0x10)
804 reg_02.raw = io_apic_read(apic, 2);
805 spin_unlock_irqrestore(&ioapic_lock, flags);
806
807 printk("\n");
808 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
809 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
810 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
811 if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
812 UNEXPECTED_IO_APIC();
813
814 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
815 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
816 if ( (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
817 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
818 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
819 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
820 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
821 (reg_01.bits.entries != 0x2E) &&
822 (reg_01.bits.entries != 0x3F) &&
823 (reg_01.bits.entries != 0x03)
824 )
825 UNEXPECTED_IO_APIC();
826
827 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
828 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
829 if ( (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
830 (reg_01.bits.version != 0x02) && /* 82801BA IO-APICs (ICH2) */
831 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
832 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
833 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
834 (reg_01.bits.version != 0x20) /* Intel P64H (82806 AA) */
835 )
836 UNEXPECTED_IO_APIC();
837 if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
838 UNEXPECTED_IO_APIC();
839
840 if (reg_01.bits.version >= 0x10) {
841 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
842 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
843 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
844 UNEXPECTED_IO_APIC();
845 }
846
847 printk(KERN_DEBUG ".... IRQ redirection table:\n");
848
849 printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
850 " Stat Dest Deli Vect: \n");
851
852 for (i = 0; i <= reg_01.bits.entries; i++) {
853 struct IO_APIC_route_entry entry;
854
855 entry = ioapic_read_entry(apic, i);
856
857 printk(KERN_DEBUG " %02x %03X %02X ",
858 i,
859 entry.dest.logical.logical_dest,
860 entry.dest.physical.physical_dest
861 );
862
863 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
864 entry.mask,
865 entry.trigger,
866 entry.irr,
867 entry.polarity,
868 entry.delivery_status,
869 entry.dest_mode,
870 entry.delivery_mode,
871 entry.vector
872 );
873 }
874 }
875 if (use_pci_vector())
876 printk(KERN_INFO "Using vector-based indexing\n");
877 printk(KERN_DEBUG "IRQ to pin mappings:\n");
878 for (i = 0; i < NR_IRQS; i++) {
879 struct irq_pin_list *entry = irq_2_pin + i;
880 if (entry->pin < 0)
881 continue;
882 if (use_pci_vector() && !platform_legacy_irq(i))
883 printk(KERN_DEBUG "IRQ%d ", IO_APIC_VECTOR(i));
884 else
885 printk(KERN_DEBUG "IRQ%d ", i);
886 for (;;) {
887 printk("-> %d:%d", entry->apic, entry->pin);
888 if (!entry->next)
889 break;
890 entry = irq_2_pin + entry->next;
891 }
892 printk("\n");
893 }
894
895 printk(KERN_INFO ".................................... done.\n");
896
897 return;
898 }
899
900 #if 0
901
902 static __apicdebuginit void print_APIC_bitfield (int base)
903 {
904 unsigned int v;
905 int i, j;
906
907 if (apic_verbosity == APIC_QUIET)
908 return;
909
910 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
911 for (i = 0; i < 8; i++) {
912 v = apic_read(base + i*0x10);
913 for (j = 0; j < 32; j++) {
914 if (v & (1<<j))
915 printk("1");
916 else
917 printk("0");
918 }
919 printk("\n");
920 }
921 }
922
923 void __apicdebuginit print_local_APIC(void * dummy)
924 {
925 unsigned int v, ver, maxlvt;
926
927 if (apic_verbosity == APIC_QUIET)
928 return;
929
930 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
931 smp_processor_id(), hard_smp_processor_id());
932 v = apic_read(APIC_ID);
933 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(v));
934 v = apic_read(APIC_LVR);
935 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
936 ver = GET_APIC_VERSION(v);
937 maxlvt = get_maxlvt();
938
939 v = apic_read(APIC_TASKPRI);
940 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
941
942 v = apic_read(APIC_ARBPRI);
943 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
944 v & APIC_ARBPRI_MASK);
945 v = apic_read(APIC_PROCPRI);
946 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
947
948 v = apic_read(APIC_EOI);
949 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
950 v = apic_read(APIC_RRR);
951 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
952 v = apic_read(APIC_LDR);
953 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
954 v = apic_read(APIC_DFR);
955 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
956 v = apic_read(APIC_SPIV);
957 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
958
959 printk(KERN_DEBUG "... APIC ISR field:\n");
960 print_APIC_bitfield(APIC_ISR);
961 printk(KERN_DEBUG "... APIC TMR field:\n");
962 print_APIC_bitfield(APIC_TMR);
963 printk(KERN_DEBUG "... APIC IRR field:\n");
964 print_APIC_bitfield(APIC_IRR);
965
966 v = apic_read(APIC_ESR);
967 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
968
969 v = apic_read(APIC_ICR);
970 printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
971 v = apic_read(APIC_ICR2);
972 printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
973
974 v = apic_read(APIC_LVTT);
975 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
976
977 if (maxlvt > 3) { /* PC is LVT#4. */
978 v = apic_read(APIC_LVTPC);
979 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
980 }
981 v = apic_read(APIC_LVT0);
982 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
983 v = apic_read(APIC_LVT1);
984 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
985
986 if (maxlvt > 2) { /* ERR is LVT#3. */
987 v = apic_read(APIC_LVTERR);
988 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
989 }
990
991 v = apic_read(APIC_TMICT);
992 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
993 v = apic_read(APIC_TMCCT);
994 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
995 v = apic_read(APIC_TDCR);
996 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
997 printk("\n");
998 }
999
1000 void print_all_local_APICs (void)
1001 {
1002 on_each_cpu(print_local_APIC, NULL, 1, 1);
1003 }
1004
1005 void __apicdebuginit print_PIC(void)
1006 {
1007 unsigned int v;
1008 unsigned long flags;
1009
1010 if (apic_verbosity == APIC_QUIET)
1011 return;
1012
1013 printk(KERN_DEBUG "\nprinting PIC contents\n");
1014
1015 spin_lock_irqsave(&i8259A_lock, flags);
1016
1017 v = inb(0xa1) << 8 | inb(0x21);
1018 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1019
1020 v = inb(0xa0) << 8 | inb(0x20);
1021 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1022
1023 outb(0x0b,0xa0);
1024 outb(0x0b,0x20);
1025 v = inb(0xa0) << 8 | inb(0x20);
1026 outb(0x0a,0xa0);
1027 outb(0x0a,0x20);
1028
1029 spin_unlock_irqrestore(&i8259A_lock, flags);
1030
1031 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1032
1033 v = inb(0x4d1) << 8 | inb(0x4d0);
1034 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1035 }
1036
1037 #endif /* 0 */
1038
1039 static void __init enable_IO_APIC(void)
1040 {
1041 union IO_APIC_reg_01 reg_01;
1042 int i8259_apic, i8259_pin;
1043 int i, apic;
1044 unsigned long flags;
1045
1046 for (i = 0; i < PIN_MAP_SIZE; i++) {
1047 irq_2_pin[i].pin = -1;
1048 irq_2_pin[i].next = 0;
1049 }
1050
1051 /*
1052 * The number of IO-APIC IRQ registers (== #pins):
1053 */
1054 for (apic = 0; apic < nr_ioapics; apic++) {
1055 spin_lock_irqsave(&ioapic_lock, flags);
1056 reg_01.raw = io_apic_read(apic, 1);
1057 spin_unlock_irqrestore(&ioapic_lock, flags);
1058 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1059 }
1060 for(apic = 0; apic < nr_ioapics; apic++) {
1061 int pin;
1062 /* See if any of the pins is in ExtINT mode */
1063 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1064 struct IO_APIC_route_entry entry;
1065 entry = ioapic_read_entry(apic, pin);
1066
1067 /* If the interrupt line is enabled and in ExtInt mode
1068 * I have found the pin where the i8259 is connected.
1069 */
1070 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1071 ioapic_i8259.apic = apic;
1072 ioapic_i8259.pin = pin;
1073 goto found_i8259;
1074 }
1075 }
1076 }
1077 found_i8259:
1078 /* Look to see what if the MP table has reported the ExtINT */
1079 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1080 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1081 /* Trust the MP table if nothing is setup in the hardware */
1082 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1083 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1084 ioapic_i8259.pin = i8259_pin;
1085 ioapic_i8259.apic = i8259_apic;
1086 }
1087 /* Complain if the MP table and the hardware disagree */
1088 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1089 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1090 {
1091 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1092 }
1093
1094 /*
1095 * Do not trust the IO-APIC being empty at bootup
1096 */
1097 clear_IO_APIC();
1098 }
1099
1100 /*
1101 * Not an __init, needed by the reboot code
1102 */
1103 void disable_IO_APIC(void)
1104 {
1105 /*
1106 * Clear the IO-APIC before rebooting:
1107 */
1108 clear_IO_APIC();
1109
1110 /*
1111 * If the i8259 is routed through an IOAPIC
1112 * Put that IOAPIC in virtual wire mode
1113 * so legacy interrupts can be delivered.
1114 */
1115 if (ioapic_i8259.pin != -1) {
1116 struct IO_APIC_route_entry entry;
1117
1118 memset(&entry, 0, sizeof(entry));
1119 entry.mask = 0; /* Enabled */
1120 entry.trigger = 0; /* Edge */
1121 entry.irr = 0;
1122 entry.polarity = 0; /* High */
1123 entry.delivery_status = 0;
1124 entry.dest_mode = 0; /* Physical */
1125 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1126 entry.vector = 0;
1127 entry.dest.physical.physical_dest =
1128 GET_APIC_ID(apic_read(APIC_ID));
1129
1130 /*
1131 * Add it to the IO-APIC irq-routing table:
1132 */
1133 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1134 }
1135
1136 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1137 }
1138
1139 /*
1140 * There is a nasty bug in some older SMP boards, their mptable lies
1141 * about the timer IRQ. We do the following to work around the situation:
1142 *
1143 * - timer IRQ defaults to IO-APIC IRQ
1144 * - if this function detects that timer IRQs are defunct, then we fall
1145 * back to ISA timer IRQs
1146 */
1147 static int __init timer_irq_works(void)
1148 {
1149 unsigned long t1 = jiffies;
1150
1151 local_irq_enable();
1152 /* Let ten ticks pass... */
1153 mdelay((10 * 1000) / HZ);
1154
1155 /*
1156 * Expect a few ticks at least, to be sure some possible
1157 * glue logic does not lock up after one or two first
1158 * ticks in a non-ExtINT mode. Also the local APIC
1159 * might have cached one ExtINT interrupt. Finally, at
1160 * least one tick may be lost due to delays.
1161 */
1162
1163 /* jiffies wrap? */
1164 if (jiffies - t1 > 4)
1165 return 1;
1166 return 0;
1167 }
1168
1169 /*
1170 * In the SMP+IOAPIC case it might happen that there are an unspecified
1171 * number of pending IRQ events unhandled. These cases are very rare,
1172 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1173 * better to do it this way as thus we do not have to be aware of
1174 * 'pending' interrupts in the IRQ path, except at this point.
1175 */
1176 /*
1177 * Edge triggered needs to resend any interrupt
1178 * that was delayed but this is now handled in the device
1179 * independent code.
1180 */
1181
1182 /*
1183 * Starting up a edge-triggered IO-APIC interrupt is
1184 * nasty - we need to make sure that we get the edge.
1185 * If it is already asserted for some reason, we need
1186 * return 1 to indicate that is was pending.
1187 *
1188 * This is not complete - we should be able to fake
1189 * an edge even if it isn't on the 8259A...
1190 */
1191
1192 static unsigned int startup_ioapic_irq(unsigned int irq)
1193 {
1194 int was_pending = 0;
1195 unsigned long flags;
1196
1197 spin_lock_irqsave(&ioapic_lock, flags);
1198 if (irq < 16) {
1199 disable_8259A_irq(irq);
1200 if (i8259A_irq_pending(irq))
1201 was_pending = 1;
1202 }
1203 __unmask_IO_APIC_irq(irq);
1204 spin_unlock_irqrestore(&ioapic_lock, flags);
1205
1206 return was_pending;
1207 }
1208
1209 static unsigned int startup_ioapic_vector(unsigned int vector)
1210 {
1211 int irq = vector_to_irq(vector);
1212
1213 return startup_ioapic_irq(irq);
1214 }
1215
1216 static void mask_ioapic_vector (unsigned int vector)
1217 {
1218 int irq = vector_to_irq(vector);
1219
1220 mask_IO_APIC_irq(irq);
1221 }
1222
1223 static void unmask_ioapic_vector (unsigned int vector)
1224 {
1225 int irq = vector_to_irq(vector);
1226
1227 unmask_IO_APIC_irq(irq);
1228 }
1229
1230 #ifdef CONFIG_SMP
1231 static void set_ioapic_affinity_vector (unsigned int vector,
1232 cpumask_t cpu_mask)
1233 {
1234 int irq = vector_to_irq(vector);
1235
1236 set_native_irq_info(vector, cpu_mask);
1237 set_ioapic_affinity_irq(irq, cpu_mask);
1238 }
1239 #endif // CONFIG_SMP
1240
1241 static int ioapic_retrigger_vector(unsigned int vector)
1242 {
1243 int irq = vector_to_irq(vector);
1244
1245 send_IPI_self(IO_APIC_VECTOR(irq));
1246
1247 return 1;
1248 }
1249
1250 /*
1251 * Level and edge triggered IO-APIC interrupts need different handling,
1252 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1253 * handled with the level-triggered descriptor, but that one has slightly
1254 * more overhead. Level-triggered interrupts cannot be handled with the
1255 * edge-triggered handler, without risking IRQ storms and other ugly
1256 * races.
1257 */
1258
1259 static void ack_apic_edge(unsigned int irq)
1260 {
1261 move_native_irq(irq);
1262 ack_APIC_irq();
1263 }
1264
1265 static void ack_apic_level(unsigned int irq)
1266 {
1267 int do_unmask_irq = 0;
1268
1269 #if defined(CONFIG_GENERIC_PENDING_IRQ) || defined(CONFIG_IRQBALANCE)
1270 /* If we are moving the irq we need to mask it */
1271 if (unlikely(irq_desc[irq].status & IRQ_MOVE_PENDING)) {
1272 do_unmask_irq = 1;
1273 mask_IO_APIC_irq(irq);
1274 }
1275 #endif
1276
1277 /*
1278 * We must acknowledge the irq before we move it or the acknowledge will
1279 * not propogate properly.
1280 */
1281 ack_APIC_irq();
1282
1283 /* Now we can move and renable the irq */
1284 move_masked_irq(irq);
1285 if (unlikely(do_unmask_irq))
1286 unmask_IO_APIC_irq(irq);
1287 }
1288
1289 static struct irq_chip ioapic_chip __read_mostly = {
1290 .name = "IO-APIC",
1291 .startup = startup_ioapic_vector,
1292 .mask = mask_ioapic_vector,
1293 .unmask = unmask_ioapic_vector,
1294 .ack = ack_apic_edge,
1295 .eoi = ack_apic_level,
1296 #ifdef CONFIG_SMP
1297 .set_affinity = set_ioapic_affinity_vector,
1298 #endif
1299 .retrigger = ioapic_retrigger_vector,
1300 };
1301
1302 static inline void init_IO_APIC_traps(void)
1303 {
1304 int irq;
1305
1306 /*
1307 * NOTE! The local APIC isn't very good at handling
1308 * multiple interrupts at the same interrupt level.
1309 * As the interrupt level is determined by taking the
1310 * vector number and shifting that right by 4, we
1311 * want to spread these out a bit so that they don't
1312 * all fall in the same interrupt level.
1313 *
1314 * Also, we've got to be careful not to trash gate
1315 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1316 */
1317 for (irq = 0; irq < NR_IRQS ; irq++) {
1318 int tmp = irq;
1319 if (use_pci_vector()) {
1320 if (!platform_legacy_irq(tmp))
1321 if ((tmp = vector_to_irq(tmp)) == -1)
1322 continue;
1323 }
1324 if (IO_APIC_IRQ(tmp) && !IO_APIC_VECTOR(tmp)) {
1325 /*
1326 * Hmm.. We don't have an entry for this,
1327 * so default to an old-fashioned 8259
1328 * interrupt if we can..
1329 */
1330 if (irq < 16)
1331 make_8259A_irq(irq);
1332 else
1333 /* Strange. Oh, well.. */
1334 irq_desc[irq].chip = &no_irq_chip;
1335 }
1336 }
1337 }
1338
1339 static void enable_lapic_irq (unsigned int irq)
1340 {
1341 unsigned long v;
1342
1343 v = apic_read(APIC_LVT0);
1344 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
1345 }
1346
1347 static void disable_lapic_irq (unsigned int irq)
1348 {
1349 unsigned long v;
1350
1351 v = apic_read(APIC_LVT0);
1352 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1353 }
1354
1355 static void ack_lapic_irq (unsigned int irq)
1356 {
1357 ack_APIC_irq();
1358 }
1359
1360 static void end_lapic_irq (unsigned int i) { /* nothing */ }
1361
1362 static struct hw_interrupt_type lapic_irq_type __read_mostly = {
1363 .typename = "local-APIC-edge",
1364 .startup = NULL, /* startup_irq() not used for IRQ0 */
1365 .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
1366 .enable = enable_lapic_irq,
1367 .disable = disable_lapic_irq,
1368 .ack = ack_lapic_irq,
1369 .end = end_lapic_irq,
1370 };
1371
1372 static void setup_nmi (void)
1373 {
1374 /*
1375 * Dirty trick to enable the NMI watchdog ...
1376 * We put the 8259A master into AEOI mode and
1377 * unmask on all local APICs LVT0 as NMI.
1378 *
1379 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1380 * is from Maciej W. Rozycki - so we do not have to EOI from
1381 * the NMI handler or the timer interrupt.
1382 */
1383 printk(KERN_INFO "activating NMI Watchdog ...");
1384
1385 enable_NMI_through_LVT0(NULL);
1386
1387 printk(" done.\n");
1388 }
1389
1390 /*
1391 * This looks a bit hackish but it's about the only one way of sending
1392 * a few INTA cycles to 8259As and any associated glue logic. ICR does
1393 * not support the ExtINT mode, unfortunately. We need to send these
1394 * cycles as some i82489DX-based boards have glue logic that keeps the
1395 * 8259A interrupt line asserted until INTA. --macro
1396 */
1397 static inline void unlock_ExtINT_logic(void)
1398 {
1399 int apic, pin, i;
1400 struct IO_APIC_route_entry entry0, entry1;
1401 unsigned char save_control, save_freq_select;
1402 unsigned long flags;
1403
1404 pin = find_isa_irq_pin(8, mp_INT);
1405 apic = find_isa_irq_apic(8, mp_INT);
1406 if (pin == -1)
1407 return;
1408
1409 spin_lock_irqsave(&ioapic_lock, flags);
1410 *(((int *)&entry0) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
1411 *(((int *)&entry0) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
1412 spin_unlock_irqrestore(&ioapic_lock, flags);
1413 clear_IO_APIC_pin(apic, pin);
1414
1415 memset(&entry1, 0, sizeof(entry1));
1416
1417 entry1.dest_mode = 0; /* physical delivery */
1418 entry1.mask = 0; /* unmask IRQ now */
1419 entry1.dest.physical.physical_dest = hard_smp_processor_id();
1420 entry1.delivery_mode = dest_ExtINT;
1421 entry1.polarity = entry0.polarity;
1422 entry1.trigger = 0;
1423 entry1.vector = 0;
1424
1425 spin_lock_irqsave(&ioapic_lock, flags);
1426 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
1427 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
1428 spin_unlock_irqrestore(&ioapic_lock, flags);
1429
1430 save_control = CMOS_READ(RTC_CONTROL);
1431 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1432 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1433 RTC_FREQ_SELECT);
1434 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1435
1436 i = 100;
1437 while (i-- > 0) {
1438 mdelay(10);
1439 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1440 i -= 10;
1441 }
1442
1443 CMOS_WRITE(save_control, RTC_CONTROL);
1444 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1445 clear_IO_APIC_pin(apic, pin);
1446
1447 spin_lock_irqsave(&ioapic_lock, flags);
1448 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
1449 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
1450 spin_unlock_irqrestore(&ioapic_lock, flags);
1451 }
1452
1453 int timer_uses_ioapic_pin_0;
1454
1455 /*
1456 * This code may look a bit paranoid, but it's supposed to cooperate with
1457 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
1458 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
1459 * fanatically on his truly buggy board.
1460 *
1461 * FIXME: really need to revamp this for modern platforms only.
1462 */
1463 static inline void check_timer(void)
1464 {
1465 int apic1, pin1, apic2, pin2;
1466 int vector;
1467
1468 /*
1469 * get/set the timer IRQ vector:
1470 */
1471 disable_8259A_irq(0);
1472 vector = assign_irq_vector(0);
1473 set_intr_gate(vector, interrupt[0]);
1474
1475 /*
1476 * Subtle, code in do_timer_interrupt() expects an AEOI
1477 * mode for the 8259A whenever interrupts are routed
1478 * through I/O APICs. Also IRQ0 has to be enabled in
1479 * the 8259A which implies the virtual wire has to be
1480 * disabled in the local APIC.
1481 */
1482 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1483 init_8259A(1);
1484 if (timer_over_8254 > 0)
1485 enable_8259A_irq(0);
1486
1487 pin1 = find_isa_irq_pin(0, mp_INT);
1488 apic1 = find_isa_irq_apic(0, mp_INT);
1489 pin2 = ioapic_i8259.pin;
1490 apic2 = ioapic_i8259.apic;
1491
1492 if (pin1 == 0)
1493 timer_uses_ioapic_pin_0 = 1;
1494
1495 apic_printk(APIC_VERBOSE,KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
1496 vector, apic1, pin1, apic2, pin2);
1497
1498 if (pin1 != -1) {
1499 /*
1500 * Ok, does IRQ0 through the IOAPIC work?
1501 */
1502 unmask_IO_APIC_irq(0);
1503 if (!no_timer_check && timer_irq_works()) {
1504 nmi_watchdog_default();
1505 if (nmi_watchdog == NMI_IO_APIC) {
1506 disable_8259A_irq(0);
1507 setup_nmi();
1508 enable_8259A_irq(0);
1509 }
1510 if (disable_timer_pin_1 > 0)
1511 clear_IO_APIC_pin(0, pin1);
1512 return;
1513 }
1514 clear_IO_APIC_pin(apic1, pin1);
1515 apic_printk(APIC_QUIET,KERN_ERR "..MP-BIOS bug: 8254 timer not "
1516 "connected to IO-APIC\n");
1517 }
1518
1519 apic_printk(APIC_VERBOSE,KERN_INFO "...trying to set up timer (IRQ0) "
1520 "through the 8259A ... ");
1521 if (pin2 != -1) {
1522 apic_printk(APIC_VERBOSE,"\n..... (found apic %d pin %d) ...",
1523 apic2, pin2);
1524 /*
1525 * legacy devices should be connected to IO APIC #0
1526 */
1527 setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
1528 if (timer_irq_works()) {
1529 apic_printk(APIC_VERBOSE," works.\n");
1530 nmi_watchdog_default();
1531 if (nmi_watchdog == NMI_IO_APIC) {
1532 setup_nmi();
1533 }
1534 return;
1535 }
1536 /*
1537 * Cleanup, just in case ...
1538 */
1539 clear_IO_APIC_pin(apic2, pin2);
1540 }
1541 apic_printk(APIC_VERBOSE," failed.\n");
1542
1543 if (nmi_watchdog == NMI_IO_APIC) {
1544 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1545 nmi_watchdog = 0;
1546 }
1547
1548 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1549
1550 disable_8259A_irq(0);
1551 irq_desc[0].chip = &lapic_irq_type;
1552 apic_write(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */
1553 enable_8259A_irq(0);
1554
1555 if (timer_irq_works()) {
1556 apic_printk(APIC_VERBOSE," works.\n");
1557 return;
1558 }
1559 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
1560 apic_printk(APIC_VERBOSE," failed.\n");
1561
1562 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1563
1564 init_8259A(0);
1565 make_8259A_irq(0);
1566 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1567
1568 unlock_ExtINT_logic();
1569
1570 if (timer_irq_works()) {
1571 apic_printk(APIC_VERBOSE," works.\n");
1572 return;
1573 }
1574 apic_printk(APIC_VERBOSE," failed :(.\n");
1575 panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n");
1576 }
1577
1578 static int __init notimercheck(char *s)
1579 {
1580 no_timer_check = 1;
1581 return 1;
1582 }
1583 __setup("no_timer_check", notimercheck);
1584
1585 /*
1586 *
1587 * IRQ's that are handled by the PIC in the MPS IOAPIC case.
1588 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1589 * Linux doesn't really care, as it's not actually used
1590 * for any interrupt handling anyway.
1591 */
1592 #define PIC_IRQS (1<<2)
1593
1594 void __init setup_IO_APIC(void)
1595 {
1596 enable_IO_APIC();
1597
1598 if (acpi_ioapic)
1599 io_apic_irqs = ~0; /* all IRQs go through IOAPIC */
1600 else
1601 io_apic_irqs = ~PIC_IRQS;
1602
1603 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
1604
1605 sync_Arb_IDs();
1606 setup_IO_APIC_irqs();
1607 init_IO_APIC_traps();
1608 check_timer();
1609 if (!acpi_ioapic)
1610 print_IO_APIC();
1611 }
1612
1613 struct sysfs_ioapic_data {
1614 struct sys_device dev;
1615 struct IO_APIC_route_entry entry[0];
1616 };
1617 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
1618
1619 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
1620 {
1621 struct IO_APIC_route_entry *entry;
1622 struct sysfs_ioapic_data *data;
1623 int i;
1624
1625 data = container_of(dev, struct sysfs_ioapic_data, dev);
1626 entry = data->entry;
1627 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
1628 *entry = ioapic_read_entry(dev->id, i);
1629
1630 return 0;
1631 }
1632
1633 static int ioapic_resume(struct sys_device *dev)
1634 {
1635 struct IO_APIC_route_entry *entry;
1636 struct sysfs_ioapic_data *data;
1637 unsigned long flags;
1638 union IO_APIC_reg_00 reg_00;
1639 int i;
1640
1641 data = container_of(dev, struct sysfs_ioapic_data, dev);
1642 entry = data->entry;
1643
1644 spin_lock_irqsave(&ioapic_lock, flags);
1645 reg_00.raw = io_apic_read(dev->id, 0);
1646 if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
1647 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
1648 io_apic_write(dev->id, 0, reg_00.raw);
1649 }
1650 spin_unlock_irqrestore(&ioapic_lock, flags);
1651 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
1652 ioapic_write_entry(dev->id, i, entry[i]);
1653
1654 return 0;
1655 }
1656
1657 static struct sysdev_class ioapic_sysdev_class = {
1658 set_kset_name("ioapic"),
1659 .suspend = ioapic_suspend,
1660 .resume = ioapic_resume,
1661 };
1662
1663 static int __init ioapic_init_sysfs(void)
1664 {
1665 struct sys_device * dev;
1666 int i, size, error = 0;
1667
1668 error = sysdev_class_register(&ioapic_sysdev_class);
1669 if (error)
1670 return error;
1671
1672 for (i = 0; i < nr_ioapics; i++ ) {
1673 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
1674 * sizeof(struct IO_APIC_route_entry);
1675 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
1676 if (!mp_ioapic_data[i]) {
1677 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1678 continue;
1679 }
1680 memset(mp_ioapic_data[i], 0, size);
1681 dev = &mp_ioapic_data[i]->dev;
1682 dev->id = i;
1683 dev->cls = &ioapic_sysdev_class;
1684 error = sysdev_register(dev);
1685 if (error) {
1686 kfree(mp_ioapic_data[i]);
1687 mp_ioapic_data[i] = NULL;
1688 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1689 continue;
1690 }
1691 }
1692
1693 return 0;
1694 }
1695
1696 device_initcall(ioapic_init_sysfs);
1697
1698 #ifdef CONFIG_PCI_MSI
1699 /*
1700 * Dynamic irq allocate and deallocation for MSI
1701 */
1702 int create_irq(void)
1703 {
1704 /* Hack of the day: irq == vector.
1705 *
1706 * Ultimately this will be be more general,
1707 * and not depend on the irq to vector identity mapping.
1708 * But this version is needed until msi.c can cope with
1709 * the more general form.
1710 */
1711 int irq, vector;
1712 unsigned long flags;
1713 vector = assign_irq_vector(AUTO_ASSIGN);
1714 irq = vector;
1715
1716 if (vector >= 0) {
1717 spin_lock_irqsave(&vector_lock, flags);
1718 vector_irq[vector] = irq;
1719 irq_vector[irq] = vector;
1720 spin_unlock_irqrestore(&vector_lock, flags);
1721
1722 set_intr_gate(vector, interrupt[irq]);
1723
1724 dynamic_irq_init(irq);
1725 }
1726 return irq;
1727 }
1728
1729 void destroy_irq(unsigned int irq)
1730 {
1731 unsigned long flags;
1732 unsigned int vector;
1733
1734 dynamic_irq_cleanup(irq);
1735
1736 spin_lock_irqsave(&vector_lock, flags);
1737 vector = irq_vector[irq];
1738 vector_irq[vector] = -1;
1739 irq_vector[irq] = 0;
1740 spin_unlock_irqrestore(&vector_lock, flags);
1741 }
1742 #endif
1743
1744 /*
1745 * MSI mesage composition
1746 */
1747 #ifdef CONFIG_PCI_MSI
1748 static int msi_msg_setup(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
1749 {
1750 /* For now always this code always uses physical delivery
1751 * mode.
1752 */
1753 int vector;
1754 unsigned dest;
1755
1756 vector = assign_irq_vector(irq);
1757 if (vector >= 0) {
1758 cpumask_t tmp;
1759
1760 cpus_clear(tmp);
1761 cpu_set(first_cpu(cpu_online_map), tmp);
1762 dest = cpu_mask_to_apicid(tmp);
1763
1764 msg->address_hi = MSI_ADDR_BASE_HI;
1765 msg->address_lo =
1766 MSI_ADDR_BASE_LO |
1767 ((INT_DEST_MODE == 0) ?
1768 MSI_ADDR_DEST_MODE_PHYSICAL:
1769 MSI_ADDR_DEST_MODE_LOGICAL) |
1770 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1771 MSI_ADDR_REDIRECTION_CPU:
1772 MSI_ADDR_REDIRECTION_LOWPRI) |
1773 MSI_ADDR_DEST_ID(dest);
1774
1775 msg->data =
1776 MSI_DATA_TRIGGER_EDGE |
1777 MSI_DATA_LEVEL_ASSERT |
1778 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1779 MSI_DATA_DELIVERY_FIXED:
1780 MSI_DATA_DELIVERY_LOWPRI) |
1781 MSI_DATA_VECTOR(vector);
1782 }
1783 return vector;
1784 }
1785
1786 static void msi_msg_teardown(unsigned int irq)
1787 {
1788 return;
1789 }
1790
1791 static void msi_msg_set_affinity(unsigned int irq, cpumask_t mask, struct msi_msg *msg)
1792 {
1793 int vector;
1794 unsigned dest;
1795
1796 vector = assign_irq_vector(irq);
1797 if (vector > 0) {
1798 dest = cpu_mask_to_apicid(mask);
1799
1800 msg->data &= ~MSI_DATA_VECTOR_MASK;
1801 msg->data |= MSI_DATA_VECTOR(vector);
1802 msg->address_lo &= ~MSI_ADDR_DEST_ID_MASK;
1803 msg->address_lo |= MSI_ADDR_DEST_ID(dest);
1804 }
1805 }
1806
1807 struct msi_ops arch_msi_ops = {
1808 .needs_64bit_address = 0,
1809 .setup = msi_msg_setup,
1810 .teardown = msi_msg_teardown,
1811 .target = msi_msg_set_affinity,
1812 };
1813
1814 #endif
1815
1816 /* --------------------------------------------------------------------------
1817 ACPI-based IOAPIC Configuration
1818 -------------------------------------------------------------------------- */
1819
1820 #ifdef CONFIG_ACPI
1821
1822 #define IO_APIC_MAX_ID 0xFE
1823
1824 int __init io_apic_get_redir_entries (int ioapic)
1825 {
1826 union IO_APIC_reg_01 reg_01;
1827 unsigned long flags;
1828
1829 spin_lock_irqsave(&ioapic_lock, flags);
1830 reg_01.raw = io_apic_read(ioapic, 1);
1831 spin_unlock_irqrestore(&ioapic_lock, flags);
1832
1833 return reg_01.bits.entries;
1834 }
1835
1836
1837 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
1838 {
1839 struct IO_APIC_route_entry entry;
1840 unsigned long flags;
1841
1842 if (!IO_APIC_IRQ(irq)) {
1843 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
1844 ioapic);
1845 return -EINVAL;
1846 }
1847
1848 /*
1849 * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
1850 * Note that we mask (disable) IRQs now -- these get enabled when the
1851 * corresponding device driver registers for this IRQ.
1852 */
1853
1854 memset(&entry,0,sizeof(entry));
1855
1856 entry.delivery_mode = INT_DELIVERY_MODE;
1857 entry.dest_mode = INT_DEST_MODE;
1858 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
1859 entry.trigger = triggering;
1860 entry.polarity = polarity;
1861 entry.mask = 1; /* Disabled (masked) */
1862
1863 irq = gsi_irq_sharing(irq);
1864 /*
1865 * IRQs < 16 are already in the irq_2_pin[] map
1866 */
1867 if (irq >= 16)
1868 add_pin_to_irq(irq, ioapic, pin);
1869
1870 entry.vector = assign_irq_vector(irq);
1871
1872 apic_printk(APIC_VERBOSE,KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry (%d-%d -> 0x%x -> "
1873 "IRQ %d Mode:%i Active:%i)\n", ioapic,
1874 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
1875 triggering, polarity);
1876
1877 ioapic_register_intr(irq, entry.vector, triggering);
1878
1879 if (!ioapic && (irq < 16))
1880 disable_8259A_irq(irq);
1881
1882 ioapic_write_entry(ioapic, pin, entry);
1883
1884 spin_lock_irqsave(&ioapic_lock, flags);
1885 set_native_irq_info(use_pci_vector() ? entry.vector : irq, TARGET_CPUS);
1886 spin_unlock_irqrestore(&ioapic_lock, flags);
1887
1888 return 0;
1889 }
1890
1891 #endif /* CONFIG_ACPI */
1892
1893
1894 /*
1895 * This function currently is only a helper for the i386 smp boot process where
1896 * we need to reprogram the ioredtbls to cater for the cpus which have come online
1897 * so mask in all cases should simply be TARGET_CPUS
1898 */
1899 #ifdef CONFIG_SMP
1900 void __init setup_ioapic_dest(void)
1901 {
1902 int pin, ioapic, irq, irq_entry;
1903
1904 if (skip_ioapic_setup == 1)
1905 return;
1906
1907 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
1908 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
1909 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
1910 if (irq_entry == -1)
1911 continue;
1912 irq = pin_2_irq(irq_entry, ioapic, pin);
1913 set_ioapic_affinity_irq(irq, TARGET_CPUS);
1914 }
1915
1916 }
1917 }
1918 #endif
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