2 * sata_sil24.c - Driver for Silicon Image 3124/3132 SATA-2 controllers
4 * Copyright 2005 Tejun Heo
6 * Based on preview driver from Silicon Image.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2, or (at your option) any
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/pci.h>
23 #include <linux/blkdev.h>
24 #include <linux/delay.h>
25 #include <linux/interrupt.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/device.h>
28 #include <scsi/scsi_host.h>
29 #include <scsi/scsi_cmnd.h>
30 #include <linux/libata.h>
33 #define DRV_NAME "sata_sil24"
34 #define DRV_VERSION "0.23"
37 * Port request block (PRB) 32 bytes
47 * Scatter gather entry (SGE) 16 bytes
58 struct sil24_port_multiplier
{
65 * Global controller registers (128 bytes @ BAR0)
68 HOST_SLOT_STAT
= 0x00, /* 32 bit slot stat * 4 */
72 HOST_BIST_CTRL
= 0x50,
73 HOST_BIST_PTRN
= 0x54,
74 HOST_BIST_STAT
= 0x58,
75 HOST_MEM_BIST_STAT
= 0x5c,
76 HOST_FLASH_CMD
= 0x70,
78 HOST_FLASH_DATA
= 0x74,
79 HOST_TRANSITION_DETECT
= 0x75,
80 HOST_GPIO_CTRL
= 0x76,
81 HOST_I2C_ADDR
= 0x78, /* 32 bit */
83 HOST_I2C_XFER_CNT
= 0x7e,
86 /* HOST_SLOT_STAT bits */
87 HOST_SSTAT_ATTN
= (1 << 31),
91 * (8192 bytes @ +0x0000, +0x2000, +0x4000 and +0x6000 @ BAR2)
93 PORT_REGS_SIZE
= 0x2000,
94 PORT_PRB
= 0x0000, /* (32 bytes PRB + 16 bytes SGEs * 6) * 31 (3968 bytes) */
96 PORT_PM
= 0x0f80, /* 8 bytes PM * 16 (128 bytes) */
98 PORT_CTRL_STAT
= 0x1000, /* write: ctrl-set, read: stat */
99 PORT_CTRL_CLR
= 0x1004, /* write: ctrl-clear */
100 PORT_IRQ_STAT
= 0x1008, /* high: status, low: interrupt */
101 PORT_IRQ_ENABLE_SET
= 0x1010, /* write: enable-set */
102 PORT_IRQ_ENABLE_CLR
= 0x1014, /* write: enable-clear */
103 PORT_ACTIVATE_UPPER_ADDR
= 0x101c,
104 PORT_EXEC_FIFO
= 0x1020, /* command execution fifo */
105 PORT_CMD_ERR
= 0x1024, /* command error number */
106 PORT_FIS_CFG
= 0x1028,
107 PORT_FIFO_THRES
= 0x102c,
109 PORT_DECODE_ERR_CNT
= 0x1040,
110 PORT_DECODE_ERR_THRESH
= 0x1042,
111 PORT_CRC_ERR_CNT
= 0x1044,
112 PORT_CRC_ERR_THRESH
= 0x1046,
113 PORT_HSHK_ERR_CNT
= 0x1048,
114 PORT_HSHK_ERR_THRESH
= 0x104a,
116 PORT_PHY_CFG
= 0x1050,
117 PORT_SLOT_STAT
= 0x1800,
118 PORT_CMD_ACTIVATE
= 0x1c00, /* 64 bit cmd activate * 31 (248 bytes) */
119 PORT_EXEC_DIAG
= 0x1e00, /* 32bit exec diag * 16 (64 bytes, 0-10 used on 3124) */
120 PORT_PSD_DIAG
= 0x1e40, /* 32bit psd diag * 16 (64 bytes, 0-8 used on 3124) */
121 PORT_SCONTROL
= 0x1f00,
122 PORT_SSTATUS
= 0x1f04,
123 PORT_SERROR
= 0x1f08,
124 PORT_SACTIVE
= 0x1f0c,
126 /* PORT_CTRL_STAT bits */
127 PORT_CS_PORT_RST
= (1 << 0), /* port reset */
128 PORT_CS_DEV_RST
= (1 << 1), /* device reset */
129 PORT_CS_INIT
= (1 << 2), /* port initialize */
130 PORT_CS_IRQ_WOC
= (1 << 3), /* interrupt write one to clear */
131 PORT_CS_CDB16
= (1 << 5), /* 0=12b cdb, 1=16b cdb */
132 PORT_CS_RESUME
= (1 << 6), /* port resume */
133 PORT_CS_32BIT_ACTV
= (1 << 10), /* 32-bit activation */
134 PORT_CS_PM_EN
= (1 << 13), /* port multiplier enable */
135 PORT_CS_RDY
= (1 << 31), /* port ready to accept commands */
137 /* PORT_IRQ_STAT/ENABLE_SET/CLR */
138 /* bits[11:0] are masked */
139 PORT_IRQ_COMPLETE
= (1 << 0), /* command(s) completed */
140 PORT_IRQ_ERROR
= (1 << 1), /* command execution error */
141 PORT_IRQ_PORTRDY_CHG
= (1 << 2), /* port ready change */
142 PORT_IRQ_PWR_CHG
= (1 << 3), /* power management change */
143 PORT_IRQ_PHYRDY_CHG
= (1 << 4), /* PHY ready change */
144 PORT_IRQ_COMWAKE
= (1 << 5), /* COMWAKE received */
145 PORT_IRQ_UNK_FIS
= (1 << 6), /* Unknown FIS received */
146 PORT_IRQ_SDB_FIS
= (1 << 11), /* SDB FIS received */
148 /* bits[27:16] are unmasked (raw) */
149 PORT_IRQ_RAW_SHIFT
= 16,
150 PORT_IRQ_MASKED_MASK
= 0x7ff,
151 PORT_IRQ_RAW_MASK
= (0x7ff << PORT_IRQ_RAW_SHIFT
),
153 /* ENABLE_SET/CLR specific, intr steering - 2 bit field */
154 PORT_IRQ_STEER_SHIFT
= 30,
155 PORT_IRQ_STEER_MASK
= (3 << PORT_IRQ_STEER_SHIFT
),
157 /* PORT_CMD_ERR constants */
158 PORT_CERR_DEV
= 1, /* Error bit in D2H Register FIS */
159 PORT_CERR_SDB
= 2, /* Error bit in SDB FIS */
160 PORT_CERR_DATA
= 3, /* Error in data FIS not detected by dev */
161 PORT_CERR_SEND
= 4, /* Initial cmd FIS transmission failure */
162 PORT_CERR_INCONSISTENT
= 5, /* Protocol mismatch */
163 PORT_CERR_DIRECTION
= 6, /* Data direction mismatch */
164 PORT_CERR_UNDERRUN
= 7, /* Ran out of SGEs while writing */
165 PORT_CERR_OVERRUN
= 8, /* Ran out of SGEs while reading */
166 PORT_CERR_PKT_PROT
= 11, /* DIR invalid in 1st PIO setup of ATAPI */
167 PORT_CERR_SGT_BOUNDARY
= 16, /* PLD ecode 00 - SGT not on qword boundary */
168 PORT_CERR_SGT_TGTABRT
= 17, /* PLD ecode 01 - target abort */
169 PORT_CERR_SGT_MSTABRT
= 18, /* PLD ecode 10 - master abort */
170 PORT_CERR_SGT_PCIPERR
= 19, /* PLD ecode 11 - PCI parity err while fetching SGT */
171 PORT_CERR_CMD_BOUNDARY
= 24, /* ctrl[15:13] 001 - PRB not on qword boundary */
172 PORT_CERR_CMD_TGTABRT
= 25, /* ctrl[15:13] 010 - target abort */
173 PORT_CERR_CMD_MSTABRT
= 26, /* ctrl[15:13] 100 - master abort */
174 PORT_CERR_CMD_PCIPERR
= 27, /* ctrl[15:13] 110 - PCI parity err while fetching PRB */
175 PORT_CERR_XFR_UNDEF
= 32, /* PSD ecode 00 - undefined */
176 PORT_CERR_XFR_TGTABRT
= 33, /* PSD ecode 01 - target abort */
177 PORT_CERR_XFR_MSGABRT
= 34, /* PSD ecode 10 - master abort */
178 PORT_CERR_XFR_PCIPERR
= 35, /* PSD ecode 11 - PCI prity err during transfer */
179 PORT_CERR_SENDSERVICE
= 36, /* FIS received while sending service */
181 /* bits of PRB control field */
182 PRB_CTRL_PROTOCOL
= (1 << 0), /* override def. ATA protocol */
183 PRB_CTRL_PACKET_READ
= (1 << 4), /* PACKET cmd read */
184 PRB_CTRL_PACKET_WRITE
= (1 << 5), /* PACKET cmd write */
185 PRB_CTRL_NIEN
= (1 << 6), /* Mask completion irq */
186 PRB_CTRL_SRST
= (1 << 7), /* Soft reset request (ign BSY?) */
188 /* PRB protocol field */
189 PRB_PROT_PACKET
= (1 << 0),
190 PRB_PROT_TCQ
= (1 << 1),
191 PRB_PROT_NCQ
= (1 << 2),
192 PRB_PROT_READ
= (1 << 3),
193 PRB_PROT_WRITE
= (1 << 4),
194 PRB_PROT_TRANSPARENT
= (1 << 5),
199 SGE_TRM
= (1 << 31), /* Last SGE in chain */
200 SGE_LNK
= (1 << 30), /* linked list
201 Points to SGT, not SGE */
202 SGE_DRD
= (1 << 29), /* discard data read (/dev/null)
203 data address ignored */
210 IRQ_STAT_4PORTS
= 0xf,
213 struct sil24_ata_block
{
214 struct sil24_prb prb
;
215 struct sil24_sge sge
[LIBATA_MAX_PRD
];
218 struct sil24_atapi_block
{
219 struct sil24_prb prb
;
221 struct sil24_sge sge
[LIBATA_MAX_PRD
- 1];
224 union sil24_cmd_block
{
225 struct sil24_ata_block ata
;
226 struct sil24_atapi_block atapi
;
232 * The preview driver always returned 0 for status. We emulate it
233 * here from the previous interrupt.
235 struct sil24_port_priv
{
236 union sil24_cmd_block
*cmd_block
; /* 32 cmd blocks */
237 dma_addr_t cmd_block_dma
; /* DMA base addr for them */
238 struct ata_taskfile tf
; /* Cached taskfile registers */
241 /* ap->host_set->private_data */
242 struct sil24_host_priv
{
243 void __iomem
*host_base
; /* global controller control (128 bytes @BAR0) */
244 void __iomem
*port_base
; /* port registers (4 * 8192 bytes @BAR2) */
247 static void sil24_dev_config(struct ata_port
*ap
, struct ata_device
*dev
);
248 static u8
sil24_check_status(struct ata_port
*ap
);
249 static u32
sil24_scr_read(struct ata_port
*ap
, unsigned sc_reg
);
250 static void sil24_scr_write(struct ata_port
*ap
, unsigned sc_reg
, u32 val
);
251 static void sil24_tf_read(struct ata_port
*ap
, struct ata_taskfile
*tf
);
252 static void sil24_phy_reset(struct ata_port
*ap
);
253 static void sil24_qc_prep(struct ata_queued_cmd
*qc
);
254 static int sil24_qc_issue(struct ata_queued_cmd
*qc
);
255 static void sil24_irq_clear(struct ata_port
*ap
);
256 static void sil24_eng_timeout(struct ata_port
*ap
);
257 static irqreturn_t
sil24_interrupt(int irq
, void *dev_instance
, struct pt_regs
*regs
);
258 static int sil24_port_start(struct ata_port
*ap
);
259 static void sil24_port_stop(struct ata_port
*ap
);
260 static void sil24_host_stop(struct ata_host_set
*host_set
);
261 static int sil24_init_one(struct pci_dev
*pdev
, const struct pci_device_id
*ent
);
263 static const struct pci_device_id sil24_pci_tbl
[] = {
264 { 0x1095, 0x3124, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, BID_SIL3124
},
265 { 0x1095, 0x3132, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, BID_SIL3132
},
266 { 0x1095, 0x3131, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, BID_SIL3131
},
267 { 0x1095, 0x3531, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, BID_SIL3131
},
268 { } /* terminate list */
271 static struct pci_driver sil24_pci_driver
= {
273 .id_table
= sil24_pci_tbl
,
274 .probe
= sil24_init_one
,
275 .remove
= ata_pci_remove_one
, /* safe? */
278 static struct scsi_host_template sil24_sht
= {
279 .module
= THIS_MODULE
,
281 .ioctl
= ata_scsi_ioctl
,
282 .queuecommand
= ata_scsi_queuecmd
,
283 .eh_strategy_handler
= ata_scsi_error
,
284 .can_queue
= ATA_DEF_QUEUE
,
285 .this_id
= ATA_SHT_THIS_ID
,
286 .sg_tablesize
= LIBATA_MAX_PRD
,
287 .max_sectors
= ATA_MAX_SECTORS
,
288 .cmd_per_lun
= ATA_SHT_CMD_PER_LUN
,
289 .emulated
= ATA_SHT_EMULATED
,
290 .use_clustering
= ATA_SHT_USE_CLUSTERING
,
291 .proc_name
= DRV_NAME
,
292 .dma_boundary
= ATA_DMA_BOUNDARY
,
293 .slave_configure
= ata_scsi_slave_config
,
294 .bios_param
= ata_std_bios_param
,
297 static const struct ata_port_operations sil24_ops
= {
298 .port_disable
= ata_port_disable
,
300 .dev_config
= sil24_dev_config
,
302 .check_status
= sil24_check_status
,
303 .check_altstatus
= sil24_check_status
,
304 .dev_select
= ata_noop_dev_select
,
306 .tf_read
= sil24_tf_read
,
308 .phy_reset
= sil24_phy_reset
,
310 .qc_prep
= sil24_qc_prep
,
311 .qc_issue
= sil24_qc_issue
,
313 .eng_timeout
= sil24_eng_timeout
,
315 .irq_handler
= sil24_interrupt
,
316 .irq_clear
= sil24_irq_clear
,
318 .scr_read
= sil24_scr_read
,
319 .scr_write
= sil24_scr_write
,
321 .port_start
= sil24_port_start
,
322 .port_stop
= sil24_port_stop
,
323 .host_stop
= sil24_host_stop
,
327 * Use bits 30-31 of host_flags to encode available port numbers.
328 * Current maxium is 4.
330 #define SIL24_NPORTS2FLAG(nports) ((((unsigned)(nports) - 1) & 0x3) << 30)
331 #define SIL24_FLAG2NPORTS(flag) ((((flag) >> 30) & 0x3) + 1)
333 static struct ata_port_info sil24_port_info
[] = {
337 .host_flags
= ATA_FLAG_SATA
| ATA_FLAG_NO_LEGACY
|
338 ATA_FLAG_SRST
| ATA_FLAG_MMIO
|
339 ATA_FLAG_PIO_DMA
| SIL24_NPORTS2FLAG(4),
340 .pio_mask
= 0x1f, /* pio0-4 */
341 .mwdma_mask
= 0x07, /* mwdma0-2 */
342 .udma_mask
= 0x3f, /* udma0-5 */
343 .port_ops
= &sil24_ops
,
348 .host_flags
= ATA_FLAG_SATA
| ATA_FLAG_NO_LEGACY
|
349 ATA_FLAG_SRST
| ATA_FLAG_MMIO
|
350 ATA_FLAG_PIO_DMA
| SIL24_NPORTS2FLAG(2),
351 .pio_mask
= 0x1f, /* pio0-4 */
352 .mwdma_mask
= 0x07, /* mwdma0-2 */
353 .udma_mask
= 0x3f, /* udma0-5 */
354 .port_ops
= &sil24_ops
,
356 /* sil_3131/sil_3531 */
359 .host_flags
= ATA_FLAG_SATA
| ATA_FLAG_NO_LEGACY
|
360 ATA_FLAG_SRST
| ATA_FLAG_MMIO
|
361 ATA_FLAG_PIO_DMA
| SIL24_NPORTS2FLAG(1),
362 .pio_mask
= 0x1f, /* pio0-4 */
363 .mwdma_mask
= 0x07, /* mwdma0-2 */
364 .udma_mask
= 0x3f, /* udma0-5 */
365 .port_ops
= &sil24_ops
,
369 static void sil24_dev_config(struct ata_port
*ap
, struct ata_device
*dev
)
371 void __iomem
*port
= (void __iomem
*)ap
->ioaddr
.cmd_addr
;
373 if (ap
->cdb_len
== 16)
374 writel(PORT_CS_CDB16
, port
+ PORT_CTRL_STAT
);
376 writel(PORT_CS_CDB16
, port
+ PORT_CTRL_CLR
);
379 static inline void sil24_update_tf(struct ata_port
*ap
)
381 struct sil24_port_priv
*pp
= ap
->private_data
;
382 void __iomem
*port
= (void __iomem
*)ap
->ioaddr
.cmd_addr
;
383 struct sil24_prb __iomem
*prb
= port
;
386 memcpy_fromio(fis
, prb
->fis
, 6 * 4);
387 ata_tf_from_fis(fis
, &pp
->tf
);
390 static u8
sil24_check_status(struct ata_port
*ap
)
392 struct sil24_port_priv
*pp
= ap
->private_data
;
393 return pp
->tf
.command
;
396 static int sil24_scr_map
[] = {
403 static u32
sil24_scr_read(struct ata_port
*ap
, unsigned sc_reg
)
405 void __iomem
*scr_addr
= (void __iomem
*)ap
->ioaddr
.scr_addr
;
406 if (sc_reg
< ARRAY_SIZE(sil24_scr_map
)) {
408 addr
= scr_addr
+ sil24_scr_map
[sc_reg
] * 4;
409 return readl(scr_addr
+ sil24_scr_map
[sc_reg
] * 4);
414 static void sil24_scr_write(struct ata_port
*ap
, unsigned sc_reg
, u32 val
)
416 void __iomem
*scr_addr
= (void __iomem
*)ap
->ioaddr
.scr_addr
;
417 if (sc_reg
< ARRAY_SIZE(sil24_scr_map
)) {
419 addr
= scr_addr
+ sil24_scr_map
[sc_reg
] * 4;
420 writel(val
, scr_addr
+ sil24_scr_map
[sc_reg
] * 4);
424 static void sil24_tf_read(struct ata_port
*ap
, struct ata_taskfile
*tf
)
426 struct sil24_port_priv
*pp
= ap
->private_data
;
430 static int sil24_issue_SRST(struct ata_port
*ap
)
432 void __iomem
*port
= (void __iomem
*)ap
->ioaddr
.cmd_addr
;
433 struct sil24_port_priv
*pp
= ap
->private_data
;
434 struct sil24_prb
*prb
= &pp
->cmd_block
[0].ata
.prb
;
435 dma_addr_t paddr
= pp
->cmd_block_dma
;
436 u32 irq_enable
, irq_stat
;
439 /* temporarily turn off IRQs during SRST */
440 irq_enable
= readl(port
+ PORT_IRQ_ENABLE_SET
);
441 writel(irq_enable
, port
+ PORT_IRQ_ENABLE_CLR
);
444 * XXX: Not sure whether the following sleep is needed or not.
445 * The original driver had it. So....
449 prb
->ctrl
= PRB_CTRL_SRST
;
450 prb
->fis
[1] = 0; /* no PM yet */
452 writel((u32
)paddr
, port
+ PORT_CMD_ACTIVATE
);
454 for (cnt
= 0; cnt
< 100; cnt
++) {
455 irq_stat
= readl(port
+ PORT_IRQ_STAT
);
456 writel(irq_stat
, port
+ PORT_IRQ_STAT
); /* clear irq */
458 irq_stat
>>= PORT_IRQ_RAW_SHIFT
;
459 if (irq_stat
& (PORT_IRQ_COMPLETE
| PORT_IRQ_ERROR
))
466 writel(irq_enable
, port
+ PORT_IRQ_ENABLE_SET
);
468 if (!(irq_stat
& PORT_IRQ_COMPLETE
))
476 static void sil24_phy_reset(struct ata_port
*ap
)
478 struct sil24_port_priv
*pp
= ap
->private_data
;
480 __sata_phy_reset(ap
);
481 if (ap
->flags
& ATA_FLAG_PORT_DISABLED
)
484 if (sil24_issue_SRST(ap
) < 0) {
485 printk(KERN_ERR DRV_NAME
486 " ata%u: SRST failed, disabling port\n", ap
->id
);
487 ap
->ops
->port_disable(ap
);
491 ap
->device
->class = ata_dev_classify(&pp
->tf
);
494 static inline void sil24_fill_sg(struct ata_queued_cmd
*qc
,
495 struct sil24_sge
*sge
)
497 struct scatterlist
*sg
;
498 unsigned int idx
= 0;
500 ata_for_each_sg(sg
, qc
) {
501 sge
->addr
= cpu_to_le64(sg_dma_address(sg
));
502 sge
->cnt
= cpu_to_le32(sg_dma_len(sg
));
503 if (ata_sg_is_last(sg
, qc
))
504 sge
->flags
= cpu_to_le32(SGE_TRM
);
513 static void sil24_qc_prep(struct ata_queued_cmd
*qc
)
515 struct ata_port
*ap
= qc
->ap
;
516 struct sil24_port_priv
*pp
= ap
->private_data
;
517 union sil24_cmd_block
*cb
= pp
->cmd_block
+ qc
->tag
;
518 struct sil24_prb
*prb
;
519 struct sil24_sge
*sge
;
521 switch (qc
->tf
.protocol
) {
524 case ATA_PROT_NODATA
:
531 case ATA_PROT_ATAPI_DMA
:
532 case ATA_PROT_ATAPI_NODATA
:
533 prb
= &cb
->atapi
.prb
;
535 memset(cb
->atapi
.cdb
, 0, 32);
536 memcpy(cb
->atapi
.cdb
, qc
->cdb
, ap
->cdb_len
);
538 if (qc
->tf
.protocol
!= ATA_PROT_ATAPI_NODATA
) {
539 if (qc
->tf
.flags
& ATA_TFLAG_WRITE
)
540 prb
->ctrl
= PRB_CTRL_PACKET_WRITE
;
542 prb
->ctrl
= PRB_CTRL_PACKET_READ
;
549 prb
= NULL
; /* shut up, gcc */
554 ata_tf_to_fis(&qc
->tf
, prb
->fis
, 0);
556 if (qc
->flags
& ATA_QCFLAG_DMAMAP
)
557 sil24_fill_sg(qc
, sge
);
560 static int sil24_qc_issue(struct ata_queued_cmd
*qc
)
562 struct ata_port
*ap
= qc
->ap
;
563 void __iomem
*port
= (void __iomem
*)ap
->ioaddr
.cmd_addr
;
564 struct sil24_port_priv
*pp
= ap
->private_data
;
565 dma_addr_t paddr
= pp
->cmd_block_dma
+ qc
->tag
* sizeof(*pp
->cmd_block
);
567 writel((u32
)paddr
, port
+ PORT_CMD_ACTIVATE
);
571 static void sil24_irq_clear(struct ata_port
*ap
)
576 static int __sil24_restart_controller(void __iomem
*port
)
581 writel(PORT_CS_INIT
, port
+ PORT_CTRL_STAT
);
584 for (cnt
= 0; cnt
< 10000; cnt
++) {
585 tmp
= readl(port
+ PORT_CTRL_STAT
);
586 if (tmp
& PORT_CS_RDY
)
594 static void sil24_restart_controller(struct ata_port
*ap
)
596 if (__sil24_restart_controller((void __iomem
*)ap
->ioaddr
.cmd_addr
))
597 printk(KERN_ERR DRV_NAME
598 " ata%u: failed to restart controller\n", ap
->id
);
601 static int __sil24_reset_controller(void __iomem
*port
)
606 /* Reset controller state. Is this correct? */
607 writel(PORT_CS_DEV_RST
, port
+ PORT_CTRL_STAT
);
608 readl(port
+ PORT_CTRL_STAT
); /* sync */
611 for (cnt
= 0; cnt
< 1000; cnt
++) {
613 tmp
= readl(port
+ PORT_CTRL_STAT
);
614 if (!(tmp
& PORT_CS_DEV_RST
))
618 if (tmp
& PORT_CS_DEV_RST
)
621 if (tmp
& PORT_CS_RDY
)
624 return __sil24_restart_controller(port
);
627 static void sil24_reset_controller(struct ata_port
*ap
)
629 printk(KERN_NOTICE DRV_NAME
630 " ata%u: resetting controller...\n", ap
->id
);
631 if (__sil24_reset_controller((void __iomem
*)ap
->ioaddr
.cmd_addr
))
632 printk(KERN_ERR DRV_NAME
633 " ata%u: failed to reset controller\n", ap
->id
);
636 static void sil24_eng_timeout(struct ata_port
*ap
)
638 struct ata_queued_cmd
*qc
;
640 qc
= ata_qc_from_tag(ap
, ap
->active_tag
);
642 printk(KERN_ERR
"ata%u: BUG: timeout without command\n",
648 * hack alert! We cannot use the supplied completion
649 * function from inside the ->eh_strategy_handler() thread.
650 * libata is the only user of ->eh_strategy_handler() in
651 * any kernel, so the default scsi_done() assumes it is
652 * not being called from the SCSI EH.
654 printk(KERN_ERR
"ata%u: command timeout\n", ap
->id
);
655 qc
->scsidone
= scsi_finish_command
;
656 qc
->err_mask
|= AC_ERR_OTHER
;
659 sil24_reset_controller(ap
);
662 static void sil24_error_intr(struct ata_port
*ap
, u32 slot_stat
)
664 struct ata_queued_cmd
*qc
= ata_qc_from_tag(ap
, ap
->active_tag
);
665 struct sil24_port_priv
*pp
= ap
->private_data
;
666 void __iomem
*port
= (void __iomem
*)ap
->ioaddr
.cmd_addr
;
667 u32 irq_stat
, cmd_err
, sstatus
, serror
;
668 unsigned int err_mask
;
670 irq_stat
= readl(port
+ PORT_IRQ_STAT
);
671 writel(irq_stat
, port
+ PORT_IRQ_STAT
); /* clear irq */
673 if (!(irq_stat
& PORT_IRQ_ERROR
)) {
674 /* ignore non-completion, non-error irqs for now */
675 printk(KERN_WARNING DRV_NAME
676 "ata%u: non-error exception irq (irq_stat %x)\n",
681 cmd_err
= readl(port
+ PORT_CMD_ERR
);
682 sstatus
= readl(port
+ PORT_SSTATUS
);
683 serror
= readl(port
+ PORT_SERROR
);
685 writel(serror
, port
+ PORT_SERROR
);
688 * Don't log ATAPI device errors. They're supposed to happen
689 * and any serious errors will be logged using sense data by
692 if (ap
->device
[0].class != ATA_DEV_ATAPI
|| cmd_err
> PORT_CERR_SDB
)
693 printk("ata%u: error interrupt on port%d\n"
694 " stat=0x%x irq=0x%x cmd_err=%d sstatus=0x%x serror=0x%x\n",
695 ap
->id
, ap
->port_no
, slot_stat
, irq_stat
, cmd_err
, sstatus
, serror
);
697 if (cmd_err
== PORT_CERR_DEV
|| cmd_err
== PORT_CERR_SDB
) {
699 * Device is reporting error, tf registers are valid.
702 err_mask
= ac_err_mask(pp
->tf
.command
);
703 sil24_restart_controller(ap
);
706 * Other errors. libata currently doesn't have any
707 * mechanism to report these errors. Just turn on
710 err_mask
= AC_ERR_OTHER
;
711 sil24_reset_controller(ap
);
715 qc
->err_mask
|= err_mask
;
720 static inline void sil24_host_intr(struct ata_port
*ap
)
722 struct ata_queued_cmd
*qc
= ata_qc_from_tag(ap
, ap
->active_tag
);
723 void __iomem
*port
= (void __iomem
*)ap
->ioaddr
.cmd_addr
;
726 slot_stat
= readl(port
+ PORT_SLOT_STAT
);
727 if (!(slot_stat
& HOST_SSTAT_ATTN
)) {
728 struct sil24_port_priv
*pp
= ap
->private_data
;
730 * !HOST_SSAT_ATTN guarantees successful completion,
731 * so reading back tf registers is unnecessary for
732 * most commands. TODO: read tf registers for
733 * commands which require these values on successful
734 * completion (EXECUTE DEVICE DIAGNOSTIC, CHECK POWER,
735 * DEVICE RESET and READ PORT MULTIPLIER (any more?).
740 qc
->err_mask
|= ac_err_mask(pp
->tf
.command
);
744 sil24_error_intr(ap
, slot_stat
);
747 static irqreturn_t
sil24_interrupt(int irq
, void *dev_instance
, struct pt_regs
*regs
)
749 struct ata_host_set
*host_set
= dev_instance
;
750 struct sil24_host_priv
*hpriv
= host_set
->private_data
;
751 unsigned handled
= 0;
755 status
= readl(hpriv
->host_base
+ HOST_IRQ_STAT
);
757 if (status
== 0xffffffff) {
758 printk(KERN_ERR DRV_NAME
": IRQ status == 0xffffffff, "
759 "PCI fault or device removal?\n");
763 if (!(status
& IRQ_STAT_4PORTS
))
766 spin_lock(&host_set
->lock
);
768 for (i
= 0; i
< host_set
->n_ports
; i
++)
769 if (status
& (1 << i
)) {
770 struct ata_port
*ap
= host_set
->ports
[i
];
771 if (ap
&& !(ap
->flags
& ATA_FLAG_PORT_DISABLED
)) {
772 sil24_host_intr(host_set
->ports
[i
]);
775 printk(KERN_ERR DRV_NAME
776 ": interrupt from disabled port %d\n", i
);
779 spin_unlock(&host_set
->lock
);
781 return IRQ_RETVAL(handled
);
784 static inline void sil24_cblk_free(struct sil24_port_priv
*pp
, struct device
*dev
)
786 const size_t cb_size
= sizeof(*pp
->cmd_block
);
788 dma_free_coherent(dev
, cb_size
, pp
->cmd_block
, pp
->cmd_block_dma
);
791 static int sil24_port_start(struct ata_port
*ap
)
793 struct device
*dev
= ap
->host_set
->dev
;
794 struct sil24_port_priv
*pp
;
795 union sil24_cmd_block
*cb
;
796 size_t cb_size
= sizeof(*cb
);
800 pp
= kzalloc(sizeof(*pp
), GFP_KERNEL
);
804 pp
->tf
.command
= ATA_DRDY
;
806 cb
= dma_alloc_coherent(dev
, cb_size
, &cb_dma
, GFP_KERNEL
);
809 memset(cb
, 0, cb_size
);
811 rc
= ata_pad_alloc(ap
, dev
);
816 pp
->cmd_block_dma
= cb_dma
;
818 ap
->private_data
= pp
;
823 sil24_cblk_free(pp
, dev
);
830 static void sil24_port_stop(struct ata_port
*ap
)
832 struct device
*dev
= ap
->host_set
->dev
;
833 struct sil24_port_priv
*pp
= ap
->private_data
;
835 sil24_cblk_free(pp
, dev
);
836 ata_pad_free(ap
, dev
);
840 static void sil24_host_stop(struct ata_host_set
*host_set
)
842 struct sil24_host_priv
*hpriv
= host_set
->private_data
;
844 iounmap(hpriv
->host_base
);
845 iounmap(hpriv
->port_base
);
849 static int sil24_init_one(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
851 static int printed_version
= 0;
852 unsigned int board_id
= (unsigned int)ent
->driver_data
;
853 struct ata_port_info
*pinfo
= &sil24_port_info
[board_id
];
854 struct ata_probe_ent
*probe_ent
= NULL
;
855 struct sil24_host_priv
*hpriv
= NULL
;
856 void __iomem
*host_base
= NULL
;
857 void __iomem
*port_base
= NULL
;
860 if (!printed_version
++)
861 dev_printk(KERN_DEBUG
, &pdev
->dev
, "version " DRV_VERSION
"\n");
863 rc
= pci_enable_device(pdev
);
867 rc
= pci_request_regions(pdev
, DRV_NAME
);
872 /* ioremap mmio registers */
873 host_base
= ioremap(pci_resource_start(pdev
, 0),
874 pci_resource_len(pdev
, 0));
877 port_base
= ioremap(pci_resource_start(pdev
, 2),
878 pci_resource_len(pdev
, 2));
882 /* allocate & init probe_ent and hpriv */
883 probe_ent
= kmalloc(sizeof(*probe_ent
), GFP_KERNEL
);
887 hpriv
= kmalloc(sizeof(*hpriv
), GFP_KERNEL
);
891 memset(probe_ent
, 0, sizeof(*probe_ent
));
892 probe_ent
->dev
= pci_dev_to_dev(pdev
);
893 INIT_LIST_HEAD(&probe_ent
->node
);
895 probe_ent
->sht
= pinfo
->sht
;
896 probe_ent
->host_flags
= pinfo
->host_flags
;
897 probe_ent
->pio_mask
= pinfo
->pio_mask
;
898 probe_ent
->udma_mask
= pinfo
->udma_mask
;
899 probe_ent
->port_ops
= pinfo
->port_ops
;
900 probe_ent
->n_ports
= SIL24_FLAG2NPORTS(pinfo
->host_flags
);
902 probe_ent
->irq
= pdev
->irq
;
903 probe_ent
->irq_flags
= SA_SHIRQ
;
904 probe_ent
->mmio_base
= port_base
;
905 probe_ent
->private_data
= hpriv
;
907 memset(hpriv
, 0, sizeof(*hpriv
));
908 hpriv
->host_base
= host_base
;
909 hpriv
->port_base
= port_base
;
912 * Configure the device
915 * FIXME: This device is certainly 64-bit capable. We just
916 * don't know how to use it. After fixing 32bit activation in
917 * this function, enable 64bit masks here.
919 rc
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
);
921 dev_printk(KERN_ERR
, &pdev
->dev
,
922 "32-bit DMA enable failed\n");
925 rc
= pci_set_consistent_dma_mask(pdev
, DMA_32BIT_MASK
);
927 dev_printk(KERN_ERR
, &pdev
->dev
,
928 "32-bit consistent DMA enable failed\n");
933 writel(0, host_base
+ HOST_FLASH_CMD
);
935 /* Mask interrupts during initialization */
936 writel(0, host_base
+ HOST_CTRL
);
938 for (i
= 0; i
< probe_ent
->n_ports
; i
++) {
939 void __iomem
*port
= port_base
+ i
* PORT_REGS_SIZE
;
940 unsigned long portu
= (unsigned long)port
;
944 probe_ent
->port
[i
].cmd_addr
= portu
+ PORT_PRB
;
945 probe_ent
->port
[i
].scr_addr
= portu
+ PORT_SCONTROL
;
947 ata_std_ports(&probe_ent
->port
[i
]);
949 /* Initial PHY setting */
950 writel(0x20c, port
+ PORT_PHY_CFG
);
953 tmp
= readl(port
+ PORT_CTRL_STAT
);
954 if (tmp
& PORT_CS_PORT_RST
) {
955 writel(PORT_CS_PORT_RST
, port
+ PORT_CTRL_CLR
);
956 readl(port
+ PORT_CTRL_STAT
); /* sync */
957 for (cnt
= 0; cnt
< 10; cnt
++) {
959 tmp
= readl(port
+ PORT_CTRL_STAT
);
960 if (!(tmp
& PORT_CS_PORT_RST
))
963 if (tmp
& PORT_CS_PORT_RST
)
964 dev_printk(KERN_ERR
, &pdev
->dev
,
965 "failed to clear port RST\n");
968 /* Zero error counters. */
969 writel(0x8000, port
+ PORT_DECODE_ERR_THRESH
);
970 writel(0x8000, port
+ PORT_CRC_ERR_THRESH
);
971 writel(0x8000, port
+ PORT_HSHK_ERR_THRESH
);
972 writel(0x0000, port
+ PORT_DECODE_ERR_CNT
);
973 writel(0x0000, port
+ PORT_CRC_ERR_CNT
);
974 writel(0x0000, port
+ PORT_HSHK_ERR_CNT
);
976 /* FIXME: 32bit activation? */
977 writel(0, port
+ PORT_ACTIVATE_UPPER_ADDR
);
978 writel(PORT_CS_32BIT_ACTV
, port
+ PORT_CTRL_STAT
);
980 /* Configure interrupts */
981 writel(0xffff, port
+ PORT_IRQ_ENABLE_CLR
);
982 writel(PORT_IRQ_COMPLETE
| PORT_IRQ_ERROR
| PORT_IRQ_SDB_FIS
,
983 port
+ PORT_IRQ_ENABLE_SET
);
985 /* Clear interrupts */
986 writel(0x0fff0fff, port
+ PORT_IRQ_STAT
);
987 writel(PORT_CS_IRQ_WOC
, port
+ PORT_CTRL_CLR
);
989 /* Clear port multiplier enable and resume bits */
990 writel(PORT_CS_PM_EN
| PORT_CS_RESUME
, port
+ PORT_CTRL_CLR
);
993 if (__sil24_reset_controller(port
))
994 dev_printk(KERN_ERR
, &pdev
->dev
,
995 "failed to reset controller\n");
998 /* Turn on interrupts */
999 writel(IRQ_STAT_4PORTS
, host_base
+ HOST_CTRL
);
1001 pci_set_master(pdev
);
1003 /* FIXME: check ata_device_add return value */
1004 ata_device_add(probe_ent
);
1016 pci_release_regions(pdev
);
1018 pci_disable_device(pdev
);
1022 static int __init
sil24_init(void)
1024 return pci_module_init(&sil24_pci_driver
);
1027 static void __exit
sil24_exit(void)
1029 pci_unregister_driver(&sil24_pci_driver
);
1032 MODULE_AUTHOR("Tejun Heo");
1033 MODULE_DESCRIPTION("Silicon Image 3124/3132 SATA low-level driver");
1034 MODULE_LICENSE("GPL");
1035 MODULE_DEVICE_TABLE(pci
, sil24_pci_tbl
);
1037 module_init(sil24_init
);
1038 module_exit(sil24_exit
);