2 * Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com>
3 * Copyright (c) 1999-2000 Grant Erickson <grant@lcse.umn.edu>
5 * Module name: iSeries_setup.c
8 * Architecture- / platform-specific boot-time initialization code for
9 * the IBM iSeries LPAR. Adapted from original code by Grant Erickson and
10 * code by Gary Thomas, Cort Dougan <cort@fsmlabs.com>, and Dan Malek
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version
16 * 2 of the License, or (at your option) any later version.
21 #include <linux/config.h>
22 #include <linux/init.h>
23 #include <linux/threads.h>
24 #include <linux/smp.h>
25 #include <linux/param.h>
26 #include <linux/string.h>
27 #include <linux/initrd.h>
28 #include <linux/seq_file.h>
29 #include <linux/kdev_t.h>
30 #include <linux/major.h>
31 #include <linux/root_dev.h>
33 #include <asm/processor.h>
34 #include <asm/machdep.h>
37 #include <asm/pgtable.h>
38 #include <asm/mmu_context.h>
39 #include <asm/cputable.h>
40 #include <asm/sections.h>
41 #include <asm/iommu.h>
42 #include <asm/firmware.h>
45 #include "iSeries_setup.h"
48 #include <asm/cache.h>
49 #include <asm/sections.h>
50 #include <asm/abs_addr.h>
51 #include <asm/iSeries/HvCallHpt.h>
52 #include <asm/iSeries/HvLpConfig.h>
53 #include <asm/iSeries/HvCallEvent.h>
54 #include <asm/iSeries/HvCallSm.h>
55 #include <asm/iSeries/HvCallXm.h>
56 #include <asm/iSeries/ItLpQueue.h>
57 #include <asm/iSeries/IoHriMainStore.h>
58 #include <asm/iSeries/mf.h>
59 #include <asm/iSeries/HvLpEvent.h>
60 #include <asm/iSeries/iSeries_irq.h>
61 #include <asm/iSeries/IoHriProcessorVpd.h>
62 #include <asm/iSeries/ItVpdAreas.h>
63 #include <asm/iSeries/LparMap.h>
65 extern void hvlog(char *fmt
, ...);
68 #define DBG(fmt...) hvlog(fmt)
73 /* Function Prototypes */
74 extern void ppcdbg_initialize(void);
76 static void build_iSeries_Memory_Map(void);
77 static void setup_iSeries_cache_sizes(void);
78 static int iseries_shared_idle(void);
79 static int iseries_dedicated_idle(void);
81 extern void iSeries_pci_final_fixup(void);
83 static void iSeries_pci_final_fixup(void) { }
86 /* Global Variables */
87 static unsigned long procFreqHz
;
88 static unsigned long procFreqMhz
;
89 static unsigned long procFreqMhzHundreths
;
91 static unsigned long tbFreqHz
;
92 static unsigned long tbFreqMhz
;
93 static unsigned long tbFreqMhzHundreths
;
95 int piranha_simulator
;
97 extern int rd_size
; /* Defined in drivers/block/rd.c */
98 extern unsigned long klimit
;
99 extern unsigned long embedded_sysmap_start
;
100 extern unsigned long embedded_sysmap_end
;
102 extern unsigned long iSeries_recal_tb
;
103 extern unsigned long iSeries_recal_titan
;
105 static int mf_initialized
;
108 unsigned long absStart
;
109 unsigned long absEnd
;
110 unsigned long logicalStart
;
111 unsigned long logicalEnd
;
115 * Process the main store vpd to determine where the holes in memory are
116 * and return the number of physical blocks and fill in the array of
119 static unsigned long iSeries_process_Condor_mainstore_vpd(
120 struct MemoryBlock
*mb_array
, unsigned long max_entries
)
122 unsigned long holeFirstChunk
, holeSizeChunks
;
123 unsigned long numMemoryBlocks
= 1;
124 struct IoHriMainStoreSegment4
*msVpd
=
125 (struct IoHriMainStoreSegment4
*)xMsVpd
;
126 unsigned long holeStart
= msVpd
->nonInterleavedBlocksStartAdr
;
127 unsigned long holeEnd
= msVpd
->nonInterleavedBlocksEndAdr
;
128 unsigned long holeSize
= holeEnd
- holeStart
;
130 printk("Mainstore_VPD: Condor\n");
132 * Determine if absolute memory has any
133 * holes so that we can interpret the
134 * access map we get back from the hypervisor
137 mb_array
[0].logicalStart
= 0;
138 mb_array
[0].logicalEnd
= 0x100000000;
139 mb_array
[0].absStart
= 0;
140 mb_array
[0].absEnd
= 0x100000000;
144 holeStart
= holeStart
& 0x000fffffffffffff;
145 holeStart
= addr_to_chunk(holeStart
);
146 holeFirstChunk
= holeStart
;
147 holeSize
= addr_to_chunk(holeSize
);
148 holeSizeChunks
= holeSize
;
149 printk( "Main store hole: start chunk = %0lx, size = %0lx chunks\n",
150 holeFirstChunk
, holeSizeChunks
);
151 mb_array
[0].logicalEnd
= holeFirstChunk
;
152 mb_array
[0].absEnd
= holeFirstChunk
;
153 mb_array
[1].logicalStart
= holeFirstChunk
;
154 mb_array
[1].logicalEnd
= 0x100000000 - holeSizeChunks
;
155 mb_array
[1].absStart
= holeFirstChunk
+ holeSizeChunks
;
156 mb_array
[1].absEnd
= 0x100000000;
158 return numMemoryBlocks
;
161 #define MaxSegmentAreas 32
162 #define MaxSegmentAdrRangeBlocks 128
163 #define MaxAreaRangeBlocks 4
165 static unsigned long iSeries_process_Regatta_mainstore_vpd(
166 struct MemoryBlock
*mb_array
, unsigned long max_entries
)
168 struct IoHriMainStoreSegment5
*msVpdP
=
169 (struct IoHriMainStoreSegment5
*)xMsVpd
;
170 unsigned long numSegmentBlocks
= 0;
171 u32 existsBits
= msVpdP
->msAreaExists
;
172 unsigned long area_num
;
174 printk("Mainstore_VPD: Regatta\n");
176 for (area_num
= 0; area_num
< MaxSegmentAreas
; ++area_num
) {
177 unsigned long numAreaBlocks
;
178 struct IoHriMainStoreArea4
*currentArea
;
180 if (existsBits
& 0x80000000) {
181 unsigned long block_num
;
183 currentArea
= &msVpdP
->msAreaArray
[area_num
];
184 numAreaBlocks
= currentArea
->numAdrRangeBlocks
;
185 printk("ms_vpd: processing area %2ld blocks=%ld",
186 area_num
, numAreaBlocks
);
187 for (block_num
= 0; block_num
< numAreaBlocks
;
189 /* Process an address range block */
190 struct MemoryBlock tempBlock
;
194 (unsigned long)currentArea
->xAdrRangeBlock
[block_num
].blockStart
;
196 (unsigned long)currentArea
->xAdrRangeBlock
[block_num
].blockEnd
;
197 tempBlock
.logicalStart
= 0;
198 tempBlock
.logicalEnd
= 0;
199 printk("\n block %ld absStart=%016lx absEnd=%016lx",
200 block_num
, tempBlock
.absStart
,
203 for (i
= 0; i
< numSegmentBlocks
; ++i
) {
204 if (mb_array
[i
].absStart
==
208 if (i
== numSegmentBlocks
) {
209 if (numSegmentBlocks
== max_entries
)
210 panic("iSeries_process_mainstore_vpd: too many memory blocks");
211 mb_array
[numSegmentBlocks
] = tempBlock
;
214 printk(" (duplicate)");
220 /* Now sort the blocks found into ascending sequence */
221 if (numSegmentBlocks
> 1) {
224 for (m
= 0; m
< numSegmentBlocks
- 1; ++m
) {
225 for (n
= numSegmentBlocks
- 1; m
< n
; --n
) {
226 if (mb_array
[n
].absStart
<
227 mb_array
[n
-1].absStart
) {
228 struct MemoryBlock tempBlock
;
230 tempBlock
= mb_array
[n
];
231 mb_array
[n
] = mb_array
[n
-1];
232 mb_array
[n
-1] = tempBlock
;
238 * Assign "logical" addresses to each block. These
239 * addresses correspond to the hypervisor "bitmap" space.
240 * Convert all addresses into units of 256K chunks.
243 unsigned long i
, nextBitmapAddress
;
245 printk("ms_vpd: %ld sorted memory blocks\n", numSegmentBlocks
);
246 nextBitmapAddress
= 0;
247 for (i
= 0; i
< numSegmentBlocks
; ++i
) {
248 unsigned long length
= mb_array
[i
].absEnd
-
249 mb_array
[i
].absStart
;
251 mb_array
[i
].logicalStart
= nextBitmapAddress
;
252 mb_array
[i
].logicalEnd
= nextBitmapAddress
+ length
;
253 nextBitmapAddress
+= length
;
254 printk(" Bitmap range: %016lx - %016lx\n"
255 " Absolute range: %016lx - %016lx\n",
256 mb_array
[i
].logicalStart
,
257 mb_array
[i
].logicalEnd
,
258 mb_array
[i
].absStart
, mb_array
[i
].absEnd
);
259 mb_array
[i
].absStart
= addr_to_chunk(mb_array
[i
].absStart
&
261 mb_array
[i
].absEnd
= addr_to_chunk(mb_array
[i
].absEnd
&
263 mb_array
[i
].logicalStart
=
264 addr_to_chunk(mb_array
[i
].logicalStart
);
265 mb_array
[i
].logicalEnd
= addr_to_chunk(mb_array
[i
].logicalEnd
);
269 return numSegmentBlocks
;
272 static unsigned long iSeries_process_mainstore_vpd(struct MemoryBlock
*mb_array
,
273 unsigned long max_entries
)
276 unsigned long mem_blocks
= 0;
278 if (cpu_has_feature(CPU_FTR_SLB
))
279 mem_blocks
= iSeries_process_Regatta_mainstore_vpd(mb_array
,
282 mem_blocks
= iSeries_process_Condor_mainstore_vpd(mb_array
,
285 printk("Mainstore_VPD: numMemoryBlocks = %ld \n", mem_blocks
);
286 for (i
= 0; i
< mem_blocks
; ++i
) {
287 printk("Mainstore_VPD: block %3ld logical chunks %016lx - %016lx\n"
288 " abs chunks %016lx - %016lx\n",
289 i
, mb_array
[i
].logicalStart
, mb_array
[i
].logicalEnd
,
290 mb_array
[i
].absStart
, mb_array
[i
].absEnd
);
295 static void __init
iSeries_get_cmdline(void)
299 /* copy the command line parameter from the primary VSP */
300 HvCallEvent_dmaToSp(cmd_line
, 2 * 64* 1024, 256,
301 HvLpDma_Direction_RemoteToLocal
);
306 if (!*p
|| *p
== '\n')
313 static void __init
iSeries_init_early(void)
315 extern unsigned long memory_limit
;
317 DBG(" -> iSeries_init_early()\n");
319 ppc64_firmware_features
= FW_FEATURE_ISERIES
;
323 ppc64_interrupt_controller
= IC_ISERIES
;
325 #if defined(CONFIG_BLK_DEV_INITRD)
327 * If the init RAM disk has been configured and there is
328 * a non-zero starting address for it, set it up
331 initrd_start
= (unsigned long)__va(naca
.xRamDisk
);
332 initrd_end
= initrd_start
+ naca
.xRamDiskSize
* PAGE_SIZE
;
333 initrd_below_start_ok
= 1; // ramdisk in kernel space
334 ROOT_DEV
= Root_RAM0
;
335 if (((rd_size
* 1024) / PAGE_SIZE
) < naca
.xRamDiskSize
)
336 rd_size
= (naca
.xRamDiskSize
* PAGE_SIZE
) / 1024;
338 #endif /* CONFIG_BLK_DEV_INITRD */
340 /* ROOT_DEV = MKDEV(VIODASD_MAJOR, 1); */
343 iSeries_recal_tb
= get_tb();
344 iSeries_recal_titan
= HvCallXm_loadTod();
347 * Cache sizes must be initialized before hpte_init_iSeries is called
348 * as the later need them for flush_icache_range()
350 setup_iSeries_cache_sizes();
353 * Initialize the hash table management pointers
358 * Initialize the DMA/TCE management
360 iommu_init_early_iSeries();
362 iSeries_get_cmdline();
364 /* Save unparsed command line copy for /proc/cmdline */
365 strlcpy(saved_command_line
, cmd_line
, COMMAND_LINE_SIZE
);
367 /* Parse early parameters, in particular mem=x */
371 if (memory_limit
< systemcfg
->physicalMemorySize
)
372 systemcfg
->physicalMemorySize
= memory_limit
;
374 printk("Ignoring mem=%lu >= ram_top.\n", memory_limit
);
380 lmb_add(0, systemcfg
->physicalMemorySize
);
382 lmb_reserve(0, __pa(klimit
));
384 /* Initialize machine-dependency vectors */
388 if (itLpNaca
.xPirEnvironMode
== 0)
389 piranha_simulator
= 1;
391 /* Associate Lp Event Queue 0 with processor 0 */
392 HvCallEvent_setLpEventQueueInterruptProc(0, 0);
398 /* If we were passed an initrd, set the ROOT_DEV properly if the values
399 * look sensible. If not, clear initrd reference.
401 #ifdef CONFIG_BLK_DEV_INITRD
402 if (initrd_start
>= KERNELBASE
&& initrd_end
>= KERNELBASE
&&
403 initrd_end
> initrd_start
)
404 ROOT_DEV
= Root_RAM0
;
406 initrd_start
= initrd_end
= 0;
407 #endif /* CONFIG_BLK_DEV_INITRD */
409 DBG(" <- iSeries_init_early()\n");
412 struct mschunks_map mschunks_map
= {
413 /* XXX We don't use these, but Piranha might need them. */
414 .chunk_size
= MSCHUNKS_CHUNK_SIZE
,
415 .chunk_shift
= MSCHUNKS_CHUNK_SHIFT
,
416 .chunk_mask
= MSCHUNKS_OFFSET_MASK
,
418 EXPORT_SYMBOL(mschunks_map
);
420 void mschunks_alloc(unsigned long num_chunks
)
422 klimit
= _ALIGN(klimit
, sizeof(u32
));
423 mschunks_map
.mapping
= (u32
*)klimit
;
424 klimit
+= num_chunks
* sizeof(u32
);
425 mschunks_map
.num_chunks
= num_chunks
;
429 * The iSeries may have very large memories ( > 128 GB ) and a partition
430 * may get memory in "chunks" that may be anywhere in the 2**52 real
431 * address space. The chunks are 256K in size. To map this to the
432 * memory model Linux expects, the AS/400 specific code builds a
433 * translation table to translate what Linux thinks are "physical"
434 * addresses to the actual real addresses. This allows us to make
435 * it appear to Linux that we have contiguous memory starting at
436 * physical address zero while in fact this could be far from the truth.
437 * To avoid confusion, I'll let the words physical and/or real address
438 * apply to the Linux addresses while I'll use "absolute address" to
439 * refer to the actual hardware real address.
441 * build_iSeries_Memory_Map gets information from the Hypervisor and
442 * looks at the Main Store VPD to determine the absolute addresses
443 * of the memory that has been assigned to our partition and builds
444 * a table used to translate Linux's physical addresses to these
445 * absolute addresses. Absolute addresses are needed when
446 * communicating with the hypervisor (e.g. to build HPT entries)
449 static void __init
build_iSeries_Memory_Map(void)
451 u32 loadAreaFirstChunk
, loadAreaLastChunk
, loadAreaSize
;
453 u32 hptFirstChunk
, hptLastChunk
, hptSizeChunks
, hptSizePages
;
455 u32 totalChunks
,moreChunks
;
456 u32 currChunk
, thisChunk
, absChunk
;
460 struct MemoryBlock mb
[32];
461 unsigned long numMemoryBlocks
, curBlock
;
463 /* Chunk size on iSeries is 256K bytes */
464 totalChunks
= (u32
)HvLpConfig_getMsChunks();
465 mschunks_alloc(totalChunks
);
468 * Get absolute address of our load area
469 * and map it to physical address 0
470 * This guarantees that the loadarea ends up at physical 0
471 * otherwise, it might not be returned by PLIC as the first
475 loadAreaFirstChunk
= (u32
)addr_to_chunk(itLpNaca
.xLoadAreaAddr
);
476 loadAreaSize
= itLpNaca
.xLoadAreaChunks
;
479 * Only add the pages already mapped here.
480 * Otherwise we might add the hpt pages
481 * The rest of the pages of the load area
482 * aren't in the HPT yet and can still
483 * be assigned an arbitrary physical address
485 if ((loadAreaSize
* 64) > HvPagesToMap
)
486 loadAreaSize
= HvPagesToMap
/ 64;
488 loadAreaLastChunk
= loadAreaFirstChunk
+ loadAreaSize
- 1;
491 * TODO Do we need to do something if the HPT is in the 64MB load area?
492 * This would be required if the itLpNaca.xLoadAreaChunks includes
496 printk("Mapping load area - physical addr = 0000000000000000\n"
497 " absolute addr = %016lx\n",
498 chunk_to_addr(loadAreaFirstChunk
));
499 printk("Load area size %dK\n", loadAreaSize
* 256);
501 for (nextPhysChunk
= 0; nextPhysChunk
< loadAreaSize
; ++nextPhysChunk
)
502 mschunks_map
.mapping
[nextPhysChunk
] =
503 loadAreaFirstChunk
+ nextPhysChunk
;
506 * Get absolute address of our HPT and remember it so
507 * we won't map it to any physical address
509 hptFirstChunk
= (u32
)addr_to_chunk(HvCallHpt_getHptAddress());
510 hptSizePages
= (u32
)HvCallHpt_getHptPages();
511 hptSizeChunks
= hptSizePages
>> (MSCHUNKS_CHUNK_SHIFT
- PAGE_SHIFT
);
512 hptLastChunk
= hptFirstChunk
+ hptSizeChunks
- 1;
514 printk("HPT absolute addr = %016lx, size = %dK\n",
515 chunk_to_addr(hptFirstChunk
), hptSizeChunks
* 256);
517 /* Fill in the hashed page table hash mask */
518 num_ptegs
= hptSizePages
*
519 (PAGE_SIZE
/ (sizeof(hpte_t
) * HPTES_PER_GROUP
));
520 htab_hash_mask
= num_ptegs
- 1;
523 * The actual hashed page table is in the hypervisor,
524 * we have no direct access
529 * Determine if absolute memory has any
530 * holes so that we can interpret the
531 * access map we get back from the hypervisor
534 numMemoryBlocks
= iSeries_process_mainstore_vpd(mb
, 32);
537 * Process the main store access map from the hypervisor
538 * to build up our physical -> absolute translation table
543 moreChunks
= totalChunks
;
546 map
= HvCallSm_get64BitsOfAccessMap(itLpNaca
.xLpIndex
,
548 thisChunk
= currChunk
;
550 chunkBit
= map
>> 63;
554 while (thisChunk
>= mb
[curBlock
].logicalEnd
) {
556 if (curBlock
>= numMemoryBlocks
)
557 panic("out of memory blocks");
559 if (thisChunk
< mb
[curBlock
].logicalStart
)
560 panic("memory block error");
562 absChunk
= mb
[curBlock
].absStart
+
563 (thisChunk
- mb
[curBlock
].logicalStart
);
564 if (((absChunk
< hptFirstChunk
) ||
565 (absChunk
> hptLastChunk
)) &&
566 ((absChunk
< loadAreaFirstChunk
) ||
567 (absChunk
> loadAreaLastChunk
))) {
568 mschunks_map
.mapping
[nextPhysChunk
] =
580 * main store size (in chunks) is
581 * totalChunks - hptSizeChunks
582 * which should be equal to
585 systemcfg
->physicalMemorySize
= chunk_to_addr(nextPhysChunk
);
589 * Set up the variables that describe the cache line sizes
592 static void __init
setup_iSeries_cache_sizes(void)
595 unsigned int procIx
= get_paca()->lppaca
.dyn_hv_phys_proc_index
;
597 systemcfg
->icache_size
=
598 ppc64_caches
.isize
= xIoHriProcessorVpd
[procIx
].xInstCacheSize
* 1024;
599 systemcfg
->icache_line_size
=
600 ppc64_caches
.iline_size
=
601 xIoHriProcessorVpd
[procIx
].xInstCacheOperandSize
;
602 systemcfg
->dcache_size
=
604 xIoHriProcessorVpd
[procIx
].xDataL1CacheSizeKB
* 1024;
605 systemcfg
->dcache_line_size
=
606 ppc64_caches
.dline_size
=
607 xIoHriProcessorVpd
[procIx
].xDataCacheOperandSize
;
608 ppc64_caches
.ilines_per_page
= PAGE_SIZE
/ ppc64_caches
.iline_size
;
609 ppc64_caches
.dlines_per_page
= PAGE_SIZE
/ ppc64_caches
.dline_size
;
611 i
= ppc64_caches
.iline_size
;
613 while ((i
= (i
/ 2)))
615 ppc64_caches
.log_iline_size
= n
;
617 i
= ppc64_caches
.dline_size
;
619 while ((i
= (i
/ 2)))
621 ppc64_caches
.log_dline_size
= n
;
623 printk("D-cache line size = %d\n",
624 (unsigned int)ppc64_caches
.dline_size
);
625 printk("I-cache line size = %d\n",
626 (unsigned int)ppc64_caches
.iline_size
);
632 static void __init
iSeries_setup_arch(void)
634 unsigned procIx
= get_paca()->lppaca
.dyn_hv_phys_proc_index
;
636 if (get_paca()->lppaca
.shared_proc
) {
637 ppc_md
.idle_loop
= iseries_shared_idle
;
638 printk(KERN_INFO
"Using shared processor idle loop\n");
640 ppc_md
.idle_loop
= iseries_dedicated_idle
;
641 printk(KERN_INFO
"Using dedicated idle loop\n");
644 /* Add an eye catcher and the systemcfg layout version number */
645 strcpy(systemcfg
->eye_catcher
, "SYSTEMCFG:PPC64");
646 systemcfg
->version
.major
= SYSTEMCFG_MAJOR
;
647 systemcfg
->version
.minor
= SYSTEMCFG_MINOR
;
649 /* Setup the Lp Event Queue */
650 setup_hvlpevent_queue();
652 /* Compute processor frequency */
653 procFreqHz
= ((1UL << 34) * 1000000) /
654 xIoHriProcessorVpd
[procIx
].xProcFreq
;
655 procFreqMhz
= procFreqHz
/ 1000000;
656 procFreqMhzHundreths
= (procFreqHz
/ 10000) - (procFreqMhz
* 100);
657 ppc_proc_freq
= procFreqHz
;
659 /* Compute time base frequency */
660 tbFreqHz
= ((1UL << 32) * 1000000) /
661 xIoHriProcessorVpd
[procIx
].xTimeBaseFreq
;
662 tbFreqMhz
= tbFreqHz
/ 1000000;
663 tbFreqMhzHundreths
= (tbFreqHz
/ 10000) - (tbFreqMhz
* 100);
664 ppc_tb_freq
= tbFreqHz
;
666 printk("Max logical processors = %d\n",
667 itVpdAreas
.xSlicMaxLogicalProcs
);
668 printk("Max physical processors = %d\n",
669 itVpdAreas
.xSlicMaxPhysicalProcs
);
670 printk("Processor frequency = %lu.%02lu\n", procFreqMhz
,
671 procFreqMhzHundreths
);
672 printk("Time base frequency = %lu.%02lu\n", tbFreqMhz
,
674 systemcfg
->processor
= xIoHriProcessorVpd
[procIx
].xPVR
;
675 printk("Processor version = %x\n", systemcfg
->processor
);
678 static void iSeries_get_cpuinfo(struct seq_file
*m
)
680 seq_printf(m
, "machine\t\t: 64-bit iSeries Logical Partition\n");
687 static int iSeries_get_irq(struct pt_regs
*regs
)
689 /* -2 means ignore this interrupt */
696 static void iSeries_restart(char *cmd
)
704 static void iSeries_power_off(void)
712 static void iSeries_halt(void)
718 * void __init iSeries_calibrate_decr()
721 * This routine retrieves the internal processor frequency from the VPD,
722 * and sets up the kernel timer decrementer based on that value.
725 static void __init
iSeries_calibrate_decr(void)
727 unsigned long cyclesPerUsec
;
728 struct div_result divres
;
730 /* Compute decrementer (and TB) frequency in cycles/sec */
731 cyclesPerUsec
= ppc_tb_freq
/ 1000000;
734 * Set the amount to refresh the decrementer by. This
735 * is the number of decrementer ticks it takes for
738 tb_ticks_per_jiffy
= ppc_tb_freq
/ HZ
;
741 /* TEST CODE FOR ADJTIME */
742 tb_ticks_per_jiffy
+= tb_ticks_per_jiffy
/ 5000;
743 /* END OF TEST CODE */
747 * tb_ticks_per_sec = freq; would give better accuracy
748 * but tb_ticks_per_sec = tb_ticks_per_jiffy*HZ; assures
749 * that jiffies (and xtime) will match the time returned
750 * by do_gettimeofday.
752 tb_ticks_per_sec
= tb_ticks_per_jiffy
* HZ
;
753 tb_ticks_per_usec
= cyclesPerUsec
;
754 tb_to_us
= mulhwu_scale_factor(ppc_tb_freq
, 1000000);
755 div128_by_32(1024 * 1024, 0, tb_ticks_per_sec
, &divres
);
756 tb_to_xs
= divres
.result_low
;
757 setup_default_decr();
760 static void __init
iSeries_progress(char * st
, unsigned short code
)
762 printk("Progress: [%04x] - %s\n", (unsigned)code
, st
);
763 if (!piranha_simulator
&& mf_initialized
) {
765 mf_display_progress(code
);
771 static void __init
iSeries_fixup_klimit(void)
774 * Change klimit to take into account any ram disk
775 * that may be included
778 klimit
= KERNELBASE
+ (u64
)naca
.xRamDisk
+
779 (naca
.xRamDiskSize
* PAGE_SIZE
);
782 * No ram disk was included - check and see if there
783 * was an embedded system map. Change klimit to take
784 * into account any embedded system map
786 if (embedded_sysmap_end
)
787 klimit
= KERNELBASE
+ ((embedded_sysmap_end
+ 4095) &
792 static int __init
iSeries_src_init(void)
794 /* clear the progress line */
795 ppc_md
.progress(" ", 0xffff);
799 late_initcall(iSeries_src_init
);
801 static inline void process_iSeries_events(void)
803 asm volatile ("li 0,0x5555; sc" : : : "r0", "r3");
806 static void yield_shared_processor(void)
810 HvCall_setEnabledInterrupts(HvCall_MaskIPI
|
816 /* Compute future tb value when yield should expire */
817 HvCall_yieldProcessor(HvCall_YieldTimed
, tb
+tb_ticks_per_jiffy
);
820 * The decrementer stops during the yield. Force a fake decrementer
821 * here and let the timer_interrupt code sort out the actual time.
823 get_paca()->lppaca
.int_dword
.fields
.decr_int
= 1;
824 process_iSeries_events();
827 static int iseries_shared_idle(void)
830 while (!need_resched() && !hvlpevent_is_pending()) {
832 ppc64_runlatch_off();
834 /* Recheck with irqs off */
835 if (!need_resched() && !hvlpevent_is_pending())
836 yield_shared_processor();
844 if (hvlpevent_is_pending())
845 process_iSeries_events();
853 static int iseries_dedicated_idle(void)
858 oldval
= test_and_clear_thread_flag(TIF_NEED_RESCHED
);
861 set_thread_flag(TIF_POLLING_NRFLAG
);
863 while (!need_resched()) {
864 ppc64_runlatch_off();
867 if (hvlpevent_is_pending()) {
870 process_iSeries_events();
875 clear_thread_flag(TIF_POLLING_NRFLAG
);
888 void __init
iSeries_init_IRQ(void) { }
891 static int __init
iseries_probe(int platform
)
893 return PLATFORM_ISERIES_LPAR
== platform
;
896 struct machdep_calls __initdata iseries_md
= {
897 .setup_arch
= iSeries_setup_arch
,
898 .get_cpuinfo
= iSeries_get_cpuinfo
,
899 .init_IRQ
= iSeries_init_IRQ
,
900 .get_irq
= iSeries_get_irq
,
901 .init_early
= iSeries_init_early
,
902 .pcibios_fixup
= iSeries_pci_final_fixup
,
903 .restart
= iSeries_restart
,
904 .power_off
= iSeries_power_off
,
905 .halt
= iSeries_halt
,
906 .get_boot_time
= iSeries_get_boot_time
,
907 .set_rtc_time
= iSeries_set_rtc_time
,
908 .get_rtc_time
= iSeries_get_rtc_time
,
909 .calibrate_decr
= iSeries_calibrate_decr
,
910 .progress
= iSeries_progress
,
911 .probe
= iseries_probe
,
912 /* XXX Implement enable_pmcs for iSeries */
916 unsigned char data
[PAGE_SIZE
];
920 struct iseries_flat_dt
{
921 struct boot_param_header header
;
927 struct iseries_flat_dt iseries_dt
;
929 void dt_init(struct iseries_flat_dt
*dt
)
931 dt
->header
.off_mem_rsvmap
=
932 offsetof(struct iseries_flat_dt
, reserve_map
);
933 dt
->header
.off_dt_struct
= offsetof(struct iseries_flat_dt
, dt
);
934 dt
->header
.off_dt_strings
= offsetof(struct iseries_flat_dt
, strings
);
935 dt
->header
.totalsize
= sizeof(struct iseries_flat_dt
);
936 dt
->header
.dt_strings_size
= sizeof(struct blob
);
938 /* There is no notion of hardware cpu id on iSeries */
939 dt
->header
.boot_cpuid_phys
= smp_processor_id();
941 dt
->dt
.next
= (unsigned long)&dt
->dt
.data
;
942 dt
->strings
.next
= (unsigned long)&dt
->strings
.data
;
944 dt
->header
.magic
= OF_DT_HEADER
;
945 dt
->header
.version
= 0x10;
946 dt
->header
.last_comp_version
= 0x10;
948 dt
->reserve_map
[0] = 0;
949 dt
->reserve_map
[1] = 0;
952 void dt_check_blob(struct blob
*b
)
954 if (b
->next
>= (unsigned long)&b
->next
) {
955 DBG("Ran out of space in flat device tree blob!\n");
960 void dt_push_u32(struct iseries_flat_dt
*dt
, u32 value
)
962 *((u32
*)dt
->dt
.next
) = value
;
963 dt
->dt
.next
+= sizeof(u32
);
965 dt_check_blob(&dt
->dt
);
968 void dt_push_u64(struct iseries_flat_dt
*dt
, u64 value
)
970 *((u64
*)dt
->dt
.next
) = value
;
971 dt
->dt
.next
+= sizeof(u64
);
973 dt_check_blob(&dt
->dt
);
976 unsigned long dt_push_bytes(struct blob
*blob
, char *data
, int len
)
978 unsigned long start
= blob
->next
- (unsigned long)blob
->data
;
980 memcpy((char *)blob
->next
, data
, len
);
981 blob
->next
= _ALIGN(blob
->next
+ len
, 4);
988 void dt_start_node(struct iseries_flat_dt
*dt
, char *name
)
990 dt_push_u32(dt
, OF_DT_BEGIN_NODE
);
991 dt_push_bytes(&dt
->dt
, name
, strlen(name
) + 1);
994 #define dt_end_node(dt) dt_push_u32(dt, OF_DT_END_NODE)
996 void dt_prop(struct iseries_flat_dt
*dt
, char *name
, char *data
, int len
)
998 unsigned long offset
;
1000 dt_push_u32(dt
, OF_DT_PROP
);
1002 /* Length of the data */
1003 dt_push_u32(dt
, len
);
1005 /* Put the property name in the string blob. */
1006 offset
= dt_push_bytes(&dt
->strings
, name
, strlen(name
) + 1);
1008 /* The offset of the properties name in the string blob. */
1009 dt_push_u32(dt
, (u32
)offset
);
1011 /* The actual data. */
1012 dt_push_bytes(&dt
->dt
, data
, len
);
1015 void dt_prop_str(struct iseries_flat_dt
*dt
, char *name
, char *data
)
1017 dt_prop(dt
, name
, data
, strlen(data
) + 1); /* + 1 for NULL */
1020 void dt_prop_u32(struct iseries_flat_dt
*dt
, char *name
, u32 data
)
1022 dt_prop(dt
, name
, (char *)&data
, sizeof(u32
));
1025 void dt_prop_u64(struct iseries_flat_dt
*dt
, char *name
, u64 data
)
1027 dt_prop(dt
, name
, (char *)&data
, sizeof(u64
));
1030 void dt_prop_u64_list(struct iseries_flat_dt
*dt
, char *name
, u64
*data
, int n
)
1032 dt_prop(dt
, name
, (char *)data
, sizeof(u64
) * n
);
1035 void dt_prop_empty(struct iseries_flat_dt
*dt
, char *name
)
1037 dt_prop(dt
, name
, NULL
, 0);
1040 void build_flat_dt(struct iseries_flat_dt
*dt
)
1044 dt_start_node(dt
, "");
1047 dt_push_u32(dt
, OF_DT_END
);
1050 void * __init
iSeries_early_setup(void)
1052 iSeries_fixup_klimit();
1055 * Initialize the table which translate Linux physical addresses to
1056 * AS/400 absolute addresses
1058 build_iSeries_Memory_Map();
1060 build_flat_dt(&iseries_dt
);
1062 return (void *) __pa(&iseries_dt
);