2 * linux/arch/i386/nmi.c
4 * NMI watchdog support on APIC systems
6 * Started by Ingo Molnar <mingo@redhat.com>
9 * Mikael Pettersson : AMD K7 support for local APIC NMI watchdog.
10 * Mikael Pettersson : Power Management for local APIC NMI watchdog.
11 * Mikael Pettersson : Pentium 4 support for local APIC NMI watchdog.
13 * Mikael Pettersson : PM converted to driver model. Disable/enable API.
16 #include <linux/config.h>
17 #include <linux/delay.h>
18 #include <linux/interrupt.h>
19 #include <linux/module.h>
20 #include <linux/nmi.h>
21 #include <linux/sysdev.h>
22 #include <linux/sysctl.h>
23 #include <linux/percpu.h>
28 #include "mach_traps.h"
30 unsigned int nmi_watchdog
= NMI_NONE
;
31 extern int unknown_nmi_panic
;
32 static unsigned int nmi_hz
= HZ
;
33 static unsigned int nmi_perfctr_msr
; /* the MSR to reset in NMI handler */
34 static unsigned int nmi_p4_cccr_val
;
35 extern void show_registers(struct pt_regs
*regs
);
38 * lapic_nmi_owner tracks the ownership of the lapic NMI hardware:
39 * - it may be reserved by some other driver, or not
40 * - when not reserved by some other driver, it may be used for
41 * the NMI watchdog, or not
43 * This is maintained separately from nmi_active because the NMI
44 * watchdog may also be driven from the I/O APIC timer.
46 static DEFINE_SPINLOCK(lapic_nmi_owner_lock
);
47 static unsigned int lapic_nmi_owner
;
48 #define LAPIC_NMI_WATCHDOG (1<<0)
49 #define LAPIC_NMI_RESERVED (1<<1)
52 * +1: the lapic NMI watchdog is active, but can be disabled
53 * 0: the lapic NMI watchdog has not been set up, and cannot
55 * -1: the lapic NMI watchdog is disabled, but can be enabled
59 #define K7_EVNTSEL_ENABLE (1 << 22)
60 #define K7_EVNTSEL_INT (1 << 20)
61 #define K7_EVNTSEL_OS (1 << 17)
62 #define K7_EVNTSEL_USR (1 << 16)
63 #define K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING 0x76
64 #define K7_NMI_EVENT K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING
66 #define P6_EVNTSEL0_ENABLE (1 << 22)
67 #define P6_EVNTSEL_INT (1 << 20)
68 #define P6_EVNTSEL_OS (1 << 17)
69 #define P6_EVNTSEL_USR (1 << 16)
70 #define P6_EVENT_CPU_CLOCKS_NOT_HALTED 0x79
71 #define P6_NMI_EVENT P6_EVENT_CPU_CLOCKS_NOT_HALTED
73 #define MSR_P4_MISC_ENABLE 0x1A0
74 #define MSR_P4_MISC_ENABLE_PERF_AVAIL (1<<7)
75 #define MSR_P4_MISC_ENABLE_PEBS_UNAVAIL (1<<12)
76 #define MSR_P4_PERFCTR0 0x300
77 #define MSR_P4_CCCR0 0x360
78 #define P4_ESCR_EVENT_SELECT(N) ((N)<<25)
79 #define P4_ESCR_OS (1<<3)
80 #define P4_ESCR_USR (1<<2)
81 #define P4_CCCR_OVF_PMI0 (1<<26)
82 #define P4_CCCR_OVF_PMI1 (1<<27)
83 #define P4_CCCR_THRESHOLD(N) ((N)<<20)
84 #define P4_CCCR_COMPLEMENT (1<<19)
85 #define P4_CCCR_COMPARE (1<<18)
86 #define P4_CCCR_REQUIRED (3<<16)
87 #define P4_CCCR_ESCR_SELECT(N) ((N)<<13)
88 #define P4_CCCR_ENABLE (1<<12)
89 /* Set up IQ_COUNTER0 to behave like a clock, by having IQ_CCCR0 filter
90 CRU_ESCR0 (with any non-null event selector) through a complemented
91 max threshold. [IA32-Vol3, Section 14.9.9] */
92 #define MSR_P4_IQ_COUNTER0 0x30C
93 #define P4_NMI_CRU_ESCR0 (P4_ESCR_EVENT_SELECT(0x3F)|P4_ESCR_OS|P4_ESCR_USR)
94 #define P4_NMI_IQ_CCCR0 \
95 (P4_CCCR_OVF_PMI0|P4_CCCR_THRESHOLD(15)|P4_CCCR_COMPLEMENT| \
96 P4_CCCR_COMPARE|P4_CCCR_REQUIRED|P4_CCCR_ESCR_SELECT(4)|P4_CCCR_ENABLE)
99 /* The performance counters used by NMI_LOCAL_APIC don't trigger when
100 * the CPU is idle. To make sure the NMI watchdog really ticks on all
101 * CPUs during the test make them busy.
103 static __init
void nmi_cpu_busy(void *data
)
105 volatile int *endflag
= data
;
107 /* Intentionally don't use cpu_relax here. This is
108 to make sure that the performance counter really ticks,
109 even if there is a simulator or similar that catches the
110 pause instruction. On a real HT machine this is fine because
111 all other CPUs are busy with "useless" delay loops and don't
112 care if they get somewhat less cycles. */
113 while (*endflag
== 0)
118 static int __init
check_nmi_watchdog(void)
120 volatile int endflag
= 0;
121 unsigned int *prev_nmi_count
;
124 if (nmi_watchdog
== NMI_NONE
)
127 prev_nmi_count
= kmalloc(NR_CPUS
* sizeof(int), GFP_KERNEL
);
131 printk(KERN_INFO
"Testing NMI watchdog ... ");
133 if (nmi_watchdog
== NMI_LOCAL_APIC
)
134 smp_call_function(nmi_cpu_busy
, (void *)&endflag
, 0, 0);
136 for_each_possible_cpu(cpu
)
137 prev_nmi_count
[cpu
] = per_cpu(irq_stat
, cpu
).__nmi_count
;
139 mdelay((10*1000)/nmi_hz
); // wait 10 ticks
141 for_each_possible_cpu(cpu
) {
143 /* Check cpu_callin_map here because that is set
144 after the timer is started. */
145 if (!cpu_isset(cpu
, cpu_callin_map
))
148 if (nmi_count(cpu
) - prev_nmi_count
[cpu
] <= 5) {
150 printk("CPU#%d: NMI appears to be stuck (%d->%d)!\n",
155 lapic_nmi_owner
&= ~LAPIC_NMI_WATCHDOG
;
156 kfree(prev_nmi_count
);
163 /* now that we know it works we can reduce NMI frequency to
164 something more reasonable; makes a difference in some configs */
165 if (nmi_watchdog
== NMI_LOCAL_APIC
)
168 kfree(prev_nmi_count
);
171 /* This needs to happen later in boot so counters are working */
172 late_initcall(check_nmi_watchdog
);
174 static int __init
setup_nmi_watchdog(char *str
)
178 get_option(&str
, &nmi
);
180 if (nmi
>= NMI_INVALID
)
185 * If any other x86 CPU has a local APIC, then
186 * please test the NMI stuff there and send me the
187 * missing bits. Right now Intel P6/P4 and AMD K7 only.
189 if ((nmi
== NMI_LOCAL_APIC
) &&
190 (boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
) &&
191 (boot_cpu_data
.x86
== 6 || boot_cpu_data
.x86
== 15))
193 if ((nmi
== NMI_LOCAL_APIC
) &&
194 (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
) &&
195 (boot_cpu_data
.x86
== 6 || boot_cpu_data
.x86
== 15))
198 * We can enable the IO-APIC watchdog
201 if (nmi
== NMI_IO_APIC
) {
208 __setup("nmi_watchdog=", setup_nmi_watchdog
);
210 static void disable_lapic_nmi_watchdog(void)
214 switch (boot_cpu_data
.x86_vendor
) {
216 wrmsr(MSR_K7_EVNTSEL0
, 0, 0);
218 case X86_VENDOR_INTEL
:
219 switch (boot_cpu_data
.x86
) {
221 if (boot_cpu_data
.x86_model
> 0xd)
224 wrmsr(MSR_P6_EVNTSEL0
, 0, 0);
227 if (boot_cpu_data
.x86_model
> 0x4)
230 wrmsr(MSR_P4_IQ_CCCR0
, 0, 0);
231 wrmsr(MSR_P4_CRU_ESCR0
, 0, 0);
237 /* tell do_nmi() and others that we're not active any more */
241 static void enable_lapic_nmi_watchdog(void)
243 if (nmi_active
< 0) {
244 nmi_watchdog
= NMI_LOCAL_APIC
;
245 setup_apic_nmi_watchdog();
249 int reserve_lapic_nmi(void)
251 unsigned int old_owner
;
253 spin_lock(&lapic_nmi_owner_lock
);
254 old_owner
= lapic_nmi_owner
;
255 lapic_nmi_owner
|= LAPIC_NMI_RESERVED
;
256 spin_unlock(&lapic_nmi_owner_lock
);
257 if (old_owner
& LAPIC_NMI_RESERVED
)
259 if (old_owner
& LAPIC_NMI_WATCHDOG
)
260 disable_lapic_nmi_watchdog();
264 void release_lapic_nmi(void)
266 unsigned int new_owner
;
268 spin_lock(&lapic_nmi_owner_lock
);
269 new_owner
= lapic_nmi_owner
& ~LAPIC_NMI_RESERVED
;
270 lapic_nmi_owner
= new_owner
;
271 spin_unlock(&lapic_nmi_owner_lock
);
272 if (new_owner
& LAPIC_NMI_WATCHDOG
)
273 enable_lapic_nmi_watchdog();
276 void disable_timer_nmi_watchdog(void)
278 if ((nmi_watchdog
!= NMI_IO_APIC
) || (nmi_active
<= 0))
281 unset_nmi_callback();
283 nmi_watchdog
= NMI_NONE
;
286 void enable_timer_nmi_watchdog(void)
288 if (nmi_active
< 0) {
289 nmi_watchdog
= NMI_IO_APIC
;
290 touch_nmi_watchdog();
297 static int nmi_pm_active
; /* nmi_active before suspend */
299 static int lapic_nmi_suspend(struct sys_device
*dev
, pm_message_t state
)
301 nmi_pm_active
= nmi_active
;
302 disable_lapic_nmi_watchdog();
306 static int lapic_nmi_resume(struct sys_device
*dev
)
308 if (nmi_pm_active
> 0)
309 enable_lapic_nmi_watchdog();
314 static struct sysdev_class nmi_sysclass
= {
315 set_kset_name("lapic_nmi"),
316 .resume
= lapic_nmi_resume
,
317 .suspend
= lapic_nmi_suspend
,
320 static struct sys_device device_lapic_nmi
= {
322 .cls
= &nmi_sysclass
,
325 static int __init
init_lapic_nmi_sysfs(void)
329 if (nmi_active
== 0 || nmi_watchdog
!= NMI_LOCAL_APIC
)
332 error
= sysdev_class_register(&nmi_sysclass
);
334 error
= sysdev_register(&device_lapic_nmi
);
337 /* must come after the local APIC's device_initcall() */
338 late_initcall(init_lapic_nmi_sysfs
);
340 #endif /* CONFIG_PM */
343 * Activate the NMI watchdog via the local APIC.
344 * Original code written by Keith Owens.
347 static void clear_msr_range(unsigned int base
, unsigned int n
)
351 for(i
= 0; i
< n
; ++i
)
355 static void write_watchdog_counter(const char *descr
)
357 u64 count
= (u64
)cpu_khz
* 1000;
359 do_div(count
, nmi_hz
);
361 Dprintk("setting %s to -0x%08Lx\n", descr
, count
);
362 wrmsrl(nmi_perfctr_msr
, 0 - count
);
365 static void setup_k7_watchdog(void)
367 unsigned int evntsel
;
369 nmi_perfctr_msr
= MSR_K7_PERFCTR0
;
371 clear_msr_range(MSR_K7_EVNTSEL0
, 4);
372 clear_msr_range(MSR_K7_PERFCTR0
, 4);
374 evntsel
= K7_EVNTSEL_INT
379 wrmsr(MSR_K7_EVNTSEL0
, evntsel
, 0);
380 write_watchdog_counter("K7_PERFCTR0");
381 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
382 evntsel
|= K7_EVNTSEL_ENABLE
;
383 wrmsr(MSR_K7_EVNTSEL0
, evntsel
, 0);
386 static void setup_p6_watchdog(void)
388 unsigned int evntsel
;
390 nmi_perfctr_msr
= MSR_P6_PERFCTR0
;
392 clear_msr_range(MSR_P6_EVNTSEL0
, 2);
393 clear_msr_range(MSR_P6_PERFCTR0
, 2);
395 evntsel
= P6_EVNTSEL_INT
400 wrmsr(MSR_P6_EVNTSEL0
, evntsel
, 0);
401 write_watchdog_counter("P6_PERFCTR0");
402 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
403 evntsel
|= P6_EVNTSEL0_ENABLE
;
404 wrmsr(MSR_P6_EVNTSEL0
, evntsel
, 0);
407 static int setup_p4_watchdog(void)
409 unsigned int misc_enable
, dummy
;
411 rdmsr(MSR_P4_MISC_ENABLE
, misc_enable
, dummy
);
412 if (!(misc_enable
& MSR_P4_MISC_ENABLE_PERF_AVAIL
))
415 nmi_perfctr_msr
= MSR_P4_IQ_COUNTER0
;
416 nmi_p4_cccr_val
= P4_NMI_IQ_CCCR0
;
418 if (smp_num_siblings
== 2)
419 nmi_p4_cccr_val
|= P4_CCCR_OVF_PMI1
;
422 if (!(misc_enable
& MSR_P4_MISC_ENABLE_PEBS_UNAVAIL
))
423 clear_msr_range(0x3F1, 2);
424 /* MSR 0x3F0 seems to have a default value of 0xFC00, but current
425 docs doesn't fully define it, so leave it alone for now. */
426 if (boot_cpu_data
.x86_model
>= 0x3) {
427 /* MSR_P4_IQ_ESCR0/1 (0x3ba/0x3bb) removed */
428 clear_msr_range(0x3A0, 26);
429 clear_msr_range(0x3BC, 3);
431 clear_msr_range(0x3A0, 31);
433 clear_msr_range(0x3C0, 6);
434 clear_msr_range(0x3C8, 6);
435 clear_msr_range(0x3E0, 2);
436 clear_msr_range(MSR_P4_CCCR0
, 18);
437 clear_msr_range(MSR_P4_PERFCTR0
, 18);
439 wrmsr(MSR_P4_CRU_ESCR0
, P4_NMI_CRU_ESCR0
, 0);
440 wrmsr(MSR_P4_IQ_CCCR0
, P4_NMI_IQ_CCCR0
& ~P4_CCCR_ENABLE
, 0);
441 write_watchdog_counter("P4_IQ_COUNTER0");
442 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
443 wrmsr(MSR_P4_IQ_CCCR0
, nmi_p4_cccr_val
, 0);
447 void setup_apic_nmi_watchdog (void)
449 switch (boot_cpu_data
.x86_vendor
) {
451 if (boot_cpu_data
.x86
!= 6 && boot_cpu_data
.x86
!= 15)
455 case X86_VENDOR_INTEL
:
456 switch (boot_cpu_data
.x86
) {
458 if (boot_cpu_data
.x86_model
> 0xd)
464 if (boot_cpu_data
.x86_model
> 0x4)
467 if (!setup_p4_watchdog())
477 lapic_nmi_owner
= LAPIC_NMI_WATCHDOG
;
482 * the best way to detect whether a CPU has a 'hard lockup' problem
483 * is to check it's local APIC timer IRQ counts. If they are not
484 * changing then that CPU has some problem.
486 * as these watchdog NMI IRQs are generated on every CPU, we only
487 * have to check the current processor.
489 * since NMIs don't listen to _any_ locks, we have to be extremely
490 * careful not to rely on unsafe variables. The printk might lock
491 * up though, so we have to break up any console locks first ...
492 * [when there will be more tty-related locks, break them up
497 last_irq_sums
[NR_CPUS
],
498 alert_counter
[NR_CPUS
];
500 void touch_nmi_watchdog (void)
505 * Just reset the alert counters, (other CPUs might be
506 * spinning on locks we hold):
508 for_each_possible_cpu(i
)
509 alert_counter
[i
] = 0;
512 * Tickle the softlockup detector too:
514 touch_softlockup_watchdog();
517 extern void die_nmi(struct pt_regs
*, const char *msg
);
519 void nmi_watchdog_tick (struct pt_regs
* regs
)
523 * Since current_thread_info()-> is always on the stack, and we
524 * always switch the stack NMI-atomically, it's safe to use
525 * smp_processor_id().
528 int cpu
= smp_processor_id();
530 sum
= per_cpu(irq_stat
, cpu
).apic_timer_irqs
;
532 if (last_irq_sums
[cpu
] == sum
) {
534 * Ayiee, looks like this CPU is stuck ...
535 * wait a few IRQs (5 seconds) before doing the oops ...
537 alert_counter
[cpu
]++;
538 if (alert_counter
[cpu
] == 5*nmi_hz
)
540 * die_nmi will return ONLY if NOTIFY_STOP happens..
542 die_nmi(regs
, "BUG: NMI Watchdog detected LOCKUP");
544 last_irq_sums
[cpu
] = sum
;
545 alert_counter
[cpu
] = 0;
547 if (nmi_perfctr_msr
) {
548 if (nmi_perfctr_msr
== MSR_P4_IQ_COUNTER0
) {
551 * - An overflown perfctr will assert its interrupt
552 * until the OVF flag in its CCCR is cleared.
553 * - LVTPC is masked on interrupt and must be
554 * unmasked by the LVTPC handler.
556 wrmsr(MSR_P4_IQ_CCCR0
, nmi_p4_cccr_val
, 0);
557 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
559 else if (nmi_perfctr_msr
== MSR_P6_PERFCTR0
) {
560 /* Only P6 based Pentium M need to re-unmask
561 * the apic vector but it doesn't hurt
562 * other P6 variant */
563 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
565 write_watchdog_counter(NULL
);
571 static int unknown_nmi_panic_callback(struct pt_regs
*regs
, int cpu
)
573 unsigned char reason
= get_nmi_reason();
576 if (!(reason
& 0xc0)) {
577 sprintf(buf
, "NMI received for unknown reason %02x\n", reason
);
584 * proc handler for /proc/sys/kernel/unknown_nmi_panic
586 int proc_unknown_nmi_panic(ctl_table
*table
, int write
, struct file
*file
,
587 void __user
*buffer
, size_t *length
, loff_t
*ppos
)
591 old_state
= unknown_nmi_panic
;
592 proc_dointvec(table
, write
, file
, buffer
, length
, ppos
);
593 if (!!old_state
== !!unknown_nmi_panic
)
596 if (unknown_nmi_panic
) {
597 if (reserve_lapic_nmi() < 0) {
598 unknown_nmi_panic
= 0;
601 set_nmi_callback(unknown_nmi_panic_callback
);
605 unset_nmi_callback();
612 EXPORT_SYMBOL(nmi_active
);
613 EXPORT_SYMBOL(nmi_watchdog
);
614 EXPORT_SYMBOL(reserve_lapic_nmi
);
615 EXPORT_SYMBOL(release_lapic_nmi
);
616 EXPORT_SYMBOL(disable_timer_nmi_watchdog
);
617 EXPORT_SYMBOL(enable_timer_nmi_watchdog
);