?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
sky2: debug interface
[usb.git] / drivers / net / sky2.c
blob90b1b970817853fd25fc6d14d92465a8859ce476
1 /*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
25 #include <linux/crc32.h>
26 #include <linux/kernel.h>
27 #include <linux/version.h>
28 #include <linux/module.h>
29 #include <linux/netdevice.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/etherdevice.h>
32 #include <linux/ethtool.h>
33 #include <linux/pci.h>
34 #include <linux/ip.h>
35 #include <net/ip.h>
36 #include <linux/tcp.h>
37 #include <linux/in.h>
38 #include <linux/delay.h>
39 #include <linux/workqueue.h>
40 #include <linux/if_vlan.h>
41 #include <linux/prefetch.h>
42 #include <linux/debugfs.h>
43 #include <linux/mii.h>
44
45 #include <asm/irq.h>
46
47 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
48 #define SKY2_VLAN_TAG_USED 1
49 #endif
50
51 #include "sky2.h"
52
53 #define DRV_NAME "sky2"
54 #define DRV_VERSION "1.15"
55 #define PFX DRV_NAME " "
56
57 /*
58 * The Yukon II chipset takes 64 bit command blocks (called list elements)
59 * that are organized into three (receive, transmit, status) different rings
60 * similar to Tigon3.
61 */
62
63 #define RX_LE_SIZE 1024
64 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
65 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
66 #define RX_DEF_PENDING RX_MAX_PENDING
67 #define RX_SKB_ALIGN 8
68 #define RX_BUF_WRITE 16
69
70 #define TX_RING_SIZE 512
71 #define TX_DEF_PENDING (TX_RING_SIZE - 1)
72 #define TX_MIN_PENDING 64
73 #define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
74
75 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
76 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
77 #define TX_WATCHDOG (5 * HZ)
78 #define NAPI_WEIGHT 64
79 #define PHY_RETRIES 1000
80
81 #define RING_NEXT(x,s) (((x)+1) & ((s)-1))
82
83 static const u32 default_msg =
84 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
85 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
86 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
87
88 static int debug = -1; /* defaults above */
89 module_param(debug, int, 0);
90 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
91
92 static int copybreak __read_mostly = 128;
93 module_param(copybreak, int, 0);
94 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
95
96 static int disable_msi = 0;
97 module_param(disable_msi, int, 0);
98 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
99
100 static int idle_timeout = 100;
101 module_param(idle_timeout, int, 0);
102 MODULE_PARM_DESC(idle_timeout, "Watchdog timer for lost interrupts (ms)");
103
104 static const struct pci_device_id sky2_id_table[] = {
105 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
106 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
109 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
110 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
135 { 0 }
136 };
137
138 MODULE_DEVICE_TABLE(pci, sky2_id_table);
139
140 /* Avoid conditionals by using array */
141 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
142 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
143 static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
144
145 /* This driver supports yukon2 chipset only */
146 static const char *yukon2_name[] = {
147 "XL", /* 0xb3 */
148 "EC Ultra", /* 0xb4 */
149 "Extreme", /* 0xb5 */
150 "EC", /* 0xb6 */
151 "FE", /* 0xb7 */
152 };
153
154 /* Access to external PHY */
155 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
156 {
157 int i;
158
159 gma_write16(hw, port, GM_SMI_DATA, val);
160 gma_write16(hw, port, GM_SMI_CTRL,
161 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
162
163 for (i = 0; i < PHY_RETRIES; i++) {
164 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
165 return 0;
166 udelay(1);
167 }
168
169 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
170 return -ETIMEDOUT;
171 }
172
173 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
174 {
175 int i;
176
177 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
178 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
179
180 for (i = 0; i < PHY_RETRIES; i++) {
181 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
182 *val = gma_read16(hw, port, GM_SMI_DATA);
183 return 0;
184 }
185
186 udelay(1);
187 }
188
189 return -ETIMEDOUT;
190 }
191
192 static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
193 {
194 u16 v;
195
196 if (__gm_phy_read(hw, port, reg, &v) != 0)
197 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
198 return v;
199 }
200
201
202 static void sky2_power_on(struct sky2_hw *hw)
203 {
204 /* switch power to VCC (WA for VAUX problem) */
205 sky2_write8(hw, B0_POWER_CTRL,
206 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
207
208 /* disable Core Clock Division, */
209 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
210
211 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
212 /* enable bits are inverted */
213 sky2_write8(hw, B2_Y2_CLK_GATE,
214 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
215 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
216 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
217 else
218 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
219
220 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX) {
221 u32 reg;
222
223 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
224 /* set all bits to 0 except bits 15..12 and 8 */
225 reg &= P_ASPM_CONTROL_MSK;
226 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
227
228 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
229 /* set all bits to 0 except bits 28 & 27 */
230 reg &= P_CTL_TIM_VMAIN_AV_MSK;
231 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
232
233 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
234
235 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
236 reg = sky2_read32(hw, B2_GP_IO);
237 reg |= GLB_GPIO_STAT_RACE_DIS;
238 sky2_write32(hw, B2_GP_IO, reg);
239 }
240 }
241
242 static void sky2_power_aux(struct sky2_hw *hw)
243 {
244 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
245 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
246 else
247 /* enable bits are inverted */
248 sky2_write8(hw, B2_Y2_CLK_GATE,
249 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
250 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
251 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
252
253 /* switch power to VAUX */
254 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
255 sky2_write8(hw, B0_POWER_CTRL,
256 (PC_VAUX_ENA | PC_VCC_ENA |
257 PC_VAUX_ON | PC_VCC_OFF));
258 }
259
260 static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
261 {
262 u16 reg;
263
264 /* disable all GMAC IRQ's */
265 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
266 /* disable PHY IRQs */
267 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
268
269 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
270 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
271 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
272 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
273
274 reg = gma_read16(hw, port, GM_RX_CTRL);
275 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
276 gma_write16(hw, port, GM_RX_CTRL, reg);
277 }
278
279 /* flow control to advertise bits */
280 static const u16 copper_fc_adv[] = {
281 [FC_NONE] = 0,
282 [FC_TX] = PHY_M_AN_ASP,
283 [FC_RX] = PHY_M_AN_PC,
284 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
285 };
286
287 /* flow control to advertise bits when using 1000BaseX */
288 static const u16 fiber_fc_adv[] = {
289 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
290 [FC_TX] = PHY_M_P_ASYM_MD_X,
291 [FC_RX] = PHY_M_P_SYM_MD_X,
292 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
293 };
294
295 /* flow control to GMA disable bits */
296 static const u16 gm_fc_disable[] = {
297 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
298 [FC_TX] = GM_GPCR_FC_RX_DIS,
299 [FC_RX] = GM_GPCR_FC_TX_DIS,
300 [FC_BOTH] = 0,
301 };
302
303
304 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
305 {
306 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
307 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
308
309 if (sky2->autoneg == AUTONEG_ENABLE
310 && !(hw->chip_id == CHIP_ID_YUKON_XL
311 || hw->chip_id == CHIP_ID_YUKON_EC_U
312 || hw->chip_id == CHIP_ID_YUKON_EX)) {
313 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
314
315 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
316 PHY_M_EC_MAC_S_MSK);
317 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
318
319 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
320 if (hw->chip_id == CHIP_ID_YUKON_EC)
321 /* set downshift counter to 3x and enable downshift */
322 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
323 else
324 /* set master & slave downshift counter to 1x */
325 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
326
327 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
328 }
329
330 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
331 if (sky2_is_copper(hw)) {
332 if (hw->chip_id == CHIP_ID_YUKON_FE) {
333 /* enable automatic crossover */
334 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
335 } else {
336 /* disable energy detect */
337 ctrl &= ~PHY_M_PC_EN_DET_MSK;
338
339 /* enable automatic crossover */
340 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
341
342 /* downshift on PHY 88E1112 and 88E1149 is changed */
343 if (sky2->autoneg == AUTONEG_ENABLE
344 && (hw->chip_id == CHIP_ID_YUKON_XL
345 || hw->chip_id == CHIP_ID_YUKON_EC_U
346 || hw->chip_id == CHIP_ID_YUKON_EX)) {
347 /* set downshift counter to 3x and enable downshift */
348 ctrl &= ~PHY_M_PC_DSC_MSK;
349 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
350 }
351 }
352 } else {
353 /* workaround for deviation #4.88 (CRC errors) */
354 /* disable Automatic Crossover */
355
356 ctrl &= ~PHY_M_PC_MDIX_MSK;
357 }
358
359 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
360
361 /* special setup for PHY 88E1112 Fiber */
362 if (hw->chip_id == CHIP_ID_YUKON_XL && !sky2_is_copper(hw)) {
363 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
364
365 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
366 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
367 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
368 ctrl &= ~PHY_M_MAC_MD_MSK;
369 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
370 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
371
372 if (hw->pmd_type == 'P') {
373 /* select page 1 to access Fiber registers */
374 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
375
376 /* for SFP-module set SIGDET polarity to low */
377 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
378 ctrl |= PHY_M_FIB_SIGD_POL;
379 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
380 }
381
382 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
383 }
384
385 ctrl = PHY_CT_RESET;
386 ct1000 = 0;
387 adv = PHY_AN_CSMA;
388 reg = 0;
389
390 if (sky2->autoneg == AUTONEG_ENABLE) {
391 if (sky2_is_copper(hw)) {
392 if (sky2->advertising & ADVERTISED_1000baseT_Full)
393 ct1000 |= PHY_M_1000C_AFD;
394 if (sky2->advertising & ADVERTISED_1000baseT_Half)
395 ct1000 |= PHY_M_1000C_AHD;
396 if (sky2->advertising & ADVERTISED_100baseT_Full)
397 adv |= PHY_M_AN_100_FD;
398 if (sky2->advertising & ADVERTISED_100baseT_Half)
399 adv |= PHY_M_AN_100_HD;
400 if (sky2->advertising & ADVERTISED_10baseT_Full)
401 adv |= PHY_M_AN_10_FD;
402 if (sky2->advertising & ADVERTISED_10baseT_Half)
403 adv |= PHY_M_AN_10_HD;
404
405 adv |= copper_fc_adv[sky2->flow_mode];
406 } else { /* special defines for FIBER (88E1040S only) */
407 if (sky2->advertising & ADVERTISED_1000baseT_Full)
408 adv |= PHY_M_AN_1000X_AFD;
409 if (sky2->advertising & ADVERTISED_1000baseT_Half)
410 adv |= PHY_M_AN_1000X_AHD;
411
412 adv |= fiber_fc_adv[sky2->flow_mode];
413 }
414
415 /* Restart Auto-negotiation */
416 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
417 } else {
418 /* forced speed/duplex settings */
419 ct1000 = PHY_M_1000C_MSE;
420
421 /* Disable auto update for duplex flow control and speed */
422 reg |= GM_GPCR_AU_ALL_DIS;
423
424 switch (sky2->speed) {
425 case SPEED_1000:
426 ctrl |= PHY_CT_SP1000;
427 reg |= GM_GPCR_SPEED_1000;
428 break;
429 case SPEED_100:
430 ctrl |= PHY_CT_SP100;
431 reg |= GM_GPCR_SPEED_100;
432 break;
433 }
434
435 if (sky2->duplex == DUPLEX_FULL) {
436 reg |= GM_GPCR_DUP_FULL;
437 ctrl |= PHY_CT_DUP_MD;
438 } else if (sky2->speed < SPEED_1000)
439 sky2->flow_mode = FC_NONE;
440
441
442 reg |= gm_fc_disable[sky2->flow_mode];
443
444 /* Forward pause packets to GMAC? */
445 if (sky2->flow_mode & FC_RX)
446 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
447 else
448 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
449 }
450
451 gma_write16(hw, port, GM_GP_CTRL, reg);
452
453 if (hw->chip_id != CHIP_ID_YUKON_FE)
454 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
455
456 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
457 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
458
459 /* Setup Phy LED's */
460 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
461 ledover = 0;
462
463 switch (hw->chip_id) {
464 case CHIP_ID_YUKON_FE:
465 /* on 88E3082 these bits are at 11..9 (shifted left) */
466 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
467
468 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
469
470 /* delete ACT LED control bits */
471 ctrl &= ~PHY_M_FELP_LED1_MSK;
472 /* change ACT LED control to blink mode */
473 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
474 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
475 break;
476
477 case CHIP_ID_YUKON_XL:
478 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
479
480 /* select page 3 to access LED control register */
481 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
482
483 /* set LED Function Control register */
484 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
485 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
486 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
487 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
488 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
489
490 /* set Polarity Control register */
491 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
492 (PHY_M_POLC_LS1_P_MIX(4) |
493 PHY_M_POLC_IS0_P_MIX(4) |
494 PHY_M_POLC_LOS_CTRL(2) |
495 PHY_M_POLC_INIT_CTRL(2) |
496 PHY_M_POLC_STA1_CTRL(2) |
497 PHY_M_POLC_STA0_CTRL(2)));
498
499 /* restore page register */
500 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
501 break;
502
503 case CHIP_ID_YUKON_EC_U:
504 case CHIP_ID_YUKON_EX:
505 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
506
507 /* select page 3 to access LED control register */
508 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
509
510 /* set LED Function Control register */
511 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
512 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
513 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
514 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
515 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
516
517 /* set Blink Rate in LED Timer Control Register */
518 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
519 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
520 /* restore page register */
521 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
522 break;
523
524 default:
525 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
526 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
527 /* turn off the Rx LED (LED_RX) */
528 ledover &= ~PHY_M_LED_MO_RX;
529 }
530
531 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
532 hw->chip_rev == CHIP_REV_YU_EC_U_A1) {
533 /* apply fixes in PHY AFE */
534 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
535
536 /* increase differential signal amplitude in 10BASE-T */
537 gm_phy_write(hw, port, 0x18, 0xaa99);
538 gm_phy_write(hw, port, 0x17, 0x2011);
539
540 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
541 gm_phy_write(hw, port, 0x18, 0xa204);
542 gm_phy_write(hw, port, 0x17, 0x2002);
543
544 /* set page register to 0 */
545 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
546 } else if (hw->chip_id != CHIP_ID_YUKON_EX) {
547 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
548
549 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
550 /* turn on 100 Mbps LED (LED_LINK100) */
551 ledover |= PHY_M_LED_MO_100;
552 }
553
554 if (ledover)
555 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
556
557 }
558
559 /* Enable phy interrupt on auto-negotiation complete (or link up) */
560 if (sky2->autoneg == AUTONEG_ENABLE)
561 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
562 else
563 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
564 }
565
566 static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff)
567 {
568 u32 reg1;
569 static const u32 phy_power[]
570 = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
571
572 /* looks like this XL is back asswards .. */
573 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
574 onoff = !onoff;
575
576 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
577 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
578 if (onoff)
579 /* Turn off phy power saving */
580 reg1 &= ~phy_power[port];
581 else
582 reg1 |= phy_power[port];
583
584 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
585 sky2_pci_read32(hw, PCI_DEV_REG1);
586 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
587 udelay(100);
588 }
589
590 /* Force a renegotiation */
591 static void sky2_phy_reinit(struct sky2_port *sky2)
592 {
593 spin_lock_bh(&sky2->phy_lock);
594 sky2_phy_init(sky2->hw, sky2->port);
595 spin_unlock_bh(&sky2->phy_lock);
596 }
597
598 /* Put device in state to listen for Wake On Lan */
599 static void sky2_wol_init(struct sky2_port *sky2)
600 {
601 struct sky2_hw *hw = sky2->hw;
602 unsigned port = sky2->port;
603 enum flow_control save_mode;
604 u16 ctrl;
605 u32 reg1;
606
607 /* Bring hardware out of reset */
608 sky2_write16(hw, B0_CTST, CS_RST_CLR);
609 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
610
611 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
612 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
613
614 /* Force to 10/100
615 * sky2_reset will re-enable on resume
616 */
617 save_mode = sky2->flow_mode;
618 ctrl = sky2->advertising;
619
620 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
621 sky2->flow_mode = FC_NONE;
622 sky2_phy_power(hw, port, 1);
623 sky2_phy_reinit(sky2);
624
625 sky2->flow_mode = save_mode;
626 sky2->advertising = ctrl;
627
628 /* Set GMAC to no flow control and auto update for speed/duplex */
629 gma_write16(hw, port, GM_GP_CTRL,
630 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
631 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
632
633 /* Set WOL address */
634 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
635 sky2->netdev->dev_addr, ETH_ALEN);
636
637 /* Turn on appropriate WOL control bits */
638 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
639 ctrl = 0;
640 if (sky2->wol & WAKE_PHY)
641 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
642 else
643 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
644
645 if (sky2->wol & WAKE_MAGIC)
646 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
647 else
648 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
649
650 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
651 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
652
653 /* Turn on legacy PCI-Express PME mode */
654 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
655 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
656 reg1 |= PCI_Y2_PME_LEGACY;
657 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
658 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
659
660 /* block receiver */
661 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
662
663 }
664
665 static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
666 {
667 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev != CHIP_REV_YU_EX_A0) {
668 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
669 TX_STFW_ENA |
670 (hw->dev[port]->mtu > ETH_DATA_LEN) ? TX_JUMBO_ENA : TX_JUMBO_DIS);
671 } else {
672 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
673 /* set Tx GMAC FIFO Almost Empty Threshold */
674 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
675 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
676
677 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
678 TX_JUMBO_ENA | TX_STFW_DIS);
679
680 /* Can't do offload because of lack of store/forward */
681 hw->dev[port]->features &= ~(NETIF_F_TSO | NETIF_F_SG
682 | NETIF_F_ALL_CSUM);
683 } else
684 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
685 TX_JUMBO_DIS | TX_STFW_ENA);
686 }
687 }
688
689 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
690 {
691 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
692 u16 reg;
693 int i;
694 const u8 *addr = hw->dev[port]->dev_addr;
695
696 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
697 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
698
699 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
700
701 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
702 /* WA DEV_472 -- looks like crossed wires on port 2 */
703 /* clear GMAC 1 Control reset */
704 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
705 do {
706 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
707 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
708 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
709 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
710 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
711 }
712
713 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
714
715 /* Enable Transmit FIFO Underrun */
716 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
717
718 spin_lock_bh(&sky2->phy_lock);
719 sky2_phy_init(hw, port);
720 spin_unlock_bh(&sky2->phy_lock);
721
722 /* MIB clear */
723 reg = gma_read16(hw, port, GM_PHY_ADDR);
724 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
725
726 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
727 gma_read16(hw, port, i);
728 gma_write16(hw, port, GM_PHY_ADDR, reg);
729
730 /* transmit control */
731 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
732
733 /* receive control reg: unicast + multicast + no FCS */
734 gma_write16(hw, port, GM_RX_CTRL,
735 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
736
737 /* transmit flow control */
738 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
739
740 /* transmit parameter */
741 gma_write16(hw, port, GM_TX_PARAM,
742 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
743 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
744 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
745 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
746
747 /* serial mode register */
748 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
749 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
750
751 if (hw->dev[port]->mtu > ETH_DATA_LEN)
752 reg |= GM_SMOD_JUMBO_ENA;
753
754 gma_write16(hw, port, GM_SERIAL_MODE, reg);
755
756 /* virtual address for data */
757 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
758
759 /* physical address: used for pause frames */
760 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
761
762 /* ignore counter overflows */
763 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
764 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
765 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
766
767 /* Configure Rx MAC FIFO */
768 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
769 reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
770 if (hw->chip_id == CHIP_ID_YUKON_EX)
771 reg |= GMF_RX_OVER_ON;
772
773 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
774
775 /* Flush Rx MAC FIFO on any flow control or error */
776 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
777
778 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
779 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
780
781 /* Configure Tx MAC FIFO */
782 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
783 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
784
785 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX) {
786 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
787 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
788
789 sky2_set_tx_stfwd(hw, port);
790 }
791
792 }
793
794 /* Assign Ram Buffer allocation to queue */
795 static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
796 {
797 u32 end;
798
799 /* convert from K bytes to qwords used for hw register */
800 start *= 1024/8;
801 space *= 1024/8;
802 end = start + space - 1;
803
804 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
805 sky2_write32(hw, RB_ADDR(q, RB_START), start);
806 sky2_write32(hw, RB_ADDR(q, RB_END), end);
807 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
808 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
809
810 if (q == Q_R1 || q == Q_R2) {
811 u32 tp = space - space/4;
812
813 /* On receive queue's set the thresholds
814 * give receiver priority when > 3/4 full
815 * send pause when down to 2K
816 */
817 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
818 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
819
820 tp = space - 2048/8;
821 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
822 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
823 } else {
824 /* Enable store & forward on Tx queue's because
825 * Tx FIFO is only 1K on Yukon
826 */
827 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
828 }
829
830 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
831 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
832 }
833
834 /* Setup Bus Memory Interface */
835 static void sky2_qset(struct sky2_hw *hw, u16 q)
836 {
837 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
838 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
839 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
840 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
841 }
842
843 /* Setup prefetch unit registers. This is the interface between
844 * hardware and driver list elements
845 */
846 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
847 u64 addr, u32 last)
848 {
849 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
850 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
851 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
852 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
853 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
854 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
855
856 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
857 }
858
859 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
860 {
861 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
862
863 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
864 le->ctrl = 0;
865 return le;
866 }
867
868 static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
869 struct sky2_tx_le *le)
870 {
871 return sky2->tx_ring + (le - sky2->tx_le);
872 }
873
874 /* Update chip's next pointer */
875 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
876 {
877 /* Make sure write' to descriptors are complete before we tell hardware */
878 wmb();
879 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
880
881 /* Synchronize I/O on since next processor may write to tail */
882 mmiowb();
883 }
884
885
886 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
887 {
888 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
889 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
890 le->ctrl = 0;
891 return le;
892 }
893
894 /* Return high part of DMA address (could be 32 or 64 bit) */
895 static inline u32 high32(dma_addr_t a)
896 {
897 return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0;
898 }
899
900 /* Build description to hardware for one receive segment */
901 static void sky2_rx_add(struct sky2_port *sky2, u8 op,
902 dma_addr_t map, unsigned len)
903 {
904 struct sky2_rx_le *le;
905 u32 hi = high32(map);
906
907 if (sky2->rx_addr64 != hi) {
908 le = sky2_next_rx(sky2);
909 le->addr = cpu_to_le32(hi);
910 le->opcode = OP_ADDR64 | HW_OWNER;
911 sky2->rx_addr64 = high32(map + len);
912 }
913
914 le = sky2_next_rx(sky2);
915 le->addr = cpu_to_le32((u32) map);
916 le->length = cpu_to_le16(len);
917 le->opcode = op | HW_OWNER;
918 }
919
920 /* Build description to hardware for one possibly fragmented skb */
921 static void sky2_rx_submit(struct sky2_port *sky2,
922 const struct rx_ring_info *re)
923 {
924 int i;
925
926 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
927
928 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
929 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
930 }
931
932
933 static void sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
934 unsigned size)
935 {
936 struct sk_buff *skb = re->skb;
937 int i;
938
939 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
940 pci_unmap_len_set(re, data_size, size);
941
942 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
943 re->frag_addr[i] = pci_map_page(pdev,
944 skb_shinfo(skb)->frags[i].page,
945 skb_shinfo(skb)->frags[i].page_offset,
946 skb_shinfo(skb)->frags[i].size,
947 PCI_DMA_FROMDEVICE);
948 }
949
950 static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
951 {
952 struct sk_buff *skb = re->skb;
953 int i;
954
955 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
956 PCI_DMA_FROMDEVICE);
957
958 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
959 pci_unmap_page(pdev, re->frag_addr[i],
960 skb_shinfo(skb)->frags[i].size,
961 PCI_DMA_FROMDEVICE);
962 }
963
964 /* Tell chip where to start receive checksum.
965 * Actually has two checksums, but set both same to avoid possible byte
966 * order problems.
967 */
968 static void rx_set_checksum(struct sky2_port *sky2)
969 {
970 struct sky2_rx_le *le;
971
972 if (sky2->hw->chip_id != CHIP_ID_YUKON_EX) {
973 le = sky2_next_rx(sky2);
974 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
975 le->ctrl = 0;
976 le->opcode = OP_TCPSTART | HW_OWNER;
977
978 sky2_write32(sky2->hw,
979 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
980 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
981 }
982
983 }
984
985 /*
986 * The RX Stop command will not work for Yukon-2 if the BMU does not
987 * reach the end of packet and since we can't make sure that we have
988 * incoming data, we must reset the BMU while it is not doing a DMA
989 * transfer. Since it is possible that the RX path is still active,
990 * the RX RAM buffer will be stopped first, so any possible incoming
991 * data will not trigger a DMA. After the RAM buffer is stopped, the
992 * BMU is polled until any DMA in progress is ended and only then it
993 * will be reset.
994 */
995 static void sky2_rx_stop(struct sky2_port *sky2)
996 {
997 struct sky2_hw *hw = sky2->hw;
998 unsigned rxq = rxqaddr[sky2->port];
999 int i;
1000
1001 /* disable the RAM Buffer receive queue */
1002 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1003
1004 for (i = 0; i < 0xffff; i++)
1005 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1006 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1007 goto stopped;
1008
1009 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
1010 sky2->netdev->name);
1011 stopped:
1012 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1013
1014 /* reset the Rx prefetch unit */
1015 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1016 mmiowb();
1017 }
1018
1019 /* Clean out receive buffer area, assumes receiver hardware stopped */
1020 static void sky2_rx_clean(struct sky2_port *sky2)
1021 {
1022 unsigned i;
1023
1024 memset(sky2->rx_le, 0, RX_LE_BYTES);
1025 for (i = 0; i < sky2->rx_pending; i++) {
1026 struct rx_ring_info *re = sky2->rx_ring + i;
1027
1028 if (re->skb) {
1029 sky2_rx_unmap_skb(sky2->hw->pdev, re);
1030 kfree_skb(re->skb);
1031 re->skb = NULL;
1032 }
1033 }
1034 }
1035
1036 /* Basic MII support */
1037 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1038 {
1039 struct mii_ioctl_data *data = if_mii(ifr);
1040 struct sky2_port *sky2 = netdev_priv(dev);
1041 struct sky2_hw *hw = sky2->hw;
1042 int err = -EOPNOTSUPP;
1043
1044 if (!netif_running(dev))
1045 return -ENODEV; /* Phy still in reset */
1046
1047 switch (cmd) {
1048 case SIOCGMIIPHY:
1049 data->phy_id = PHY_ADDR_MARV;
1050
1051 /* fallthru */
1052 case SIOCGMIIREG: {
1053 u16 val = 0;
1054
1055 spin_lock_bh(&sky2->phy_lock);
1056 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
1057 spin_unlock_bh(&sky2->phy_lock);
1058
1059 data->val_out = val;
1060 break;
1061 }
1062
1063 case SIOCSMIIREG:
1064 if (!capable(CAP_NET_ADMIN))
1065 return -EPERM;
1066
1067 spin_lock_bh(&sky2->phy_lock);
1068 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1069 data->val_in);
1070 spin_unlock_bh(&sky2->phy_lock);
1071 break;
1072 }
1073 return err;
1074 }
1075
1076 #ifdef SKY2_VLAN_TAG_USED
1077 static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1078 {
1079 struct sky2_port *sky2 = netdev_priv(dev);
1080 struct sky2_hw *hw = sky2->hw;
1081 u16 port = sky2->port;
1082
1083 netif_tx_lock_bh(dev);
1084 netif_poll_disable(sky2->hw->dev[0]);
1085
1086 sky2->vlgrp = grp;
1087 if (grp) {
1088 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1089 RX_VLAN_STRIP_ON);
1090 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1091 TX_VLAN_TAG_ON);
1092 } else {
1093 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1094 RX_VLAN_STRIP_OFF);
1095 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1096 TX_VLAN_TAG_OFF);
1097 }
1098
1099 netif_poll_enable(sky2->hw->dev[0]);
1100 netif_tx_unlock_bh(dev);
1101 }
1102 #endif
1103
1104 /*
1105 * Allocate an skb for receiving. If the MTU is large enough
1106 * make the skb non-linear with a fragment list of pages.
1107 *
1108 * It appears the hardware has a bug in the FIFO logic that
1109 * cause it to hang if the FIFO gets overrun and the receive buffer
1110 * is not 64 byte aligned. The buffer returned from netdev_alloc_skb is
1111 * aligned except if slab debugging is enabled.
1112 */
1113 static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
1114 {
1115 struct sk_buff *skb;
1116 unsigned long p;
1117 int i;
1118
1119 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + RX_SKB_ALIGN);
1120 if (!skb)
1121 goto nomem;
1122
1123 p = (unsigned long) skb->data;
1124 skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);
1125
1126 for (i = 0; i < sky2->rx_nfrags; i++) {
1127 struct page *page = alloc_page(GFP_ATOMIC);
1128
1129 if (!page)
1130 goto free_partial;
1131 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
1132 }
1133
1134 return skb;
1135 free_partial:
1136 kfree_skb(skb);
1137 nomem:
1138 return NULL;
1139 }
1140
1141 /*
1142 * Allocate and setup receiver buffer pool.
1143 * Normal case this ends up creating one list element for skb
1144 * in the receive ring. Worst case if using large MTU and each
1145 * allocation falls on a different 64 bit region, that results
1146 * in 6 list elements per ring entry.
1147 * One element is used for checksum enable/disable, and one
1148 * extra to avoid wrap.
1149 */
1150 static int sky2_rx_start(struct sky2_port *sky2)
1151 {
1152 struct sky2_hw *hw = sky2->hw;
1153 struct rx_ring_info *re;
1154 unsigned rxq = rxqaddr[sky2->port];
1155 unsigned i, size, space, thresh;
1156
1157 sky2->rx_put = sky2->rx_next = 0;
1158 sky2_qset(hw, rxq);
1159
1160 /* On PCI express lowering the watermark gives better performance */
1161 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1162 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1163
1164 /* These chips have no ram buffer?
1165 * MAC Rx RAM Read is controlled by hardware */
1166 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1167 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1168 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
1169 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
1170
1171 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1172
1173 rx_set_checksum(sky2);
1174
1175 /* Space needed for frame data + headers rounded up */
1176 size = ALIGN(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8)
1177 + 8;
1178
1179 /* Stopping point for hardware truncation */
1180 thresh = (size - 8) / sizeof(u32);
1181
1182 /* Account for overhead of skb - to avoid order > 0 allocation */
1183 space = SKB_DATA_ALIGN(size) + NET_SKB_PAD
1184 + sizeof(struct skb_shared_info);
1185
1186 sky2->rx_nfrags = space >> PAGE_SHIFT;
1187 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1188
1189 if (sky2->rx_nfrags != 0) {
1190 /* Compute residue after pages */
1191 space = sky2->rx_nfrags << PAGE_SHIFT;
1192
1193 if (space < size)
1194 size -= space;
1195 else
1196 size = 0;
1197
1198 /* Optimize to handle small packets and headers */
1199 if (size < copybreak)
1200 size = copybreak;
1201 if (size < ETH_HLEN)
1202 size = ETH_HLEN;
1203 }
1204 sky2->rx_data_size = size;
1205
1206 /* Fill Rx ring */
1207 for (i = 0; i < sky2->rx_pending; i++) {
1208 re = sky2->rx_ring + i;
1209
1210 re->skb = sky2_rx_alloc(sky2);
1211 if (!re->skb)
1212 goto nomem;
1213
1214 sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size);
1215 sky2_rx_submit(sky2, re);
1216 }
1217
1218 /*
1219 * The receiver hangs if it receives frames larger than the
1220 * packet buffer. As a workaround, truncate oversize frames, but
1221 * the register is limited to 9 bits, so if you do frames > 2052
1222 * you better get the MTU right!
1223 */
1224 if (thresh > 0x1ff)
1225 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1226 else {
1227 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1228 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1229 }
1230
1231 /* Tell chip about available buffers */
1232 sky2_put_idx(hw, rxq, sky2->rx_put);
1233 return 0;
1234 nomem:
1235 sky2_rx_clean(sky2);
1236 return -ENOMEM;
1237 }
1238
1239 /* Bring up network interface. */
1240 static int sky2_up(struct net_device *dev)
1241 {
1242 struct sky2_port *sky2 = netdev_priv(dev);
1243 struct sky2_hw *hw = sky2->hw;
1244 unsigned port = sky2->port;
1245 u32 ramsize, imask;
1246 int cap, err = -ENOMEM;
1247 struct net_device *otherdev = hw->dev[sky2->port^1];
1248
1249 /*
1250 * On dual port PCI-X card, there is an problem where status
1251 * can be received out of order due to split transactions
1252 */
1253 if (otherdev && netif_running(otherdev) &&
1254 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1255 struct sky2_port *osky2 = netdev_priv(otherdev);
1256 u16 cmd;
1257
1258 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1259 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1260 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1261
1262 sky2->rx_csum = 0;
1263 osky2->rx_csum = 0;
1264 }
1265
1266 if (netif_msg_ifup(sky2))
1267 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1268
1269 netif_carrier_off(dev);
1270
1271 /* must be power of 2 */
1272 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1273 TX_RING_SIZE *
1274 sizeof(struct sky2_tx_le),
1275 &sky2->tx_le_map);
1276 if (!sky2->tx_le)
1277 goto err_out;
1278
1279 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
1280 GFP_KERNEL);
1281 if (!sky2->tx_ring)
1282 goto err_out;
1283 sky2->tx_prod = sky2->tx_cons = 0;
1284
1285 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1286 &sky2->rx_le_map);
1287 if (!sky2->rx_le)
1288 goto err_out;
1289 memset(sky2->rx_le, 0, RX_LE_BYTES);
1290
1291 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
1292 GFP_KERNEL);
1293 if (!sky2->rx_ring)
1294 goto err_out;
1295
1296 sky2_phy_power(hw, port, 1);
1297
1298 sky2_mac_init(hw, port);
1299
1300 /* Register is number of 4K blocks on internal RAM buffer. */
1301 ramsize = sky2_read8(hw, B2_E_0) * 4;
1302 printk(KERN_INFO PFX "%s: ram buffer %dK\n", dev->name, ramsize);
1303
1304 if (ramsize > 0) {
1305 u32 rxspace;
1306
1307 if (ramsize < 16)
1308 rxspace = ramsize / 2;
1309 else
1310 rxspace = 8 + (2*(ramsize - 16))/3;
1311
1312 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1313 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1314
1315 /* Make sure SyncQ is disabled */
1316 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1317 RB_RST_SET);
1318 }
1319
1320 sky2_qset(hw, txqaddr[port]);
1321
1322 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1323 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1324 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1325
1326 /* Set almost empty threshold */
1327 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1328 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
1329 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
1330
1331 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1332 TX_RING_SIZE - 1);
1333
1334 err = sky2_rx_start(sky2);
1335 if (err)
1336 goto err_out;
1337
1338 /* Enable interrupts from phy/mac for port */
1339 imask = sky2_read32(hw, B0_IMSK);
1340 imask |= portirq_msk[port];
1341 sky2_write32(hw, B0_IMSK, imask);
1342
1343 return 0;
1344
1345 err_out:
1346 if (sky2->rx_le) {
1347 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1348 sky2->rx_le, sky2->rx_le_map);
1349 sky2->rx_le = NULL;
1350 }
1351 if (sky2->tx_le) {
1352 pci_free_consistent(hw->pdev,
1353 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1354 sky2->tx_le, sky2->tx_le_map);
1355 sky2->tx_le = NULL;
1356 }
1357 kfree(sky2->tx_ring);
1358 kfree(sky2->rx_ring);
1359
1360 sky2->tx_ring = NULL;
1361 sky2->rx_ring = NULL;
1362 return err;
1363 }
1364
1365 /* Modular subtraction in ring */
1366 static inline int tx_dist(unsigned tail, unsigned head)
1367 {
1368 return (head - tail) & (TX_RING_SIZE - 1);
1369 }
1370
1371 /* Number of list elements available for next tx */
1372 static inline int tx_avail(const struct sky2_port *sky2)
1373 {
1374 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
1375 }
1376
1377 /* Estimate of number of transmit list elements required */
1378 static unsigned tx_le_req(const struct sk_buff *skb)
1379 {
1380 unsigned count;
1381
1382 count = sizeof(dma_addr_t) / sizeof(u32);
1383 count += skb_shinfo(skb)->nr_frags * count;
1384
1385 if (skb_is_gso(skb))
1386 ++count;
1387
1388 if (skb->ip_summed == CHECKSUM_PARTIAL)
1389 ++count;
1390
1391 return count;
1392 }
1393
1394 /*
1395 * Put one packet in ring for transmit.
1396 * A single packet can generate multiple list elements, and
1397 * the number of ring elements will probably be less than the number
1398 * of list elements used.
1399 */
1400 static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1401 {
1402 struct sky2_port *sky2 = netdev_priv(dev);
1403 struct sky2_hw *hw = sky2->hw;
1404 struct sky2_tx_le *le = NULL;
1405 struct tx_ring_info *re;
1406 unsigned i, len;
1407 dma_addr_t mapping;
1408 u32 addr64;
1409 u16 mss;
1410 u8 ctrl;
1411
1412 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1413 return NETDEV_TX_BUSY;
1414
1415 if (unlikely(netif_msg_tx_queued(sky2)))
1416 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1417 dev->name, sky2->tx_prod, skb->len);
1418
1419 len = skb_headlen(skb);
1420 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1421 addr64 = high32(mapping);
1422
1423 /* Send high bits if changed or crosses boundary */
1424 if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
1425 le = get_tx_le(sky2);
1426 le->addr = cpu_to_le32(addr64);
1427 le->opcode = OP_ADDR64 | HW_OWNER;
1428 sky2->tx_addr64 = high32(mapping + len);
1429 }
1430
1431 /* Check for TCP Segmentation Offload */
1432 mss = skb_shinfo(skb)->gso_size;
1433 if (mss != 0) {
1434 if (hw->chip_id != CHIP_ID_YUKON_EX)
1435 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1436
1437 if (mss != sky2->tx_last_mss) {
1438 le = get_tx_le(sky2);
1439 le->addr = cpu_to_le32(mss);
1440 if (hw->chip_id == CHIP_ID_YUKON_EX)
1441 le->opcode = OP_MSS | HW_OWNER;
1442 else
1443 le->opcode = OP_LRGLEN | HW_OWNER;
1444 sky2->tx_last_mss = mss;
1445 }
1446 }
1447
1448 ctrl = 0;
1449 #ifdef SKY2_VLAN_TAG_USED
1450 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1451 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1452 if (!le) {
1453 le = get_tx_le(sky2);
1454 le->addr = 0;
1455 le->opcode = OP_VLAN|HW_OWNER;
1456 } else
1457 le->opcode |= OP_VLAN;
1458 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1459 ctrl |= INS_VLAN;
1460 }
1461 #endif
1462
1463 /* Handle TCP checksum offload */
1464 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1465 /* On Yukon EX (some versions) encoding change. */
1466 if (hw->chip_id == CHIP_ID_YUKON_EX
1467 && hw->chip_rev != CHIP_REV_YU_EX_B0)
1468 ctrl |= CALSUM; /* auto checksum */
1469 else {
1470 const unsigned offset = skb_transport_offset(skb);
1471 u32 tcpsum;
1472
1473 tcpsum = offset << 16; /* sum start */
1474 tcpsum |= offset + skb->csum_offset; /* sum write */
1475
1476 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1477 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1478 ctrl |= UDPTCP;
1479
1480 if (tcpsum != sky2->tx_tcpsum) {
1481 sky2->tx_tcpsum = tcpsum;
1482
1483 le = get_tx_le(sky2);
1484 le->addr = cpu_to_le32(tcpsum);
1485 le->length = 0; /* initial checksum value */
1486 le->ctrl = 1; /* one packet */
1487 le->opcode = OP_TCPLISW | HW_OWNER;
1488 }
1489 }
1490 }
1491
1492 le = get_tx_le(sky2);
1493 le->addr = cpu_to_le32((u32) mapping);
1494 le->length = cpu_to_le16(len);
1495 le->ctrl = ctrl;
1496 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1497
1498 re = tx_le_re(sky2, le);
1499 re->skb = skb;
1500 pci_unmap_addr_set(re, mapaddr, mapping);
1501 pci_unmap_len_set(re, maplen, len);
1502
1503 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1504 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1505
1506 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1507 frag->size, PCI_DMA_TODEVICE);
1508 addr64 = high32(mapping);
1509 if (addr64 != sky2->tx_addr64) {
1510 le = get_tx_le(sky2);
1511 le->addr = cpu_to_le32(addr64);
1512 le->ctrl = 0;
1513 le->opcode = OP_ADDR64 | HW_OWNER;
1514 sky2->tx_addr64 = addr64;
1515 }
1516
1517 le = get_tx_le(sky2);
1518 le->addr = cpu_to_le32((u32) mapping);
1519 le->length = cpu_to_le16(frag->size);
1520 le->ctrl = ctrl;
1521 le->opcode = OP_BUFFER | HW_OWNER;
1522
1523 re = tx_le_re(sky2, le);
1524 re->skb = skb;
1525 pci_unmap_addr_set(re, mapaddr, mapping);
1526 pci_unmap_len_set(re, maplen, frag->size);
1527 }
1528
1529 le->ctrl |= EOP;
1530
1531 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1532 netif_stop_queue(dev);
1533
1534 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
1535
1536 dev->trans_start = jiffies;
1537 return NETDEV_TX_OK;
1538 }
1539
1540 /*
1541 * Free ring elements from starting at tx_cons until "done"
1542 *
1543 * NB: the hardware will tell us about partial completion of multi-part
1544 * buffers so make sure not to free skb to early.
1545 */
1546 static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1547 {
1548 struct net_device *dev = sky2->netdev;
1549 struct pci_dev *pdev = sky2->hw->pdev;
1550 unsigned idx;
1551
1552 BUG_ON(done >= TX_RING_SIZE);
1553
1554 for (idx = sky2->tx_cons; idx != done;
1555 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1556 struct sky2_tx_le *le = sky2->tx_le + idx;
1557 struct tx_ring_info *re = sky2->tx_ring + idx;
1558
1559 switch(le->opcode & ~HW_OWNER) {
1560 case OP_LARGESEND:
1561 case OP_PACKET:
1562 pci_unmap_single(pdev,
1563 pci_unmap_addr(re, mapaddr),
1564 pci_unmap_len(re, maplen),
1565 PCI_DMA_TODEVICE);
1566 break;
1567 case OP_BUFFER:
1568 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1569 pci_unmap_len(re, maplen),
1570 PCI_DMA_TODEVICE);
1571 break;
1572 }
1573
1574 if (le->ctrl & EOP) {
1575 if (unlikely(netif_msg_tx_done(sky2)))
1576 printk(KERN_DEBUG "%s: tx done %u\n",
1577 dev->name, idx);
1578
1579 sky2->net_stats.tx_packets++;
1580 sky2->net_stats.tx_bytes += re->skb->len;
1581
1582 dev_kfree_skb_any(re->skb);
1583 sky2->tx_next = RING_NEXT(idx, TX_RING_SIZE);
1584 }
1585 }
1586
1587 sky2->tx_cons = idx;
1588 smp_mb();
1589
1590 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
1591 netif_wake_queue(dev);
1592 }
1593
1594 /* Cleanup all untransmitted buffers, assume transmitter not running */
1595 static void sky2_tx_clean(struct net_device *dev)
1596 {
1597 struct sky2_port *sky2 = netdev_priv(dev);
1598
1599 netif_tx_lock_bh(dev);
1600 sky2_tx_complete(sky2, sky2->tx_prod);
1601 netif_tx_unlock_bh(dev);
1602 }
1603
1604 /* Network shutdown */
1605 static int sky2_down(struct net_device *dev)
1606 {
1607 struct sky2_port *sky2 = netdev_priv(dev);
1608 struct sky2_hw *hw = sky2->hw;
1609 unsigned port = sky2->port;
1610 u16 ctrl;
1611 u32 imask;
1612
1613 /* Never really got started! */
1614 if (!sky2->tx_le)
1615 return 0;
1616
1617 if (netif_msg_ifdown(sky2))
1618 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1619
1620 /* Stop more packets from being queued */
1621 netif_stop_queue(dev);
1622
1623 /* Disable port IRQ */
1624 imask = sky2_read32(hw, B0_IMSK);
1625 imask &= ~portirq_msk[port];
1626 sky2_write32(hw, B0_IMSK, imask);
1627
1628 sky2_gmac_reset(hw, port);
1629
1630 /* Stop transmitter */
1631 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1632 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1633
1634 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1635 RB_RST_SET | RB_DIS_OP_MD);
1636
1637 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1638 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
1639 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1640
1641 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1642
1643 /* Workaround shared GMAC reset */
1644 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1645 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1646 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1647
1648 /* Disable Force Sync bit and Enable Alloc bit */
1649 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1650 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1651
1652 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1653 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1654 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1655
1656 /* Reset the PCI FIFO of the async Tx queue */
1657 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1658 BMU_RST_SET | BMU_FIFO_RST);
1659
1660 /* Reset the Tx prefetch units */
1661 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1662 PREF_UNIT_RST_SET);
1663
1664 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1665
1666 sky2_rx_stop(sky2);
1667
1668 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1669 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1670
1671 sky2_phy_power(hw, port, 0);
1672
1673 netif_carrier_off(dev);
1674
1675 /* turn off LED's */
1676 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1677
1678 synchronize_irq(hw->pdev->irq);
1679
1680 sky2_tx_clean(dev);
1681 sky2_rx_clean(sky2);
1682
1683 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1684 sky2->rx_le, sky2->rx_le_map);
1685 kfree(sky2->rx_ring);
1686
1687 pci_free_consistent(hw->pdev,
1688 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1689 sky2->tx_le, sky2->tx_le_map);
1690 kfree(sky2->tx_ring);
1691
1692 sky2->tx_le = NULL;
1693 sky2->rx_le = NULL;
1694
1695 sky2->rx_ring = NULL;
1696 sky2->tx_ring = NULL;
1697
1698 return 0;
1699 }
1700
1701 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1702 {
1703 if (!sky2_is_copper(hw))
1704 return SPEED_1000;
1705
1706 if (hw->chip_id == CHIP_ID_YUKON_FE)
1707 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1708
1709 switch (aux & PHY_M_PS_SPEED_MSK) {
1710 case PHY_M_PS_SPEED_1000:
1711 return SPEED_1000;
1712 case PHY_M_PS_SPEED_100:
1713 return SPEED_100;
1714 default:
1715 return SPEED_10;
1716 }
1717 }
1718
1719 static void sky2_link_up(struct sky2_port *sky2)
1720 {
1721 struct sky2_hw *hw = sky2->hw;
1722 unsigned port = sky2->port;
1723 u16 reg;
1724 static const char *fc_name[] = {
1725 [FC_NONE] = "none",
1726 [FC_TX] = "tx",
1727 [FC_RX] = "rx",
1728 [FC_BOTH] = "both",
1729 };
1730
1731 /* enable Rx/Tx */
1732 reg = gma_read16(hw, port, GM_GP_CTRL);
1733 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1734 gma_write16(hw, port, GM_GP_CTRL, reg);
1735
1736 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1737
1738 netif_carrier_on(sky2->netdev);
1739
1740 /* Turn on link LED */
1741 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
1742 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1743
1744 if (hw->chip_id == CHIP_ID_YUKON_XL
1745 || hw->chip_id == CHIP_ID_YUKON_EC_U
1746 || hw->chip_id == CHIP_ID_YUKON_EX) {
1747 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
1748 u16 led = PHY_M_LEDC_LOS_CTRL(1); /* link active */
1749
1750 switch(sky2->speed) {
1751 case SPEED_10:
1752 led |= PHY_M_LEDC_INIT_CTRL(7);
1753 break;
1754
1755 case SPEED_100:
1756 led |= PHY_M_LEDC_STA1_CTRL(7);
1757 break;
1758
1759 case SPEED_1000:
1760 led |= PHY_M_LEDC_STA0_CTRL(7);
1761 break;
1762 }
1763
1764 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
1765 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, led);
1766 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1767 }
1768
1769 if (netif_msg_link(sky2))
1770 printk(KERN_INFO PFX
1771 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1772 sky2->netdev->name, sky2->speed,
1773 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1774 fc_name[sky2->flow_status]);
1775 }
1776
1777 static void sky2_link_down(struct sky2_port *sky2)
1778 {
1779 struct sky2_hw *hw = sky2->hw;
1780 unsigned port = sky2->port;
1781 u16 reg;
1782
1783 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1784
1785 reg = gma_read16(hw, port, GM_GP_CTRL);
1786 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1787 gma_write16(hw, port, GM_GP_CTRL, reg);
1788
1789 netif_carrier_off(sky2->netdev);
1790
1791 /* Turn on link LED */
1792 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1793
1794 if (netif_msg_link(sky2))
1795 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1796
1797 sky2_phy_init(hw, port);
1798 }
1799
1800 static enum flow_control sky2_flow(int rx, int tx)
1801 {
1802 if (rx)
1803 return tx ? FC_BOTH : FC_RX;
1804 else
1805 return tx ? FC_TX : FC_NONE;
1806 }
1807
1808 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1809 {
1810 struct sky2_hw *hw = sky2->hw;
1811 unsigned port = sky2->port;
1812 u16 advert, lpa;
1813
1814 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
1815 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1816 if (lpa & PHY_M_AN_RF) {
1817 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1818 return -1;
1819 }
1820
1821 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1822 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1823 sky2->netdev->name);
1824 return -1;
1825 }
1826
1827 sky2->speed = sky2_phy_speed(hw, aux);
1828 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1829
1830 /* Since the pause result bits seem to in different positions on
1831 * different chips. look at registers.
1832 */
1833 if (!sky2_is_copper(hw)) {
1834 /* Shift for bits in fiber PHY */
1835 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
1836 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
1837
1838 if (advert & ADVERTISE_1000XPAUSE)
1839 advert |= ADVERTISE_PAUSE_CAP;
1840 if (advert & ADVERTISE_1000XPSE_ASYM)
1841 advert |= ADVERTISE_PAUSE_ASYM;
1842 if (lpa & LPA_1000XPAUSE)
1843 lpa |= LPA_PAUSE_CAP;
1844 if (lpa & LPA_1000XPAUSE_ASYM)
1845 lpa |= LPA_PAUSE_ASYM;
1846 }
1847
1848 sky2->flow_status = FC_NONE;
1849 if (advert & ADVERTISE_PAUSE_CAP) {
1850 if (lpa & LPA_PAUSE_CAP)
1851 sky2->flow_status = FC_BOTH;
1852 else if (advert & ADVERTISE_PAUSE_ASYM)
1853 sky2->flow_status = FC_RX;
1854 } else if (advert & ADVERTISE_PAUSE_ASYM) {
1855 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
1856 sky2->flow_status = FC_TX;
1857 }
1858
1859 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
1860 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
1861 sky2->flow_status = FC_NONE;
1862
1863 if (sky2->flow_status & FC_TX)
1864 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1865 else
1866 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1867
1868 return 0;
1869 }
1870
1871 /* Interrupt from PHY */
1872 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
1873 {
1874 struct net_device *dev = hw->dev[port];
1875 struct sky2_port *sky2 = netdev_priv(dev);
1876 u16 istatus, phystat;
1877
1878 if (!netif_running(dev))
1879 return;
1880
1881 spin_lock(&sky2->phy_lock);
1882 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1883 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1884
1885 if (netif_msg_intr(sky2))
1886 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1887 sky2->netdev->name, istatus, phystat);
1888
1889 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
1890 if (sky2_autoneg_done(sky2, phystat) == 0)
1891 sky2_link_up(sky2);
1892 goto out;
1893 }
1894
1895 if (istatus & PHY_M_IS_LSP_CHANGE)
1896 sky2->speed = sky2_phy_speed(hw, phystat);
1897
1898 if (istatus & PHY_M_IS_DUP_CHANGE)
1899 sky2->duplex =
1900 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1901
1902 if (istatus & PHY_M_IS_LST_CHANGE) {
1903 if (phystat & PHY_M_PS_LINK_UP)
1904 sky2_link_up(sky2);
1905 else
1906 sky2_link_down(sky2);
1907 }
1908 out:
1909 spin_unlock(&sky2->phy_lock);
1910 }
1911
1912 /* Transmit timeout is only called if we are running, carrier is up
1913 * and tx queue is full (stopped).
1914 */
1915 static void sky2_tx_timeout(struct net_device *dev)
1916 {
1917 struct sky2_port *sky2 = netdev_priv(dev);
1918 struct sky2_hw *hw = sky2->hw;
1919
1920 if (netif_msg_timer(sky2))
1921 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1922
1923 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
1924 dev->name, sky2->tx_cons, sky2->tx_prod,
1925 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
1926 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
1927
1928 /* can't restart safely under softirq */
1929 schedule_work(&hw->restart_work);
1930 }
1931
1932 static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1933 {
1934 struct sky2_port *sky2 = netdev_priv(dev);
1935 struct sky2_hw *hw = sky2->hw;
1936 unsigned port = sky2->port;
1937 int err;
1938 u16 ctl, mode;
1939 u32 imask;
1940
1941 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1942 return -EINVAL;
1943
1944 if (new_mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_FE)
1945 return -EINVAL;
1946
1947 if (!netif_running(dev)) {
1948 dev->mtu = new_mtu;
1949 return 0;
1950 }
1951
1952 imask = sky2_read32(hw, B0_IMSK);
1953 sky2_write32(hw, B0_IMSK, 0);
1954
1955 dev->trans_start = jiffies; /* prevent tx timeout */
1956 netif_stop_queue(dev);
1957 netif_poll_disable(hw->dev[0]);
1958
1959 synchronize_irq(hw->pdev->irq);
1960
1961 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX)
1962 sky2_set_tx_stfwd(hw, port);
1963
1964 ctl = gma_read16(hw, port, GM_GP_CTRL);
1965 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
1966 sky2_rx_stop(sky2);
1967 sky2_rx_clean(sky2);
1968
1969 dev->mtu = new_mtu;
1970
1971 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1972 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1973
1974 if (dev->mtu > ETH_DATA_LEN)
1975 mode |= GM_SMOD_JUMBO_ENA;
1976
1977 gma_write16(hw, port, GM_SERIAL_MODE, mode);
1978
1979 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
1980
1981 err = sky2_rx_start(sky2);
1982 sky2_write32(hw, B0_IMSK, imask);
1983
1984 if (err)
1985 dev_close(dev);
1986 else {
1987 gma_write16(hw, port, GM_GP_CTRL, ctl);
1988
1989 netif_poll_enable(hw->dev[0]);
1990 netif_wake_queue(dev);
1991 }
1992
1993 return err;
1994 }
1995
1996 /* For small just reuse existing skb for next receive */
1997 static struct sk_buff *receive_copy(struct sky2_port *sky2,
1998 const struct rx_ring_info *re,
1999 unsigned length)
2000 {
2001 struct sk_buff *skb;
2002
2003 skb = netdev_alloc_skb(sky2->netdev, length + 2);
2004 if (likely(skb)) {
2005 skb_reserve(skb, 2);
2006 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2007 length, PCI_DMA_FROMDEVICE);
2008 skb_copy_from_linear_data(re->skb, skb->data, length);
2009 skb->ip_summed = re->skb->ip_summed;
2010 skb->csum = re->skb->csum;
2011 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2012 length, PCI_DMA_FROMDEVICE);
2013 re->skb->ip_summed = CHECKSUM_NONE;
2014 skb_put(skb, length);
2015 }
2016 return skb;
2017 }
2018
2019 /* Adjust length of skb with fragments to match received data */
2020 static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2021 unsigned int length)
2022 {
2023 int i, num_frags;
2024 unsigned int size;
2025
2026 /* put header into skb */
2027 size = min(length, hdr_space);
2028 skb->tail += size;
2029 skb->len += size;
2030 length -= size;
2031
2032 num_frags = skb_shinfo(skb)->nr_frags;
2033 for (i = 0; i < num_frags; i++) {
2034 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2035
2036 if (length == 0) {
2037 /* don't need this page */
2038 __free_page(frag->page);
2039 --skb_shinfo(skb)->nr_frags;
2040 } else {
2041 size = min(length, (unsigned) PAGE_SIZE);
2042
2043 frag->size = size;
2044 skb->data_len += size;
2045 skb->truesize += size;
2046 skb->len += size;
2047 length -= size;
2048 }
2049 }
2050 }
2051
2052 /* Normal packet - take skb from ring element and put in a new one */
2053 static struct sk_buff *receive_new(struct sky2_port *sky2,
2054 struct rx_ring_info *re,
2055 unsigned int length)
2056 {
2057 struct sk_buff *skb, *nskb;
2058 unsigned hdr_space = sky2->rx_data_size;
2059
2060 pr_debug(PFX "receive new length=%d\n", length);
2061
2062 /* Don't be tricky about reusing pages (yet) */
2063 nskb = sky2_rx_alloc(sky2);
2064 if (unlikely(!nskb))
2065 return NULL;
2066
2067 skb = re->skb;
2068 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2069
2070 prefetch(skb->data);
2071 re->skb = nskb;
2072 sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space);
2073
2074 if (skb_shinfo(skb)->nr_frags)
2075 skb_put_frags(skb, hdr_space, length);
2076 else
2077 skb_put(skb, length);
2078 return skb;
2079 }
2080
2081 /*
2082 * Receive one packet.
2083 * For larger packets, get new buffer.
2084 */
2085 static struct sk_buff *sky2_receive(struct net_device *dev,
2086 u16 length, u32 status)
2087 {
2088 struct sky2_port *sky2 = netdev_priv(dev);
2089 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
2090 struct sk_buff *skb = NULL;
2091
2092 if (unlikely(netif_msg_rx_status(sky2)))
2093 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
2094 dev->name, sky2->rx_next, status, length);
2095
2096 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
2097 prefetch(sky2->rx_ring + sky2->rx_next);
2098
2099 if (status & GMR_FS_ANY_ERR)
2100 goto error;
2101
2102 if (!(status & GMR_FS_RX_OK))
2103 goto resubmit;
2104
2105 if (length < copybreak)
2106 skb = receive_copy(sky2, re, length);
2107 else
2108 skb = receive_new(sky2, re, length);
2109 resubmit:
2110 sky2_rx_submit(sky2, re);
2111
2112 return skb;
2113
2114 error:
2115 ++sky2->net_stats.rx_errors;
2116 if (status & GMR_FS_RX_FF_OV) {
2117 sky2->net_stats.rx_over_errors++;
2118 goto resubmit;
2119 }
2120
2121 if (netif_msg_rx_err(sky2) && net_ratelimit())
2122 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
2123 dev->name, status, length);
2124
2125 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
2126 sky2->net_stats.rx_length_errors++;
2127 if (status & GMR_FS_FRAGMENT)
2128 sky2->net_stats.rx_frame_errors++;
2129 if (status & GMR_FS_CRC_ERR)
2130 sky2->net_stats.rx_crc_errors++;
2131
2132 goto resubmit;
2133 }
2134
2135 /* Transmit complete */
2136 static inline void sky2_tx_done(struct net_device *dev, u16 last)
2137 {
2138 struct sky2_port *sky2 = netdev_priv(dev);
2139
2140 if (netif_running(dev)) {
2141 netif_tx_lock(dev);
2142 sky2_tx_complete(sky2, last);
2143 netif_tx_unlock(dev);
2144 }
2145 }
2146
2147 /* Process status response ring */
2148 static int sky2_status_intr(struct sky2_hw *hw, int to_do)
2149 {
2150 struct sky2_port *sky2;
2151 int work_done = 0;
2152 unsigned buf_write[2] = { 0, 0 };
2153 u16 hwidx = sky2_read16(hw, STAT_PUT_IDX);
2154
2155 rmb();
2156
2157 while (hw->st_idx != hwidx) {
2158 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2159 unsigned port = le->css & CSS_LINK_BIT;
2160 struct net_device *dev;
2161 struct sk_buff *skb;
2162 u32 status;
2163 u16 length;
2164
2165 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
2166
2167 dev = hw->dev[port];
2168 sky2 = netdev_priv(dev);
2169 length = le16_to_cpu(le->length);
2170 status = le32_to_cpu(le->status);
2171
2172 switch (le->opcode & ~HW_OWNER) {
2173 case OP_RXSTAT:
2174 skb = sky2_receive(dev, length, status);
2175 if (unlikely(!skb)) {
2176 sky2->net_stats.rx_dropped++;
2177 goto force_update;
2178 }
2179
2180 /* This chip reports checksum status differently */
2181 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2182 if (sky2->rx_csum &&
2183 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2184 (le->css & CSS_TCPUDPCSOK))
2185 skb->ip_summed = CHECKSUM_UNNECESSARY;
2186 else
2187 skb->ip_summed = CHECKSUM_NONE;
2188 }
2189
2190 skb->protocol = eth_type_trans(skb, dev);
2191 sky2->net_stats.rx_packets++;
2192 sky2->net_stats.rx_bytes += skb->len;
2193 dev->last_rx = jiffies;
2194
2195 #ifdef SKY2_VLAN_TAG_USED
2196 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2197 vlan_hwaccel_receive_skb(skb,
2198 sky2->vlgrp,
2199 be16_to_cpu(sky2->rx_tag));
2200 } else
2201 #endif
2202 netif_receive_skb(skb);
2203
2204 /* Update receiver after 16 frames */
2205 if (++buf_write[port] == RX_BUF_WRITE) {
2206 force_update:
2207 sky2_put_idx(hw, rxqaddr[port], sky2->rx_put);
2208 buf_write[port] = 0;
2209 }
2210
2211 /* Stop after net poll weight */
2212 if (++work_done >= to_do)
2213 goto exit_loop;
2214 break;
2215
2216 #ifdef SKY2_VLAN_TAG_USED
2217 case OP_RXVLAN:
2218 sky2->rx_tag = length;
2219 break;
2220
2221 case OP_RXCHKSVLAN:
2222 sky2->rx_tag = length;
2223 /* fall through */
2224 #endif
2225 case OP_RXCHKS:
2226 if (!sky2->rx_csum)
2227 break;
2228
2229 if (hw->chip_id == CHIP_ID_YUKON_EX)
2230 break;
2231
2232 /* Both checksum counters are programmed to start at
2233 * the same offset, so unless there is a problem they
2234 * should match. This failure is an early indication that
2235 * hardware receive checksumming won't work.
2236 */
2237 if (likely(status >> 16 == (status & 0xffff))) {
2238 skb = sky2->rx_ring[sky2->rx_next].skb;
2239 skb->ip_summed = CHECKSUM_COMPLETE;
2240 skb->csum = status & 0xffff;
2241 } else {
2242 printk(KERN_NOTICE PFX "%s: hardware receive "
2243 "checksum problem (status = %#x)\n",
2244 dev->name, status);
2245 sky2->rx_csum = 0;
2246 sky2_write32(sky2->hw,
2247 Q_ADDR(rxqaddr[port], Q_CSR),
2248 BMU_DIS_RX_CHKSUM);
2249 }
2250 break;
2251
2252 case OP_TXINDEXLE:
2253 /* TX index reports status for both ports */
2254 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2255 sky2_tx_done(hw->dev[0], status & 0xfff);
2256 if (hw->dev[1])
2257 sky2_tx_done(hw->dev[1],
2258 ((status >> 24) & 0xff)
2259 | (u16)(length & 0xf) << 8);
2260 break;
2261
2262 default:
2263 if (net_ratelimit())
2264 printk(KERN_WARNING PFX
2265 "unknown status opcode 0x%x\n", le->opcode);
2266 goto exit_loop;
2267 }
2268 }
2269
2270 /* Fully processed status ring so clear irq */
2271 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2272 mmiowb();
2273
2274 exit_loop:
2275 if (buf_write[0]) {
2276 sky2 = netdev_priv(hw->dev[0]);
2277 sky2_put_idx(hw, Q_R1, sky2->rx_put);
2278 }
2279
2280 if (buf_write[1]) {
2281 sky2 = netdev_priv(hw->dev[1]);
2282 sky2_put_idx(hw, Q_R2, sky2->rx_put);
2283 }
2284
2285 return work_done;
2286 }
2287
2288 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2289 {
2290 struct net_device *dev = hw->dev[port];
2291
2292 if (net_ratelimit())
2293 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2294 dev->name, status);
2295
2296 if (status & Y2_IS_PAR_RD1) {
2297 if (net_ratelimit())
2298 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2299 dev->name);
2300 /* Clear IRQ */
2301 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2302 }
2303
2304 if (status & Y2_IS_PAR_WR1) {
2305 if (net_ratelimit())
2306 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2307 dev->name);
2308
2309 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2310 }
2311
2312 if (status & Y2_IS_PAR_MAC1) {
2313 if (net_ratelimit())
2314 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
2315 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2316 }
2317
2318 if (status & Y2_IS_PAR_RX1) {
2319 if (net_ratelimit())
2320 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
2321 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2322 }
2323
2324 if (status & Y2_IS_TCP_TXA1) {
2325 if (net_ratelimit())
2326 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2327 dev->name);
2328 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2329 }
2330 }
2331
2332 static void sky2_hw_intr(struct sky2_hw *hw)
2333 {
2334 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2335
2336 if (status & Y2_IS_TIST_OV)
2337 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2338
2339 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
2340 u16 pci_err;
2341
2342 pci_err = sky2_pci_read16(hw, PCI_STATUS);
2343 if (net_ratelimit())
2344 dev_err(&hw->pdev->dev, "PCI hardware error (0x%x)\n",
2345 pci_err);
2346
2347 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2348 sky2_pci_write16(hw, PCI_STATUS,
2349 pci_err | PCI_STATUS_ERROR_BITS);
2350 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2351 }
2352
2353 if (status & Y2_IS_PCI_EXP) {
2354 /* PCI-Express uncorrectable Error occurred */
2355 u32 pex_err;
2356
2357 pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT);
2358
2359 if (net_ratelimit())
2360 dev_err(&hw->pdev->dev, "PCI Express error (0x%x)\n",
2361 pex_err);
2362
2363 /* clear the interrupt */
2364 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2365 sky2_pci_write32(hw, PEX_UNC_ERR_STAT,
2366 0xffffffffUL);
2367 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2368
2369 if (pex_err & PEX_FATAL_ERRORS) {
2370 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2371 hwmsk &= ~Y2_IS_PCI_EXP;
2372 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2373 }
2374 }
2375
2376 if (status & Y2_HWE_L1_MASK)
2377 sky2_hw_error(hw, 0, status);
2378 status >>= 8;
2379 if (status & Y2_HWE_L1_MASK)
2380 sky2_hw_error(hw, 1, status);
2381 }
2382
2383 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2384 {
2385 struct net_device *dev = hw->dev[port];
2386 struct sky2_port *sky2 = netdev_priv(dev);
2387 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2388
2389 if (netif_msg_intr(sky2))
2390 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2391 dev->name, status);
2392
2393 if (status & GM_IS_RX_CO_OV)
2394 gma_read16(hw, port, GM_RX_IRQ_SRC);
2395
2396 if (status & GM_IS_TX_CO_OV)
2397 gma_read16(hw, port, GM_TX_IRQ_SRC);
2398
2399 if (status & GM_IS_RX_FF_OR) {
2400 ++sky2->net_stats.rx_fifo_errors;
2401 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2402 }
2403
2404 if (status & GM_IS_TX_FF_UR) {
2405 ++sky2->net_stats.tx_fifo_errors;
2406 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2407 }
2408 }
2409
2410 /* This should never happen it is a bug. */
2411 static void sky2_le_error(struct sky2_hw *hw, unsigned port,
2412 u16 q, unsigned ring_size)
2413 {
2414 struct net_device *dev = hw->dev[port];
2415 struct sky2_port *sky2 = netdev_priv(dev);
2416 unsigned idx;
2417 const u64 *le = (q == Q_R1 || q == Q_R2)
2418 ? (u64 *) sky2->rx_le : (u64 *) sky2->tx_le;
2419
2420 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2421 printk(KERN_ERR PFX "%s: descriptor error q=%#x get=%u [%llx] put=%u\n",
2422 dev->name, (unsigned) q, idx, (unsigned long long) le[idx],
2423 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
2424
2425 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
2426 }
2427
2428 /* If idle then force a fake soft NAPI poll once a second
2429 * to work around cases where sharing an edge triggered interrupt.
2430 */
2431 static inline void sky2_idle_start(struct sky2_hw *hw)
2432 {
2433 if (idle_timeout > 0)
2434 mod_timer(&hw->idle_timer,
2435 jiffies + msecs_to_jiffies(idle_timeout));
2436 }
2437
2438 static void sky2_idle(unsigned long arg)
2439 {
2440 struct sky2_hw *hw = (struct sky2_hw *) arg;
2441 struct net_device *dev = hw->dev[0];
2442
2443 if (__netif_rx_schedule_prep(dev))
2444 __netif_rx_schedule(dev);
2445
2446 mod_timer(&hw->idle_timer, jiffies + msecs_to_jiffies(idle_timeout));
2447 }
2448
2449 /* Hardware/software error handling */
2450 static void sky2_err_intr(struct sky2_hw *hw, u32 status)
2451 {
2452 if (net_ratelimit())
2453 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
2454
2455 if (status & Y2_IS_HW_ERR)
2456 sky2_hw_intr(hw);
2457
2458 if (status & Y2_IS_IRQ_MAC1)
2459 sky2_mac_intr(hw, 0);
2460
2461 if (status & Y2_IS_IRQ_MAC2)
2462 sky2_mac_intr(hw, 1);
2463
2464 if (status & Y2_IS_CHK_RX1)
2465 sky2_le_error(hw, 0, Q_R1, RX_LE_SIZE);
2466
2467 if (status & Y2_IS_CHK_RX2)
2468 sky2_le_error(hw, 1, Q_R2, RX_LE_SIZE);
2469
2470 if (status & Y2_IS_CHK_TXA1)
2471 sky2_le_error(hw, 0, Q_XA1, TX_RING_SIZE);
2472
2473 if (status & Y2_IS_CHK_TXA2)
2474 sky2_le_error(hw, 1, Q_XA2, TX_RING_SIZE);
2475 }
2476
2477 static int sky2_poll(struct net_device *dev0, int *budget)
2478 {
2479 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
2480 int work_limit = min(dev0->quota, *budget);
2481 int work_done = 0;
2482 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
2483
2484 if (unlikely(status & Y2_IS_ERROR))
2485 sky2_err_intr(hw, status);
2486
2487 if (status & Y2_IS_IRQ_PHY1)
2488 sky2_phy_intr(hw, 0);
2489
2490 if (status & Y2_IS_IRQ_PHY2)
2491 sky2_phy_intr(hw, 1);
2492
2493 work_done = sky2_status_intr(hw, work_limit);
2494 if (work_done < work_limit) {
2495 /* Bug/Errata workaround?
2496 * Need to kick the TX irq moderation timer.
2497 */
2498 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_START) {
2499 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2500 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2501 }
2502 netif_rx_complete(dev0);
2503
2504 /* end of interrupt, re-enables also acts as I/O synchronization */
2505 sky2_read32(hw, B0_Y2_SP_LISR);
2506 return 0;
2507 } else {
2508 *budget -= work_done;
2509 dev0->quota -= work_done;
2510 return 1;
2511 }
2512 }
2513
2514 static irqreturn_t sky2_intr(int irq, void *dev_id)
2515 {
2516 struct sky2_hw *hw = dev_id;
2517 struct net_device *dev0 = hw->dev[0];
2518 u32 status;
2519
2520 /* Reading this mask interrupts as side effect */
2521 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2522 if (status == 0 || status == ~0)
2523 return IRQ_NONE;
2524
2525 prefetch(&hw->st_le[hw->st_idx]);
2526 if (likely(__netif_rx_schedule_prep(dev0)))
2527 __netif_rx_schedule(dev0);
2528
2529 return IRQ_HANDLED;
2530 }
2531
2532 #ifdef CONFIG_NET_POLL_CONTROLLER
2533 static void sky2_netpoll(struct net_device *dev)
2534 {
2535 struct sky2_port *sky2 = netdev_priv(dev);
2536 struct net_device *dev0 = sky2->hw->dev[0];
2537
2538 if (netif_running(dev) && __netif_rx_schedule_prep(dev0))
2539 __netif_rx_schedule(dev0);
2540 }
2541 #endif
2542
2543 /* Chip internal frequency for clock calculations */
2544 static inline u32 sky2_mhz(const struct sky2_hw *hw)
2545 {
2546 switch (hw->chip_id) {
2547 case CHIP_ID_YUKON_EC:
2548 case CHIP_ID_YUKON_EC_U:
2549 case CHIP_ID_YUKON_EX:
2550 return 125; /* 125 Mhz */
2551 case CHIP_ID_YUKON_FE:
2552 return 100; /* 100 Mhz */
2553 default: /* YUKON_XL */
2554 return 156; /* 156 Mhz */
2555 }
2556 }
2557
2558 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
2559 {
2560 return sky2_mhz(hw) * us;
2561 }
2562
2563 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
2564 {
2565 return clk / sky2_mhz(hw);
2566 }
2567
2568
2569 static int __devinit sky2_init(struct sky2_hw *hw)
2570 {
2571 u8 t8;
2572
2573 /* Enable all clocks */
2574 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
2575
2576 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2577
2578 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2579 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
2580 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2581 hw->chip_id);
2582 return -EOPNOTSUPP;
2583 }
2584
2585 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2586
2587 /* This rev is really old, and requires untested workarounds */
2588 if (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == CHIP_REV_YU_EC_A1) {
2589 dev_err(&hw->pdev->dev, "unsupported revision Yukon-%s (0x%x) rev %d\n",
2590 yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
2591 hw->chip_id, hw->chip_rev);
2592 return -EOPNOTSUPP;
2593 }
2594
2595 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2596 hw->ports = 1;
2597 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2598 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2599 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2600 ++hw->ports;
2601 }
2602
2603 return 0;
2604 }
2605
2606 static void sky2_reset(struct sky2_hw *hw)
2607 {
2608 u16 status;
2609 int i;
2610
2611 /* disable ASF */
2612 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2613 status = sky2_read16(hw, HCU_CCSR);
2614 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
2615 HCU_CCSR_UC_STATE_MSK);
2616 sky2_write16(hw, HCU_CCSR, status);
2617 } else
2618 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2619 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2620
2621 /* do a SW reset */
2622 sky2_write8(hw, B0_CTST, CS_RST_SET);
2623 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2624
2625 /* clear PCI errors, if any */
2626 status = sky2_pci_read16(hw, PCI_STATUS);
2627
2628 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2629 sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);
2630
2631
2632 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2633
2634 /* clear any PEX errors */
2635 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
2636 sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);
2637
2638
2639 sky2_power_on(hw);
2640
2641 for (i = 0; i < hw->ports; i++) {
2642 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2643 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2644
2645 if (hw->chip_id == CHIP_ID_YUKON_EX)
2646 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
2647 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
2648 | GMC_BYP_RETR_ON);
2649 }
2650
2651 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2652
2653 /* Clear I2C IRQ noise */
2654 sky2_write32(hw, B2_I2C_IRQ, 1);
2655
2656 /* turn off hardware timer (unused) */
2657 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2658 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
2659
2660 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2661
2662 /* Turn off descriptor polling */
2663 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
2664
2665 /* Turn off receive timestamp */
2666 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
2667 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2668
2669 /* enable the Tx Arbiters */
2670 for (i = 0; i < hw->ports; i++)
2671 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2672
2673 /* Initialize ram interface */
2674 for (i = 0; i < hw->ports; i++) {
2675 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
2676
2677 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2678 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2679 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2680 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2681 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2682 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2683 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2684 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2685 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2686 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2687 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2688 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2689 }
2690
2691 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
2692
2693 for (i = 0; i < hw->ports; i++)
2694 sky2_gmac_reset(hw, i);
2695
2696 memset(hw->st_le, 0, STATUS_LE_BYTES);
2697 hw->st_idx = 0;
2698
2699 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2700 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2701
2702 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
2703 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
2704
2705 /* Set the list last index */
2706 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
2707
2708 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2709 sky2_write8(hw, STAT_FIFO_WM, 16);
2710
2711 /* set Status-FIFO ISR watermark */
2712 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2713 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2714 else
2715 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
2716
2717 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
2718 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2719 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
2720
2721 /* enable status unit */
2722 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2723
2724 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2725 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2726 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2727 }
2728
2729 static void sky2_restart(struct work_struct *work)
2730 {
2731 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
2732 struct net_device *dev;
2733 int i, err;
2734
2735 dev_dbg(&hw->pdev->dev, "restarting\n");
2736
2737 del_timer_sync(&hw->idle_timer);
2738
2739 rtnl_lock();
2740 sky2_write32(hw, B0_IMSK, 0);
2741 sky2_read32(hw, B0_IMSK);
2742
2743 netif_poll_disable(hw->dev[0]);
2744
2745 for (i = 0; i < hw->ports; i++) {
2746 dev = hw->dev[i];
2747 if (netif_running(dev))
2748 sky2_down(dev);
2749 }
2750
2751 sky2_reset(hw);
2752 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
2753 netif_poll_enable(hw->dev[0]);
2754
2755 for (i = 0; i < hw->ports; i++) {
2756 dev = hw->dev[i];
2757 if (netif_running(dev)) {
2758 err = sky2_up(dev);
2759 if (err) {
2760 printk(KERN_INFO PFX "%s: could not restart %d\n",
2761 dev->name, err);
2762 dev_close(dev);
2763 }
2764 }
2765 }
2766
2767 sky2_idle_start(hw);
2768
2769 rtnl_unlock();
2770 }
2771
2772 static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
2773 {
2774 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
2775 }
2776
2777 static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2778 {
2779 const struct sky2_port *sky2 = netdev_priv(dev);
2780
2781 wol->supported = sky2_wol_supported(sky2->hw);
2782 wol->wolopts = sky2->wol;
2783 }
2784
2785 static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2786 {
2787 struct sky2_port *sky2 = netdev_priv(dev);
2788 struct sky2_hw *hw = sky2->hw;
2789
2790 if (wol->wolopts & ~sky2_wol_supported(sky2->hw))
2791 return -EOPNOTSUPP;
2792
2793 sky2->wol = wol->wolopts;
2794
2795 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX)
2796 sky2_write32(hw, B0_CTST, sky2->wol
2797 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
2798
2799 if (!netif_running(dev))
2800 sky2_wol_init(sky2);
2801 return 0;
2802 }
2803
2804 static u32 sky2_supported_modes(const struct sky2_hw *hw)
2805 {
2806 if (sky2_is_copper(hw)) {
2807 u32 modes = SUPPORTED_10baseT_Half
2808 | SUPPORTED_10baseT_Full
2809 | SUPPORTED_100baseT_Half
2810 | SUPPORTED_100baseT_Full
2811 | SUPPORTED_Autoneg | SUPPORTED_TP;
2812
2813 if (hw->chip_id != CHIP_ID_YUKON_FE)
2814 modes |= SUPPORTED_1000baseT_Half
2815 | SUPPORTED_1000baseT_Full;
2816 return modes;
2817 } else
2818 return SUPPORTED_1000baseT_Half
2819 | SUPPORTED_1000baseT_Full
2820 | SUPPORTED_Autoneg
2821 | SUPPORTED_FIBRE;
2822 }
2823
2824 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2825 {
2826 struct sky2_port *sky2 = netdev_priv(dev);
2827 struct sky2_hw *hw = sky2->hw;
2828
2829 ecmd->transceiver = XCVR_INTERNAL;
2830 ecmd->supported = sky2_supported_modes(hw);
2831 ecmd->phy_address = PHY_ADDR_MARV;
2832 if (sky2_is_copper(hw)) {
2833 ecmd->supported = SUPPORTED_10baseT_Half
2834 | SUPPORTED_10baseT_Full
2835 | SUPPORTED_100baseT_Half
2836 | SUPPORTED_100baseT_Full
2837 | SUPPORTED_1000baseT_Half
2838 | SUPPORTED_1000baseT_Full
2839 | SUPPORTED_Autoneg | SUPPORTED_TP;
2840 ecmd->port = PORT_TP;
2841 ecmd->speed = sky2->speed;
2842 } else {
2843 ecmd->speed = SPEED_1000;
2844 ecmd->port = PORT_FIBRE;
2845 }
2846
2847 ecmd->advertising = sky2->advertising;
2848 ecmd->autoneg = sky2->autoneg;
2849 ecmd->duplex = sky2->duplex;
2850 return 0;
2851 }
2852
2853 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2854 {
2855 struct sky2_port *sky2 = netdev_priv(dev);
2856 const struct sky2_hw *hw = sky2->hw;
2857 u32 supported = sky2_supported_modes(hw);
2858
2859 if (ecmd->autoneg == AUTONEG_ENABLE) {
2860 ecmd->advertising = supported;
2861 sky2->duplex = -1;
2862 sky2->speed = -1;
2863 } else {
2864 u32 setting;
2865
2866 switch (ecmd->speed) {
2867 case SPEED_1000:
2868 if (ecmd->duplex == DUPLEX_FULL)
2869 setting = SUPPORTED_1000baseT_Full;
2870 else if (ecmd->duplex == DUPLEX_HALF)
2871 setting = SUPPORTED_1000baseT_Half;
2872 else
2873 return -EINVAL;
2874 break;
2875 case SPEED_100:
2876 if (ecmd->duplex == DUPLEX_FULL)
2877 setting = SUPPORTED_100baseT_Full;
2878 else if (ecmd->duplex == DUPLEX_HALF)
2879 setting = SUPPORTED_100baseT_Half;
2880 else
2881 return -EINVAL;
2882 break;
2883
2884 case SPEED_10:
2885 if (ecmd->duplex == DUPLEX_FULL)
2886 setting = SUPPORTED_10baseT_Full;
2887 else if (ecmd->duplex == DUPLEX_HALF)
2888 setting = SUPPORTED_10baseT_Half;
2889 else
2890 return -EINVAL;
2891 break;
2892 default:
2893 return -EINVAL;
2894 }
2895
2896 if ((setting & supported) == 0)
2897 return -EINVAL;
2898
2899 sky2->speed = ecmd->speed;
2900 sky2->duplex = ecmd->duplex;
2901 }
2902
2903 sky2->autoneg = ecmd->autoneg;
2904 sky2->advertising = ecmd->advertising;
2905
2906 if (netif_running(dev))
2907 sky2_phy_reinit(sky2);
2908
2909 return 0;
2910 }
2911
2912 static void sky2_get_drvinfo(struct net_device *dev,
2913 struct ethtool_drvinfo *info)
2914 {
2915 struct sky2_port *sky2 = netdev_priv(dev);
2916
2917 strcpy(info->driver, DRV_NAME);
2918 strcpy(info->version, DRV_VERSION);
2919 strcpy(info->fw_version, "N/A");
2920 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2921 }
2922
2923 static const struct sky2_stat {
2924 char name[ETH_GSTRING_LEN];
2925 u16 offset;
2926 } sky2_stats[] = {
2927 { "tx_bytes", GM_TXO_OK_HI },
2928 { "rx_bytes", GM_RXO_OK_HI },
2929 { "tx_broadcast", GM_TXF_BC_OK },
2930 { "rx_broadcast", GM_RXF_BC_OK },
2931 { "tx_multicast", GM_TXF_MC_OK },
2932 { "rx_multicast", GM_RXF_MC_OK },
2933 { "tx_unicast", GM_TXF_UC_OK },
2934 { "rx_unicast", GM_RXF_UC_OK },
2935 { "tx_mac_pause", GM_TXF_MPAUSE },
2936 { "rx_mac_pause", GM_RXF_MPAUSE },
2937 { "collisions", GM_TXF_COL },
2938 { "late_collision",GM_TXF_LAT_COL },
2939 { "aborted", GM_TXF_ABO_COL },
2940 { "single_collisions", GM_TXF_SNG_COL },
2941 { "multi_collisions", GM_TXF_MUL_COL },
2942
2943 { "rx_short", GM_RXF_SHT },
2944 { "rx_runt", GM_RXE_FRAG },
2945 { "rx_64_byte_packets", GM_RXF_64B },
2946 { "rx_65_to_127_byte_packets", GM_RXF_127B },
2947 { "rx_128_to_255_byte_packets", GM_RXF_255B },
2948 { "rx_256_to_511_byte_packets", GM_RXF_511B },
2949 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
2950 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
2951 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
2952 { "rx_too_long", GM_RXF_LNG_ERR },
2953 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
2954 { "rx_jabber", GM_RXF_JAB_PKT },
2955 { "rx_fcs_error", GM_RXF_FCS_ERR },
2956
2957 { "tx_64_byte_packets", GM_TXF_64B },
2958 { "tx_65_to_127_byte_packets", GM_TXF_127B },
2959 { "tx_128_to_255_byte_packets", GM_TXF_255B },
2960 { "tx_256_to_511_byte_packets", GM_TXF_511B },
2961 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
2962 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
2963 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
2964 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
2965 };
2966
2967 static u32 sky2_get_rx_csum(struct net_device *dev)
2968 {
2969 struct sky2_port *sky2 = netdev_priv(dev);
2970
2971 return sky2->rx_csum;
2972 }
2973
2974 static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2975 {
2976 struct sky2_port *sky2 = netdev_priv(dev);
2977
2978 sky2->rx_csum = data;
2979
2980 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2981 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2982
2983 return 0;
2984 }
2985
2986 static u32 sky2_get_msglevel(struct net_device *netdev)
2987 {
2988 struct sky2_port *sky2 = netdev_priv(netdev);
2989 return sky2->msg_enable;
2990 }
2991
2992 static int sky2_nway_reset(struct net_device *dev)
2993 {
2994 struct sky2_port *sky2 = netdev_priv(dev);
2995
2996 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
2997 return -EINVAL;
2998
2999 sky2_phy_reinit(sky2);
3000
3001 return 0;
3002 }
3003
3004 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
3005 {
3006 struct sky2_hw *hw = sky2->hw;
3007 unsigned port = sky2->port;
3008 int i;
3009
3010 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
3011 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
3012 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
3013 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
3014
3015 for (i = 2; i < count; i++)
3016 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3017 }
3018
3019 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3020 {
3021 struct sky2_port *sky2 = netdev_priv(netdev);
3022 sky2->msg_enable = value;
3023 }
3024
3025 static int sky2_get_stats_count(struct net_device *dev)
3026 {
3027 return ARRAY_SIZE(sky2_stats);
3028 }
3029
3030 static void sky2_get_ethtool_stats(struct net_device *dev,
3031 struct ethtool_stats *stats, u64 * data)
3032 {
3033 struct sky2_port *sky2 = netdev_priv(dev);
3034
3035 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
3036 }
3037
3038 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
3039 {
3040 int i;
3041
3042 switch (stringset) {
3043 case ETH_SS_STATS:
3044 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3045 memcpy(data + i * ETH_GSTRING_LEN,
3046 sky2_stats[i].name, ETH_GSTRING_LEN);
3047 break;
3048 }
3049 }
3050
3051 static struct net_device_stats *sky2_get_stats(struct net_device *dev)
3052 {
3053 struct sky2_port *sky2 = netdev_priv(dev);
3054 return &sky2->net_stats;
3055 }
3056
3057 static int sky2_set_mac_address(struct net_device *dev, void *p)
3058 {
3059 struct sky2_port *sky2 = netdev_priv(dev);
3060 struct sky2_hw *hw = sky2->hw;
3061 unsigned port = sky2->port;
3062 const struct sockaddr *addr = p;
3063
3064 if (!is_valid_ether_addr(addr->sa_data))
3065 return -EADDRNOTAVAIL;
3066
3067 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
3068 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
3069 dev->dev_addr, ETH_ALEN);
3070 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
3071 dev->dev_addr, ETH_ALEN);
3072
3073 /* virtual address for data */
3074 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3075
3076 /* physical address: used for pause frames */
3077 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3078
3079 return 0;
3080 }
3081
3082 static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3083 {
3084 u32 bit;
3085
3086 bit = ether_crc(ETH_ALEN, addr) & 63;
3087 filter[bit >> 3] |= 1 << (bit & 7);
3088 }
3089
3090 static void sky2_set_multicast(struct net_device *dev)
3091 {
3092 struct sky2_port *sky2 = netdev_priv(dev);
3093 struct sky2_hw *hw = sky2->hw;
3094 unsigned port = sky2->port;
3095 struct dev_mc_list *list = dev->mc_list;
3096 u16 reg;
3097 u8 filter[8];
3098 int rx_pause;
3099 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
3100
3101 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
3102 memset(filter, 0, sizeof(filter));
3103
3104 reg = gma_read16(hw, port, GM_RX_CTRL);
3105 reg |= GM_RXCR_UCF_ENA;
3106
3107 if (dev->flags & IFF_PROMISC) /* promiscuous */
3108 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
3109 else if (dev->flags & IFF_ALLMULTI)
3110 memset(filter, 0xff, sizeof(filter));
3111 else if (dev->mc_count == 0 && !rx_pause)
3112 reg &= ~GM_RXCR_MCF_ENA;
3113 else {
3114 int i;
3115 reg |= GM_RXCR_MCF_ENA;
3116
3117 if (rx_pause)
3118 sky2_add_filter(filter, pause_mc_addr);
3119
3120 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3121 sky2_add_filter(filter, list->dmi_addr);
3122 }
3123
3124 gma_write16(hw, port, GM_MC_ADDR_H1,
3125 (u16) filter[0] | ((u16) filter[1] << 8));
3126 gma_write16(hw, port, GM_MC_ADDR_H2,
3127 (u16) filter[2] | ((u16) filter[3] << 8));
3128 gma_write16(hw, port, GM_MC_ADDR_H3,
3129 (u16) filter[4] | ((u16) filter[5] << 8));
3130 gma_write16(hw, port, GM_MC_ADDR_H4,
3131 (u16) filter[6] | ((u16) filter[7] << 8));
3132
3133 gma_write16(hw, port, GM_RX_CTRL, reg);
3134 }
3135
3136 /* Can have one global because blinking is controlled by
3137 * ethtool and that is always under RTNL mutex
3138 */
3139 static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
3140 {
3141 u16 pg;
3142
3143 switch (hw->chip_id) {
3144 case CHIP_ID_YUKON_XL:
3145 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3146 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3147 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3148 on ? (PHY_M_LEDC_LOS_CTRL(1) |
3149 PHY_M_LEDC_INIT_CTRL(7) |
3150 PHY_M_LEDC_STA1_CTRL(7) |
3151 PHY_M_LEDC_STA0_CTRL(7))
3152 : 0);
3153
3154 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3155 break;
3156
3157 default:
3158 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
3159 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3160 on ? PHY_M_LED_ALL : 0);
3161 }
3162 }
3163
3164 /* blink LED's for finding board */
3165 static int sky2_phys_id(struct net_device *dev, u32 data)
3166 {
3167 struct sky2_port *sky2 = netdev_priv(dev);
3168 struct sky2_hw *hw = sky2->hw;
3169 unsigned port = sky2->port;
3170 u16 ledctrl, ledover = 0;
3171 long ms;
3172 int interrupted;
3173 int onoff = 1;
3174
3175 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
3176 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
3177 else
3178 ms = data * 1000;
3179
3180 /* save initial values */
3181 spin_lock_bh(&sky2->phy_lock);
3182 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3183 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3184 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3185 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
3186 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3187 } else {
3188 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
3189 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
3190 }
3191
3192 interrupted = 0;
3193 while (!interrupted && ms > 0) {
3194 sky2_led(hw, port, onoff);
3195 onoff = !onoff;
3196
3197 spin_unlock_bh(&sky2->phy_lock);
3198 interrupted = msleep_interruptible(250);
3199 spin_lock_bh(&sky2->phy_lock);
3200
3201 ms -= 250;
3202 }
3203
3204 /* resume regularly scheduled programming */
3205 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3206 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3207 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3208 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
3209 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3210 } else {
3211 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
3212 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
3213 }
3214 spin_unlock_bh(&sky2->phy_lock);
3215
3216 return 0;
3217 }
3218
3219 static void sky2_get_pauseparam(struct net_device *dev,
3220 struct ethtool_pauseparam *ecmd)
3221 {
3222 struct sky2_port *sky2 = netdev_priv(dev);
3223
3224 switch (sky2->flow_mode) {
3225 case FC_NONE:
3226 ecmd->tx_pause = ecmd->rx_pause = 0;
3227 break;
3228 case FC_TX:
3229 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3230 break;
3231 case FC_RX:
3232 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3233 break;
3234 case FC_BOTH:
3235 ecmd->tx_pause = ecmd->rx_pause = 1;
3236 }
3237
3238 ecmd->autoneg = sky2->autoneg;
3239 }
3240
3241 static int sky2_set_pauseparam(struct net_device *dev,
3242 struct ethtool_pauseparam *ecmd)
3243 {
3244 struct sky2_port *sky2 = netdev_priv(dev);
3245
3246 sky2->autoneg = ecmd->autoneg;
3247 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
3248
3249 if (netif_running(dev))
3250 sky2_phy_reinit(sky2);
3251
3252 return 0;
3253 }
3254
3255 static int sky2_get_coalesce(struct net_device *dev,
3256 struct ethtool_coalesce *ecmd)
3257 {
3258 struct sky2_port *sky2 = netdev_priv(dev);
3259 struct sky2_hw *hw = sky2->hw;
3260
3261 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3262 ecmd->tx_coalesce_usecs = 0;
3263 else {
3264 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3265 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3266 }
3267 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3268
3269 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3270 ecmd->rx_coalesce_usecs = 0;
3271 else {
3272 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3273 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3274 }
3275 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3276
3277 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3278 ecmd->rx_coalesce_usecs_irq = 0;
3279 else {
3280 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3281 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3282 }
3283
3284 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3285
3286 return 0;
3287 }
3288
3289 /* Note: this affect both ports */
3290 static int sky2_set_coalesce(struct net_device *dev,
3291 struct ethtool_coalesce *ecmd)
3292 {
3293 struct sky2_port *sky2 = netdev_priv(dev);
3294 struct sky2_hw *hw = sky2->hw;
3295 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
3296
3297 if (ecmd->tx_coalesce_usecs > tmax ||
3298 ecmd->rx_coalesce_usecs > tmax ||
3299 ecmd->rx_coalesce_usecs_irq > tmax)
3300 return -EINVAL;
3301
3302 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
3303 return -EINVAL;
3304 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
3305 return -EINVAL;
3306 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
3307 return -EINVAL;
3308
3309 if (ecmd->tx_coalesce_usecs == 0)
3310 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3311 else {
3312 sky2_write32(hw, STAT_TX_TIMER_INI,
3313 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3314 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3315 }
3316 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3317
3318 if (ecmd->rx_coalesce_usecs == 0)
3319 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3320 else {
3321 sky2_write32(hw, STAT_LEV_TIMER_INI,
3322 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3323 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3324 }
3325 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3326
3327 if (ecmd->rx_coalesce_usecs_irq == 0)
3328 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3329 else {
3330 sky2_write32(hw, STAT_ISR_TIMER_INI,
3331 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3332 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3333 }
3334 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3335 return 0;
3336 }
3337
3338 static void sky2_get_ringparam(struct net_device *dev,
3339 struct ethtool_ringparam *ering)
3340 {
3341 struct sky2_port *sky2 = netdev_priv(dev);
3342
3343 ering->rx_max_pending = RX_MAX_PENDING;
3344 ering->rx_mini_max_pending = 0;
3345 ering->rx_jumbo_max_pending = 0;
3346 ering->tx_max_pending = TX_RING_SIZE - 1;
3347
3348 ering->rx_pending = sky2->rx_pending;
3349 ering->rx_mini_pending = 0;
3350 ering->rx_jumbo_pending = 0;
3351 ering->tx_pending = sky2->tx_pending;
3352 }
3353
3354 static int sky2_set_ringparam(struct net_device *dev,
3355 struct ethtool_ringparam *ering)
3356 {
3357 struct sky2_port *sky2 = netdev_priv(dev);
3358 int err = 0;
3359
3360 if (ering->rx_pending > RX_MAX_PENDING ||
3361 ering->rx_pending < 8 ||
3362 ering->tx_pending < MAX_SKB_TX_LE ||
3363 ering->tx_pending > TX_RING_SIZE - 1)
3364 return -EINVAL;
3365
3366 if (netif_running(dev))
3367 sky2_down(dev);
3368
3369 sky2->rx_pending = ering->rx_pending;
3370 sky2->tx_pending = ering->tx_pending;
3371
3372 if (netif_running(dev)) {
3373 err = sky2_up(dev);
3374 if (err)
3375 dev_close(dev);
3376 else
3377 sky2_set_multicast(dev);
3378 }
3379
3380 return err;
3381 }
3382
3383 static int sky2_get_regs_len(struct net_device *dev)
3384 {
3385 return 0x4000;
3386 }
3387
3388 /*
3389 * Returns copy of control register region
3390 * Note: ethtool_get_regs always provides full size (16k) buffer
3391 */
3392 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3393 void *p)
3394 {
3395 const struct sky2_port *sky2 = netdev_priv(dev);
3396 const void __iomem *io = sky2->hw->regs;
3397
3398 regs->version = 1;
3399 memset(p, 0, regs->len);
3400
3401 memcpy_fromio(p, io, B3_RAM_ADDR);
3402
3403 /* skip diagnostic ram region */
3404 memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1, 0x2000 - B3_RI_WTO_R1);
3405
3406 /* copy GMAC registers */
3407 memcpy_fromio(p + BASE_GMAC_1, io + BASE_GMAC_1, 0x1000);
3408 if (sky2->hw->ports > 1)
3409 memcpy_fromio(p + BASE_GMAC_2, io + BASE_GMAC_2, 0x1000);
3410
3411 }
3412
3413 /* In order to do Jumbo packets on these chips, need to turn off the
3414 * transmit store/forward. Therefore checksum offload won't work.
3415 */
3416 static int no_tx_offload(struct net_device *dev)
3417 {
3418 const struct sky2_port *sky2 = netdev_priv(dev);
3419 const struct sky2_hw *hw = sky2->hw;
3420
3421 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
3422 }
3423
3424 static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3425 {
3426 if (data && no_tx_offload(dev))
3427 return -EINVAL;
3428
3429 return ethtool_op_set_tx_csum(dev, data);
3430 }
3431
3432
3433 static int sky2_set_tso(struct net_device *dev, u32 data)
3434 {
3435 if (data && no_tx_offload(dev))
3436 return -EINVAL;
3437
3438 return ethtool_op_set_tso(dev, data);
3439 }
3440
3441 static const struct ethtool_ops sky2_ethtool_ops = {
3442 .get_settings = sky2_get_settings,
3443 .set_settings = sky2_set_settings,
3444 .get_drvinfo = sky2_get_drvinfo,
3445 .get_wol = sky2_get_wol,
3446 .set_wol = sky2_set_wol,
3447 .get_msglevel = sky2_get_msglevel,
3448 .set_msglevel = sky2_set_msglevel,
3449 .nway_reset = sky2_nway_reset,
3450 .get_regs_len = sky2_get_regs_len,
3451 .get_regs = sky2_get_regs,
3452 .get_link = ethtool_op_get_link,
3453 .get_sg = ethtool_op_get_sg,
3454 .set_sg = ethtool_op_set_sg,
3455 .get_tx_csum = ethtool_op_get_tx_csum,
3456 .set_tx_csum = sky2_set_tx_csum,
3457 .get_tso = ethtool_op_get_tso,
3458 .set_tso = sky2_set_tso,
3459 .get_rx_csum = sky2_get_rx_csum,
3460 .set_rx_csum = sky2_set_rx_csum,
3461 .get_strings = sky2_get_strings,
3462 .get_coalesce = sky2_get_coalesce,
3463 .set_coalesce = sky2_set_coalesce,
3464 .get_ringparam = sky2_get_ringparam,
3465 .set_ringparam = sky2_set_ringparam,
3466 .get_pauseparam = sky2_get_pauseparam,
3467 .set_pauseparam = sky2_set_pauseparam,
3468 .phys_id = sky2_phys_id,
3469 .get_stats_count = sky2_get_stats_count,
3470 .get_ethtool_stats = sky2_get_ethtool_stats,
3471 .get_perm_addr = ethtool_op_get_perm_addr,
3472 };
3473
3474 #ifdef CONFIG_SKY2_DEBUG
3475
3476 static struct dentry *sky2_debug;
3477
3478 static int sky2_debug_show(struct seq_file *seq, void *v)
3479 {
3480 struct net_device *dev = seq->private;
3481 const struct sky2_port *sky2 = netdev_priv(dev);
3482 const struct sky2_hw *hw = sky2->hw;
3483 unsigned port = sky2->port;
3484 unsigned idx, last;
3485 int sop;
3486
3487 if (!netif_running(dev))
3488 return -ENETDOWN;
3489
3490 seq_printf(seq, "IRQ src=%x mask=%x control=%x\n",
3491 sky2_read32(hw, B0_ISRC),
3492 sky2_read32(hw, B0_IMSK),
3493 sky2_read32(hw, B0_Y2_SP_ICR));
3494
3495 netif_poll_disable(hw->dev[0]);
3496 last = sky2_read16(hw, STAT_PUT_IDX);
3497
3498 if (hw->st_idx == last)
3499 seq_puts(seq, "Status ring (empty)\n");
3500 else {
3501 seq_puts(seq, "Status ring\n");
3502 for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE;
3503 idx = RING_NEXT(idx, STATUS_RING_SIZE)) {
3504 const struct sky2_status_le *le = hw->st_le + idx;
3505 seq_printf(seq, "[%d] %#x %d %#x\n",
3506 idx, le->opcode, le->length, le->status);
3507 }
3508 seq_puts(seq, "\n");
3509 }
3510
3511 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
3512 sky2->tx_cons, sky2->tx_prod,
3513 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
3514 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
3515
3516 /* Dump contents of tx ring */
3517 sop = 1;
3518 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < TX_RING_SIZE;
3519 idx = RING_NEXT(idx, TX_RING_SIZE)) {
3520 const struct sky2_tx_le *le = sky2->tx_le + idx;
3521 u32 a = le32_to_cpu(le->addr);
3522
3523 if (sop)
3524 seq_printf(seq, "%u:", idx);
3525 sop = 0;
3526
3527 switch(le->opcode & ~HW_OWNER) {
3528 case OP_ADDR64:
3529 seq_printf(seq, " %#x:", a);
3530 break;
3531 case OP_LRGLEN:
3532 seq_printf(seq, " mtu=%d", a);
3533 break;
3534 case OP_VLAN:
3535 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
3536 break;
3537 case OP_TCPLISW:
3538 seq_printf(seq, " csum=%#x", a);
3539 break;
3540 case OP_LARGESEND:
3541 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
3542 break;
3543 case OP_PACKET:
3544 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
3545 break;
3546 case OP_BUFFER:
3547 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
3548 break;
3549 default:
3550 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
3551 a, le16_to_cpu(le->length));
3552 }
3553
3554 if (le->ctrl & EOP) {
3555 seq_putc(seq, '\n');
3556 sop = 1;
3557 }
3558 }
3559
3560 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
3561 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
3562 last = sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
3563 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
3564
3565 netif_poll_enable(hw->dev[0]);
3566 return 0;
3567 }
3568
3569 static int sky2_debug_open(struct inode *inode, struct file *file)
3570 {
3571 return single_open(file, sky2_debug_show, inode->i_private);
3572 }
3573
3574 static const struct file_operations sky2_debug_fops = {
3575 .owner = THIS_MODULE,
3576 .open = sky2_debug_open,
3577 .read = seq_read,
3578 .llseek = seq_lseek,
3579 .release = single_release,
3580 };
3581
3582 /*
3583 * Use network device events to create/remove/rename
3584 * debugfs file entries
3585 */
3586 static int sky2_device_event(struct notifier_block *unused,
3587 unsigned long event, void *ptr)
3588 {
3589 struct net_device *dev = ptr;
3590
3591 if (dev->open == sky2_up) {
3592 struct sky2_port *sky2 = netdev_priv(dev);
3593
3594 switch(event) {
3595 case NETDEV_CHANGENAME:
3596 if (!netif_running(dev))
3597 break;
3598 /* fallthrough */
3599 case NETDEV_DOWN:
3600 case NETDEV_GOING_DOWN:
3601 if (sky2->debugfs) {
3602 printk(KERN_DEBUG PFX "%s: remove debugfs\n",
3603 dev->name);
3604 debugfs_remove(sky2->debugfs);
3605 sky2->debugfs = NULL;
3606 }
3607
3608 if (event != NETDEV_CHANGENAME)
3609 break;
3610 /* fallthrough for changename */
3611 case NETDEV_UP:
3612 if (sky2_debug) {
3613 struct dentry *d;
3614 d = debugfs_create_file(dev->name, S_IRUGO,
3615 sky2_debug, dev,
3616 &sky2_debug_fops);
3617 if (d == NULL || IS_ERR(d))
3618 printk(KERN_INFO PFX
3619 "%s: debugfs create failed\n",
3620 dev->name);
3621 else
3622 sky2->debugfs = d;
3623 }
3624 break;
3625 }
3626 }
3627
3628 return NOTIFY_DONE;
3629 }
3630
3631 static struct notifier_block sky2_notifier = {
3632 .notifier_call = sky2_device_event,
3633 };
3634
3635
3636 static __init void sky2_debug_init(void)
3637 {
3638 struct dentry *ent;
3639
3640 ent = debugfs_create_dir("sky2", NULL);
3641 if (!ent || IS_ERR(ent))
3642 return;
3643
3644 sky2_debug = ent;
3645 register_netdevice_notifier(&sky2_notifier);
3646 }
3647
3648 static __exit void sky2_debug_cleanup(void)
3649 {
3650 if (sky2_debug) {
3651 unregister_netdevice_notifier(&sky2_notifier);
3652 debugfs_remove(sky2_debug);
3653 sky2_debug = NULL;
3654 }
3655 }
3656
3657 #else
3658 #define sky2_debug_init()
3659 #define sky2_debug_cleanup()
3660 #endif
3661
3662
3663 /* Initialize network device */
3664 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
3665 unsigned port,
3666 int highmem, int wol)
3667 {
3668 struct sky2_port *sky2;
3669 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3670
3671 if (!dev) {
3672 dev_err(&hw->pdev->dev, "etherdev alloc failed");
3673 return NULL;
3674 }
3675
3676 SET_MODULE_OWNER(dev);
3677 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3678 dev->irq = hw->pdev->irq;
3679 dev->open = sky2_up;
3680 dev->stop = sky2_down;
3681 dev->do_ioctl = sky2_ioctl;
3682 dev->hard_start_xmit = sky2_xmit_frame;
3683 dev->get_stats = sky2_get_stats;
3684 dev->set_multicast_list = sky2_set_multicast;
3685 dev->set_mac_address = sky2_set_mac_address;
3686 dev->change_mtu = sky2_change_mtu;
3687 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3688 dev->tx_timeout = sky2_tx_timeout;
3689 dev->watchdog_timeo = TX_WATCHDOG;
3690 if (port == 0)
3691 dev->poll = sky2_poll;
3692 dev->weight = NAPI_WEIGHT;
3693 #ifdef CONFIG_NET_POLL_CONTROLLER
3694 /* Network console (only works on port 0)
3695 * because netpoll makes assumptions about NAPI
3696 */
3697 if (port == 0)
3698 dev->poll_controller = sky2_netpoll;
3699 #endif
3700
3701 sky2 = netdev_priv(dev);
3702 sky2->netdev = dev;
3703 sky2->hw = hw;
3704 sky2->msg_enable = netif_msg_init(debug, default_msg);
3705
3706 /* Auto speed and flow control */
3707 sky2->autoneg = AUTONEG_ENABLE;
3708 sky2->flow_mode = FC_BOTH;
3709
3710 sky2->duplex = -1;
3711 sky2->speed = -1;
3712 sky2->advertising = sky2_supported_modes(hw);
3713 sky2->rx_csum = 1;
3714 sky2->wol = wol;
3715
3716 spin_lock_init(&sky2->phy_lock);
3717 sky2->tx_pending = TX_DEF_PENDING;
3718 sky2->rx_pending = RX_DEF_PENDING;
3719
3720 hw->dev[port] = dev;
3721
3722 sky2->port = port;
3723
3724 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
3725 if (highmem)
3726 dev->features |= NETIF_F_HIGHDMA;
3727
3728 #ifdef SKY2_VLAN_TAG_USED
3729 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3730 dev->vlan_rx_register = sky2_vlan_rx_register;
3731 #endif
3732
3733 /* read the mac address */
3734 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
3735 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3736
3737 return dev;
3738 }
3739
3740 static void __devinit sky2_show_addr(struct net_device *dev)
3741 {
3742 const struct sky2_port *sky2 = netdev_priv(dev);
3743
3744 if (netif_msg_probe(sky2))
3745 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3746 dev->name,
3747 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3748 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3749 }
3750
3751 /* Handle software interrupt used during MSI test */
3752 static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
3753 {
3754 struct sky2_hw *hw = dev_id;
3755 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3756
3757 if (status == 0)
3758 return IRQ_NONE;
3759
3760 if (status & Y2_IS_IRQ_SW) {
3761 hw->msi = 1;
3762 wake_up(&hw->msi_wait);
3763 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3764 }
3765 sky2_write32(hw, B0_Y2_SP_ICR, 2);
3766
3767 return IRQ_HANDLED;
3768 }
3769
3770 /* Test interrupt path by forcing a a software IRQ */
3771 static int __devinit sky2_test_msi(struct sky2_hw *hw)
3772 {
3773 struct pci_dev *pdev = hw->pdev;
3774 int err;
3775
3776 init_waitqueue_head (&hw->msi_wait);
3777
3778 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
3779
3780 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
3781 if (err) {
3782 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
3783 return err;
3784 }
3785
3786 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
3787 sky2_read8(hw, B0_CTST);
3788
3789 wait_event_timeout(hw->msi_wait, hw->msi, HZ/10);
3790
3791 if (!hw->msi) {
3792 /* MSI test failed, go back to INTx mode */
3793 dev_info(&pdev->dev, "No interrupt generated using MSI, "
3794 "switching to INTx mode.\n");
3795
3796 err = -EOPNOTSUPP;
3797 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3798 }
3799
3800 sky2_write32(hw, B0_IMSK, 0);
3801 sky2_read32(hw, B0_IMSK);
3802
3803 free_irq(pdev->irq, hw);
3804
3805 return err;
3806 }
3807
3808 static int __devinit pci_wake_enabled(struct pci_dev *dev)
3809 {
3810 int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
3811 u16 value;
3812
3813 if (!pm)
3814 return 0;
3815 if (pci_read_config_word(dev, pm + PCI_PM_CTRL, &value))
3816 return 0;
3817 return value & PCI_PM_CTRL_PME_ENABLE;
3818 }
3819
3820 static int __devinit sky2_probe(struct pci_dev *pdev,
3821 const struct pci_device_id *ent)
3822 {
3823 struct net_device *dev;
3824 struct sky2_hw *hw;
3825 int err, using_dac = 0, wol_default;
3826
3827 err = pci_enable_device(pdev);
3828 if (err) {
3829 dev_err(&pdev->dev, "cannot enable PCI device\n");
3830 goto err_out;
3831 }
3832
3833 err = pci_request_regions(pdev, DRV_NAME);
3834 if (err) {
3835 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
3836 goto err_out_disable;
3837 }
3838
3839 pci_set_master(pdev);
3840
3841 if (sizeof(dma_addr_t) > sizeof(u32) &&
3842 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
3843 using_dac = 1;
3844 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3845 if (err < 0) {
3846 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
3847 "for consistent allocations\n");
3848 goto err_out_free_regions;
3849 }
3850 } else {
3851 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3852 if (err) {
3853 dev_err(&pdev->dev, "no usable DMA configuration\n");
3854 goto err_out_free_regions;
3855 }
3856 }
3857
3858 wol_default = pci_wake_enabled(pdev) ? WAKE_MAGIC : 0;
3859
3860 err = -ENOMEM;
3861 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
3862 if (!hw) {
3863 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
3864 goto err_out_free_regions;
3865 }
3866
3867 hw->pdev = pdev;
3868
3869 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3870 if (!hw->regs) {
3871 dev_err(&pdev->dev, "cannot map device registers\n");
3872 goto err_out_free_hw;
3873 }
3874
3875 #ifdef __BIG_ENDIAN
3876 /* The sk98lin vendor driver uses hardware byte swapping but
3877 * this driver uses software swapping.
3878 */
3879 {
3880 u32 reg;
3881 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
3882 reg &= ~PCI_REV_DESC;
3883 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
3884 }
3885 #endif
3886
3887 /* ring for status responses */
3888 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
3889 &hw->st_dma);
3890 if (!hw->st_le)
3891 goto err_out_iounmap;
3892
3893 err = sky2_init(hw);
3894 if (err)
3895 goto err_out_iounmap;
3896
3897 dev_info(&pdev->dev, "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
3898 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
3899 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
3900 hw->chip_id, hw->chip_rev);
3901
3902 sky2_reset(hw);
3903
3904 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
3905 if (!dev) {
3906 err = -ENOMEM;
3907 goto err_out_free_pci;
3908 }
3909
3910 if (!disable_msi && pci_enable_msi(pdev) == 0) {
3911 err = sky2_test_msi(hw);
3912 if (err == -EOPNOTSUPP)
3913 pci_disable_msi(pdev);
3914 else if (err)
3915 goto err_out_free_netdev;
3916 }
3917
3918 err = register_netdev(dev);
3919 if (err) {
3920 dev_err(&pdev->dev, "cannot register net device\n");
3921 goto err_out_free_netdev;
3922 }
3923
3924 err = request_irq(pdev->irq, sky2_intr, hw->msi ? 0 : IRQF_SHARED,
3925 dev->name, hw);
3926 if (err) {
3927 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
3928 goto err_out_unregister;
3929 }
3930 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3931
3932 sky2_show_addr(dev);
3933
3934 if (hw->ports > 1) {
3935 struct net_device *dev1;
3936
3937 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
3938 if (!dev1)
3939 dev_warn(&pdev->dev, "allocation for second device failed\n");
3940 else if ((err = register_netdev(dev1))) {
3941 dev_warn(&pdev->dev,
3942 "register of second port failed (%d)\n", err);
3943 hw->dev[1] = NULL;
3944 free_netdev(dev1);
3945 } else
3946 sky2_show_addr(dev1);
3947 }
3948
3949 setup_timer(&hw->idle_timer, sky2_idle, (unsigned long) hw);
3950 INIT_WORK(&hw->restart_work, sky2_restart);
3951
3952 sky2_idle_start(hw);
3953
3954 pci_set_drvdata(pdev, hw);
3955
3956 return 0;
3957
3958 err_out_unregister:
3959 if (hw->msi)
3960 pci_disable_msi(pdev);
3961 unregister_netdev(dev);
3962 err_out_free_netdev:
3963 free_netdev(dev);
3964 err_out_free_pci:
3965 sky2_write8(hw, B0_CTST, CS_RST_SET);
3966 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3967 err_out_iounmap:
3968 iounmap(hw->regs);
3969 err_out_free_hw:
3970 kfree(hw);
3971 err_out_free_regions:
3972 pci_release_regions(pdev);
3973 err_out_disable:
3974 pci_disable_device(pdev);
3975 err_out:
3976 pci_set_drvdata(pdev, NULL);
3977 return err;
3978 }
3979
3980 static void __devexit sky2_remove(struct pci_dev *pdev)
3981 {
3982 struct sky2_hw *hw = pci_get_drvdata(pdev);
3983 struct net_device *dev0, *dev1;
3984
3985 if (!hw)
3986 return;
3987
3988 del_timer_sync(&hw->idle_timer);
3989
3990 flush_scheduled_work();
3991
3992 sky2_write32(hw, B0_IMSK, 0);
3993 synchronize_irq(hw->pdev->irq);
3994
3995 dev0 = hw->dev[0];
3996 dev1 = hw->dev[1];
3997 if (dev1)
3998 unregister_netdev(dev1);
3999 unregister_netdev(dev0);
4000
4001 sky2_power_aux(hw);
4002
4003 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
4004 sky2_write8(hw, B0_CTST, CS_RST_SET);
4005 sky2_read8(hw, B0_CTST);
4006
4007 free_irq(pdev->irq, hw);
4008 if (hw->msi)
4009 pci_disable_msi(pdev);
4010 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
4011 pci_release_regions(pdev);
4012 pci_disable_device(pdev);
4013
4014 if (dev1)
4015 free_netdev(dev1);
4016 free_netdev(dev0);
4017 iounmap(hw->regs);
4018 kfree(hw);
4019
4020 pci_set_drvdata(pdev, NULL);
4021 }
4022
4023 #ifdef CONFIG_PM
4024 static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4025 {
4026 struct sky2_hw *hw = pci_get_drvdata(pdev);
4027 int i, wol = 0;
4028
4029 if (!hw)
4030 return 0;
4031
4032 del_timer_sync(&hw->idle_timer);
4033 netif_poll_disable(hw->dev[0]);
4034
4035 for (i = 0; i < hw->ports; i++) {
4036 struct net_device *dev = hw->dev[i];
4037 struct sky2_port *sky2 = netdev_priv(dev);
4038
4039 if (netif_running(dev))
4040 sky2_down(dev);
4041
4042 if (sky2->wol)
4043 sky2_wol_init(sky2);
4044
4045 wol |= sky2->wol;
4046 }
4047
4048 sky2_write32(hw, B0_IMSK, 0);
4049 sky2_power_aux(hw);
4050
4051 pci_save_state(pdev);
4052 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
4053 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4054
4055 return 0;
4056 }
4057
4058 static int sky2_resume(struct pci_dev *pdev)
4059 {
4060 struct sky2_hw *hw = pci_get_drvdata(pdev);
4061 int i, err;
4062
4063 if (!hw)
4064 return 0;
4065
4066 err = pci_set_power_state(pdev, PCI_D0);
4067 if (err)
4068 goto out;
4069
4070 err = pci_restore_state(pdev);
4071 if (err)
4072 goto out;
4073
4074 pci_enable_wake(pdev, PCI_D0, 0);
4075
4076 /* Re-enable all clocks */
4077 if (hw->chip_id == CHIP_ID_YUKON_EX || hw->chip_id == CHIP_ID_YUKON_EC_U)
4078 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
4079
4080 sky2_reset(hw);
4081
4082 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4083
4084 for (i = 0; i < hw->ports; i++) {
4085 struct net_device *dev = hw->dev[i];
4086 if (netif_running(dev)) {
4087 err = sky2_up(dev);
4088 if (err) {
4089 printk(KERN_ERR PFX "%s: could not up: %d\n",
4090 dev->name, err);
4091 dev_close(dev);
4092 goto out;
4093 }
4094 }
4095 }
4096
4097 netif_poll_enable(hw->dev[0]);
4098 sky2_idle_start(hw);
4099 return 0;
4100 out:
4101 dev_err(&pdev->dev, "resume failed (%d)\n", err);
4102 pci_disable_device(pdev);
4103 return err;
4104 }
4105 #endif
4106
4107 static void sky2_shutdown(struct pci_dev *pdev)
4108 {
4109 struct sky2_hw *hw = pci_get_drvdata(pdev);
4110 int i, wol = 0;
4111
4112 if (!hw)
4113 return;
4114
4115 del_timer_sync(&hw->idle_timer);
4116 netif_poll_disable(hw->dev[0]);
4117
4118 for (i = 0; i < hw->ports; i++) {
4119 struct net_device *dev = hw->dev[i];
4120 struct sky2_port *sky2 = netdev_priv(dev);
4121
4122 if (sky2->wol) {
4123 wol = 1;
4124 sky2_wol_init(sky2);
4125 }
4126 }
4127
4128 if (wol)
4129 sky2_power_aux(hw);
4130
4131 pci_enable_wake(pdev, PCI_D3hot, wol);
4132 pci_enable_wake(pdev, PCI_D3cold, wol);
4133
4134 pci_disable_device(pdev);
4135 pci_set_power_state(pdev, PCI_D3hot);
4136
4137 }
4138
4139 static struct pci_driver sky2_driver = {
4140 .name = DRV_NAME,
4141 .id_table = sky2_id_table,
4142 .probe = sky2_probe,
4143 .remove = __devexit_p(sky2_remove),
4144 #ifdef CONFIG_PM
4145 .suspend = sky2_suspend,
4146 .resume = sky2_resume,
4147 #endif
4148 .shutdown = sky2_shutdown,
4149 };
4150
4151 static int __init sky2_init_module(void)
4152 {
4153 sky2_debug_init();
4154 return pci_register_driver(&sky2_driver);
4155 }
4156
4157 static void __exit sky2_cleanup_module(void)
4158 {
4159 pci_unregister_driver(&sky2_driver);
4160 sky2_debug_cleanup();
4161 }
4162
4163 module_init(sky2_init_module);
4164 module_exit(sky2_cleanup_module);
4165
4166 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
4167 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
4168 MODULE_LICENSE("GPL");
4169 MODULE_VERSION(DRV_VERSION);
USB Experimental Work