include/asm-i386/processor.h

   1 /*
   2  * include/asm-i386/processor.h
   3  *
   4  * Copyright (C) 1994 Linus Torvalds
   5  */
   6
   7 #ifndef __ASM_I386_PROCESSOR_H
   8 #define __ASM_I386_PROCESSOR_H
   9
  10 #include <asm/vm86.h>
  11 #include <asm/math_emu.h>
  12 #include <asm/segment.h>
  13 #include <asm/page.h>
  14 #include <asm/types.h>
  15 #include <asm/sigcontext.h>
  16 #include <asm/cpufeature.h>
  17 #include <asm/msr.h>
  18 #include <asm/system.h>
  19 #include <linux/cache.h>
  20 #include <linux/threads.h>
  21 #include <asm/percpu.h>
  22 #include <linux/cpumask.h>
  23
  24 /* flag for disabling the tsc */
  25 extern int tsc_disable;
  26
  27 struct desc_struct {
  28         unsigned long a,b;
  29 };
  30
  31 #define desc_empty(desc) \
  32                 (!((desc)->a | (desc)->b))
  33
  34 #define desc_equal(desc1, desc2) \
  35                 (((desc1)->a == (desc2)->a) && ((desc1)->b == (desc2)->b))
  36 /*
  37  * Default implementation of macro that returns current
  38  * instruction pointer ("program counter").
  39  */
  40 #define current_text_addr() ({ void *pc; __asm__("movl $1f,%0\n1:":"=g" (pc)); pc; })
  41
  42 /*
  43  *  CPU type and hardware bug flags. Kept separately for each CPU.
  44  *  Members of this structure are referenced in head.S, so think twice
  45  *  before touching them. [mj]
  46  */
  47
  48 struct cpuinfo_x86 {
  49         __u8    x86;            /* CPU family */
  50         __u8    x86_vendor;     /* CPU vendor */
  51         __u8    x86_model;
  52         __u8    x86_mask;
  53         char    wp_works_ok;    /* It doesn't on 386's */
  54         char    hlt_works_ok;   /* Problems on some 486Dx4's and old 386's */
  55         char    hard_math;
  56         char    rfu;
  57         int     cpuid_level;    /* Maximum supported CPUID level, -1=no CPUID */
  58         unsigned long   x86_capability[NCAPINTS];
  59         char    x86_vendor_id[16];
  60         char    x86_model_id[64];
  61         int     x86_cache_size;  /* in KB - valid for CPUS which support this
  62                                     call  */
  63         int     x86_cache_alignment;    /* In bytes */
  64         char    fdiv_bug;
  65         char    f00f_bug;
  66         char    coma_bug;
  67         char    pad0;
  68         int     x86_power;
  69         unsigned long loops_per_jiffy;
  70 #ifdef CONFIG_SMP
  71         cpumask_t llc_shared_map;       /* cpus sharing the last level cache */
  72 #endif
  73         unsigned char x86_max_cores;    /* cpuid returned max cores value */
  74         unsigned char apicid;
  75 #ifdef CONFIG_SMP
  76         unsigned char booted_cores;     /* number of cores as seen by OS */
  77         __u8 phys_proc_id;              /* Physical processor id. */
  78         __u8 cpu_core_id;               /* Core id */
  79 #endif
  80 } __attribute__((__aligned__(SMP_CACHE_BYTES)));
  81
  82 #define X86_VENDOR_INTEL 0
  83 #define X86_VENDOR_CYRIX 1
  84 #define X86_VENDOR_AMD 2
  85 #define X86_VENDOR_UMC 3
  86 #define X86_VENDOR_NEXGEN 4
  87 #define X86_VENDOR_CENTAUR 5
  88 #define X86_VENDOR_RISE 6
  89 #define X86_VENDOR_TRANSMETA 7
  90 #define X86_VENDOR_NSC 8
  91 #define X86_VENDOR_NUM 9
  92 #define X86_VENDOR_UNKNOWN 0xff
  93
  94 /*
  95  * capabilities of CPUs
  96  */
  97
  98 extern struct cpuinfo_x86 boot_cpu_data;
  99 extern struct cpuinfo_x86 new_cpu_data;
 100 extern struct tss_struct doublefault_tss;
 101 DECLARE_PER_CPU(struct tss_struct, init_tss);
 102
 103 #ifdef CONFIG_SMP
 104 extern struct cpuinfo_x86 cpu_data[];
 105 #define current_cpu_data cpu_data[smp_processor_id()]
 106 #else
 107 #define cpu_data (&boot_cpu_data)
 108 #define current_cpu_data boot_cpu_data
 109 #endif
 110
 111 extern  int cpu_llc_id[NR_CPUS];
 112 extern char ignore_fpu_irq;
 113
 114 extern void identify_cpu(struct cpuinfo_x86 *);
 115 extern void print_cpu_info(struct cpuinfo_x86 *);
 116 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
 117 extern unsigned short num_cache_leaves;
 118
 119 #ifdef CONFIG_X86_HT
 120 extern void detect_ht(struct cpuinfo_x86 *c);
 121 #else
 122 static inline void detect_ht(struct cpuinfo_x86 *c) {}
 123 #endif
 124
 125 /*
 126  * EFLAGS bits
 127  */
 128 #define X86_EFLAGS_CF   0x00000001 /* Carry Flag */
 129 #define X86_EFLAGS_PF   0x00000004 /* Parity Flag */
 130 #define X86_EFLAGS_AF   0x00000010 /* Auxillary carry Flag */
 131 #define X86_EFLAGS_ZF   0x00000040 /* Zero Flag */
 132 #define X86_EFLAGS_SF   0x00000080 /* Sign Flag */
 133 #define X86_EFLAGS_TF   0x00000100 /* Trap Flag */
 134 #define X86_EFLAGS_IF   0x00000200 /* Interrupt Flag */
 135 #define X86_EFLAGS_DF   0x00000400 /* Direction Flag */
 136 #define X86_EFLAGS_OF   0x00000800 /* Overflow Flag */
 137 #define X86_EFLAGS_IOPL 0x00003000 /* IOPL mask */
 138 #define X86_EFLAGS_NT   0x00004000 /* Nested Task */
 139 #define X86_EFLAGS_RF   0x00010000 /* Resume Flag */
 140 #define X86_EFLAGS_VM   0x00020000 /* Virtual Mode */
 141 #define X86_EFLAGS_AC   0x00040000 /* Alignment Check */
 142 #define X86_EFLAGS_VIF  0x00080000 /* Virtual Interrupt Flag */
 143 #define X86_EFLAGS_VIP  0x00100000 /* Virtual Interrupt Pending */
 144 #define X86_EFLAGS_ID   0x00200000 /* CPUID detection flag */
 145
 146 static inline void __cpuid(unsigned int *eax, unsigned int *ebx,
 147                            unsigned int *ecx, unsigned int *edx)
 148 {
 149         /* ecx is often an input as well as an output. */
 150         __asm__("cpuid"
 151                 : "=a" (*eax),
 152                   "=b" (*ebx),
 153                   "=c" (*ecx),
 154                   "=d" (*edx)
 155                 : "0" (*eax), "2" (*ecx));
 156 }
 157
 158 /*
 159  * Generic CPUID function
 160  * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
 161  * resulting in stale register contents being returned.
 162  */
 163 static inline void cpuid(unsigned int op, unsigned int *eax, unsigned int *ebx, unsigned int *ecx, unsigned int *edx)
 164 {
 165         *eax = op;
 166         *ecx = 0;
 167         __cpuid(eax, ebx, ecx, edx);
 168 }
 169
 170 /* Some CPUID calls want 'count' to be placed in ecx */
 171 static inline void cpuid_count(int op, int count, int *eax, int *ebx, int *ecx,
 172                                int *edx)
 173 {
 174         *eax = op;
 175         *ecx = count;
 176         __cpuid(eax, ebx, ecx, edx);
 177 }
 178
 179 /*
 180  * CPUID functions returning a single datum
 181  */
 182 static inline unsigned int cpuid_eax(unsigned int op)
 183 {
 184         unsigned int eax, ebx, ecx, edx;
 185
 186         cpuid(op, &eax, &ebx, &ecx, &edx);
 187         return eax;
 188 }
 189 static inline unsigned int cpuid_ebx(unsigned int op)
 190 {
 191         unsigned int eax, ebx, ecx, edx;
 192
 193         cpuid(op, &eax, &ebx, &ecx, &edx);
 194         return ebx;
 195 }
 196 static inline unsigned int cpuid_ecx(unsigned int op)
 197 {
 198         unsigned int eax, ebx, ecx, edx;
 199
 200         cpuid(op, &eax, &ebx, &ecx, &edx);
 201         return ecx;
 202 }
 203 static inline unsigned int cpuid_edx(unsigned int op)
 204 {
 205         unsigned int eax, ebx, ecx, edx;
 206
 207         cpuid(op, &eax, &ebx, &ecx, &edx);
 208         return edx;
 209 }
 210
 211 #define load_cr3(pgdir) write_cr3(__pa(pgdir))
 212
 213 /*
 214  * Intel CPU features in CR4
 215  */
 216 #define X86_CR4_VME             0x0001  /* enable vm86 extensions */
 217 #define X86_CR4_PVI             0x0002  /* virtual interrupts flag enable */
 218 #define X86_CR4_TSD             0x0004  /* disable time stamp at ipl 3 */
 219 #define X86_CR4_DE              0x0008  /* enable debugging extensions */
 220 #define X86_CR4_PSE             0x0010  /* enable page size extensions */
 221 #define X86_CR4_PAE             0x0020  /* enable physical address extensions */
 222 #define X86_CR4_MCE             0x0040  /* Machine check enable */
 223 #define X86_CR4_PGE             0x0080  /* enable global pages */
 224 #define X86_CR4_PCE             0x0100  /* enable performance counters at ipl 3 */
 225 #define X86_CR4_OSFXSR          0x0200  /* enable fast FPU save and restore */
 226 #define X86_CR4_OSXMMEXCPT      0x0400  /* enable unmasked SSE exceptions */
 227
 228 /*
 229  * Save the cr4 feature set we're using (ie
 230  * Pentium 4MB enable and PPro Global page
 231  * enable), so that any CPU's that boot up
 232  * after us can get the correct flags.
 233  */
 234 extern unsigned long mmu_cr4_features;
 235
 236 static inline void set_in_cr4 (unsigned long mask)
 237 {
 238         unsigned cr4;
 239         mmu_cr4_features |= mask;
 240         cr4 = read_cr4();
 241         cr4 |= mask;
 242         write_cr4(cr4);
 243 }
 244
 245 static inline void clear_in_cr4 (unsigned long mask)
 246 {
 247         unsigned cr4;
 248         mmu_cr4_features &= ~mask;
 249         cr4 = read_cr4();
 250         cr4 &= ~mask;
 251         write_cr4(cr4);
 252 }
 253
 254 /*
 255  *      NSC/Cyrix CPU configuration register indexes
 256  */
 257
 258 #define CX86_PCR0 0x20
 259 #define CX86_GCR  0xb8
 260 #define CX86_CCR0 0xc0
 261 #define CX86_CCR1 0xc1
 262 #define CX86_CCR2 0xc2
 263 #define CX86_CCR3 0xc3
 264 #define CX86_CCR4 0xe8
 265 #define CX86_CCR5 0xe9
 266 #define CX86_CCR6 0xea
 267 #define CX86_CCR7 0xeb
 268 #define CX86_PCR1 0xf0
 269 #define CX86_DIR0 0xfe
 270 #define CX86_DIR1 0xff
 271 #define CX86_ARR_BASE 0xc4
 272 #define CX86_RCR_BASE 0xdc
 273
 274 /*
 275  *      NSC/Cyrix CPU indexed register access macros
 276  */
 277
 278 #define getCx86(reg) ({ outb((reg), 0x22); inb(0x23); })
 279
 280 #define setCx86(reg, data) do { \
 281         outb((reg), 0x22); \
 282         outb((data), 0x23); \
 283 } while (0)
 284
 285 /* Stop speculative execution */
 286 static inline void sync_core(void)
 287 {
 288         int tmp;
 289         asm volatile("cpuid" : "=a" (tmp) : "0" (1) : "ebx","ecx","edx","memory");
 290 }
 291
 292 static inline void __monitor(const void *eax, unsigned long ecx,
 293                 unsigned long edx)
 294 {
 295         /* "monitor %eax,%ecx,%edx;" */
 296         asm volatile(
 297                 ".byte 0x0f,0x01,0xc8;"
 298                 : :"a" (eax), "c" (ecx), "d"(edx));
 299 }
 300
 301 static inline void __mwait(unsigned long eax, unsigned long ecx)
 302 {
 303         /* "mwait %eax,%ecx;" */
 304         asm volatile(
 305                 ".byte 0x0f,0x01,0xc9;"
 306                 : :"a" (eax), "c" (ecx));
 307 }
 308
 309 /* from system description table in BIOS.  Mostly for MCA use, but
 310 others may find it useful. */
 311 extern unsigned int machine_id;
 312 extern unsigned int machine_submodel_id;
 313 extern unsigned int BIOS_revision;
 314 extern unsigned int mca_pentium_flag;
 315
 316 /* Boot loader type from the setup header */
 317 extern int bootloader_type;
 318
 319 /*
 320  * User space process size: 3GB (default).
 321  */
 322 #define TASK_SIZE       (PAGE_OFFSET)
 323
 324 /* This decides where the kernel will search for a free chunk of vm
 325  * space during mmap's.
 326  */
 327 #define TASK_UNMAPPED_BASE      (PAGE_ALIGN(TASK_SIZE / 3))
 328
 329 #define HAVE_ARCH_PICK_MMAP_LAYOUT
 330
 331 /*
 332  * Size of io_bitmap.
 333  */
 334 #define IO_BITMAP_BITS  65536
 335 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
 336 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
 337 #define IO_BITMAP_OFFSET offsetof(struct tss_struct,io_bitmap)
 338 #define INVALID_IO_BITMAP_OFFSET 0x8000
 339 #define INVALID_IO_BITMAP_OFFSET_LAZY 0x9000
 340
 341 struct i387_fsave_struct {
 342         long    cwd;
 343         long    swd;
 344         long    twd;
 345         long    fip;
 346         long    fcs;
 347         long    foo;
 348         long    fos;
 349         long    st_space[20];   /* 8*10 bytes for each FP-reg = 80 bytes */
 350         long    status;         /* software status information */
 351 };
 352
 353 struct i387_fxsave_struct {
 354         unsigned short  cwd;
 355         unsigned short  swd;
 356         unsigned short  twd;
 357         unsigned short  fop;
 358         long    fip;
 359         long    fcs;
 360         long    foo;
 361         long    fos;
 362         long    mxcsr;
 363         long    mxcsr_mask;
 364         long    st_space[32];   /* 8*16 bytes for each FP-reg = 128 bytes */
 365         long    xmm_space[32];  /* 8*16 bytes for each XMM-reg = 128 bytes */
 366         long    padding[56];
 367 } __attribute__ ((aligned (16)));
 368
 369 struct i387_soft_struct {
 370         long    cwd;
 371         long    swd;
 372         long    twd;
 373         long    fip;
 374         long    fcs;
 375         long    foo;
 376         long    fos;
 377         long    st_space[20];   /* 8*10 bytes for each FP-reg = 80 bytes */
 378         unsigned char   ftop, changed, lookahead, no_update, rm, alimit;
 379         struct info     *info;
 380         unsigned long   entry_eip;
 381 };
 382
 383 union i387_union {
 384         struct i387_fsave_struct        fsave;
 385         struct i387_fxsave_struct       fxsave;
 386         struct i387_soft_struct soft;
 387 };
 388
 389 typedef struct {
 390         unsigned long seg;
 391 } mm_segment_t;
 392
 393 struct thread_struct;
 394
 395 struct tss_struct {
 396         unsigned short  back_link,__blh;
 397         unsigned long   esp0;
 398         unsigned short  ss0,__ss0h;
 399         unsigned long   esp1;
 400         unsigned short  ss1,__ss1h;     /* ss1 is used to cache MSR_IA32_SYSENTER_CS */
 401         unsigned long   esp2;
 402         unsigned short  ss2,__ss2h;
 403         unsigned long   __cr3;
 404         unsigned long   eip;
 405         unsigned long   eflags;
 406         unsigned long   eax,ecx,edx,ebx;
 407         unsigned long   esp;
 408         unsigned long   ebp;
 409         unsigned long   esi;
 410         unsigned long   edi;
 411         unsigned short  es, __esh;
 412         unsigned short  cs, __csh;
 413         unsigned short  ss, __ssh;
 414         unsigned short  ds, __dsh;
 415         unsigned short  fs, __fsh;
 416         unsigned short  gs, __gsh;
 417         unsigned short  ldt, __ldth;
 418         unsigned short  trace, io_bitmap_base;
 419         /*
 420          * The extra 1 is there because the CPU will access an
 421          * additional byte beyond the end of the IO permission
 422          * bitmap. The extra byte must be all 1 bits, and must
 423          * be within the limit.
 424          */
 425         unsigned long   io_bitmap[IO_BITMAP_LONGS + 1];
 426         /*
 427          * Cache the current maximum and the last task that used the bitmap:
 428          */
 429         unsigned long io_bitmap_max;
 430         struct thread_struct *io_bitmap_owner;
 431         /*
 432          * pads the TSS to be cacheline-aligned (size is 0x100)
 433          */
 434         unsigned long __cacheline_filler[35];
 435         /*
 436          * .. and then another 0x100 bytes for emergency kernel stack
 437          */
 438         unsigned long stack[64];
 439 } __attribute__((packed));
 440
 441 #define ARCH_MIN_TASKALIGN      16
 442
 443 struct thread_struct {
 444 /* cached TLS descriptors. */
 445         struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
 446         unsigned long   esp0;
 447         unsigned long   sysenter_cs;
 448         unsigned long   eip;
 449         unsigned long   esp;
 450         unsigned long   fs;
 451         unsigned long   gs;
 452 /* Hardware debugging registers */
 453         unsigned long   debugreg[8];  /* %%db0-7 debug registers */
 454 /* fault info */
 455         unsigned long   cr2, trap_no, error_code;
 456 /* floating point info */
 457         union i387_union        i387;
 458 /* virtual 86 mode info */
 459         struct vm86_struct __user * vm86_info;
 460         unsigned long           screen_bitmap;
 461         unsigned long           v86flags, v86mask, saved_esp0;
 462         unsigned int            saved_fs, saved_gs;
 463 /* IO permissions */
 464         unsigned long   *io_bitmap_ptr;
 465         unsigned long   iopl;
 466 /* max allowed port in the bitmap, in bytes: */
 467         unsigned long   io_bitmap_max;
 468 };
 469
 470 #define INIT_THREAD  {                                                  \
 471         .vm86_info = NULL,                                              \
 472         .sysenter_cs = __KERNEL_CS,                                     \
 473         .io_bitmap_ptr = NULL,                                          \
 474 }
 475
 476 /*
 477  * Note that the .io_bitmap member must be extra-big. This is because
 478  * the CPU will access an additional byte beyond the end of the IO
 479  * permission bitmap. The extra byte must be all 1 bits, and must
 480  * be within the limit.
 481  */
 482 #define INIT_TSS  {                                                     \
 483         .esp0           = sizeof(init_stack) + (long)&init_stack,       \
 484         .ss0            = __KERNEL_DS,                                  \
 485         .ss1            = __KERNEL_CS,                                  \
 486         .io_bitmap_base = INVALID_IO_BITMAP_OFFSET,                     \
 487         .io_bitmap      = { [ 0 ... IO_BITMAP_LONGS] = ~0 },            \
 488 }
 489
 490 static inline void load_esp0(struct tss_struct *tss, struct thread_struct *thread)
 491 {
 492         tss->esp0 = thread->esp0;
 493         /* This can only happen when SEP is enabled, no need to test "SEP"arately */
 494         if (unlikely(tss->ss1 != thread->sysenter_cs)) {
 495                 tss->ss1 = thread->sysenter_cs;
 496                 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
 497         }
 498 }
 499
 500 #define start_thread(regs, new_eip, new_esp) do {               \
 501         __asm__("movl %0,%%fs ; movl %0,%%gs": :"r" (0));       \
 502         set_fs(USER_DS);                                        \
 503         regs->xds = __USER_DS;                                  \
 504         regs->xes = __USER_DS;                                  \
 505         regs->xss = __USER_DS;                                  \
 506         regs->xcs = __USER_CS;                                  \
 507         regs->eip = new_eip;                                    \
 508         regs->esp = new_esp;                                    \
 509 } while (0)
 510
 511 /*
 512  * These special macros can be used to get or set a debugging register
 513  */
 514 #define get_debugreg(var, register)                             \
 515                 __asm__("movl %%db" #register ", %0"            \
 516                         :"=r" (var))
 517 #define set_debugreg(value, register)                   \
 518                 __asm__("movl %0,%%db" #register                \
 519                         : /* no output */                       \
 520                         :"r" (value))
 521
 522 /*
 523  * Set IOPL bits in EFLAGS from given mask
 524  */
 525 static inline void set_iopl_mask(unsigned mask)
 526 {
 527         unsigned int reg;
 528         __asm__ __volatile__ ("pushfl;"
 529                               "popl %0;"
 530                               "andl %1, %0;"
 531                               "orl %2, %0;"
 532                               "pushl %0;"
 533                               "popfl"
 534                                 : "=&r" (reg)
 535                                 : "i" (~X86_EFLAGS_IOPL), "r" (mask));
 536 }
 537
 538 /* Forward declaration, a strange C thing */
 539 struct task_struct;
 540 struct mm_struct;
 541
 542 /* Free all resources held by a thread. */
 543 extern void release_thread(struct task_struct *);
 544
 545 /* Prepare to copy thread state - unlazy all lazy status */
 546 extern void prepare_to_copy(struct task_struct *tsk);
 547
 548 /*
 549  * create a kernel thread without removing it from tasklists
 550  */
 551 extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
 552
 553 extern unsigned long thread_saved_pc(struct task_struct *tsk);
 554 void show_trace(struct task_struct *task, struct pt_regs *regs, unsigned long *stack);
 555
 556 unsigned long get_wchan(struct task_struct *p);
 557
 558 #define THREAD_SIZE_LONGS      (THREAD_SIZE/sizeof(unsigned long))
 559 #define KSTK_TOP(info)                                                 \
 560 ({                                                                     \
 561        unsigned long *__ptr = (unsigned long *)(info);                 \
 562        (unsigned long)(&__ptr[THREAD_SIZE_LONGS]);                     \
 563 })
 564
 565 /*
 566  * The below -8 is to reserve 8 bytes on top of the ring0 stack.
 567  * This is necessary to guarantee that the entire "struct pt_regs"
 568  * is accessable even if the CPU haven't stored the SS/ESP registers
 569  * on the stack (interrupt gate does not save these registers
 570  * when switching to the same priv ring).
 571  * Therefore beware: accessing the xss/esp fields of the
 572  * "struct pt_regs" is possible, but they may contain the
 573  * completely wrong values.
 574  */
 575 #define task_pt_regs(task)                                             \
 576 ({                                                                     \
 577        struct pt_regs *__regs__;                                       \
 578        __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \
 579        __regs__ - 1;                                                   \
 580 })
 581
 582 #define KSTK_EIP(task) (task_pt_regs(task)->eip)
 583 #define KSTK_ESP(task) (task_pt_regs(task)->esp)
 584
 585
 586 struct microcode_header {
 587         unsigned int hdrver;
 588         unsigned int rev;
 589         unsigned int date;
 590         unsigned int sig;
 591         unsigned int cksum;
 592         unsigned int ldrver;
 593         unsigned int pf;
 594         unsigned int datasize;
 595         unsigned int totalsize;
 596         unsigned int reserved[3];
 597 };
 598
 599 struct microcode {
 600         struct microcode_header hdr;
 601         unsigned int bits[0];
 602 };
 603
 604 typedef struct microcode microcode_t;
 605 typedef struct microcode_header microcode_header_t;
 606
 607 /* microcode format is extended from prescott processors */
 608 struct extended_signature {
 609         unsigned int sig;
 610         unsigned int pf;
 611         unsigned int cksum;
 612 };
 613
 614 struct extended_sigtable {
 615         unsigned int count;
 616         unsigned int cksum;
 617         unsigned int reserved[3];
 618         struct extended_signature sigs[0];
 619 };
 620
 621 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
 622 static inline void rep_nop(void)
 623 {
 624         __asm__ __volatile__("rep;nop": : :"memory");
 625 }
 626
 627 #define cpu_relax()     rep_nop()
 628
 629 /* generic versions from gas */
 630 #define GENERIC_NOP1    ".byte 0x90\n"
 631 #define GENERIC_NOP2            ".byte 0x89,0xf6\n"
 632 #define GENERIC_NOP3        ".byte 0x8d,0x76,0x00\n"
 633 #define GENERIC_NOP4        ".byte 0x8d,0x74,0x26,0x00\n"
 634 #define GENERIC_NOP5        GENERIC_NOP1 GENERIC_NOP4
 635 #define GENERIC_NOP6    ".byte 0x8d,0xb6,0x00,0x00,0x00,0x00\n"
 636 #define GENERIC_NOP7    ".byte 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00\n"
 637 #define GENERIC_NOP8    GENERIC_NOP1 GENERIC_NOP7
 638
 639 /* Opteron nops */
 640 #define K8_NOP1 GENERIC_NOP1
 641 #define K8_NOP2 ".byte 0x66,0x90\n"
 642 #define K8_NOP3 ".byte 0x66,0x66,0x90\n"
 643 #define K8_NOP4 ".byte 0x66,0x66,0x66,0x90\n"
 644 #define K8_NOP5 K8_NOP3 K8_NOP2
 645 #define K8_NOP6 K8_NOP3 K8_NOP3
 646 #define K8_NOP7 K8_NOP4 K8_NOP3
 647 #define K8_NOP8 K8_NOP4 K8_NOP4
 648
 649 /* K7 nops */
 650 /* uses eax dependencies (arbitary choice) */
 651 #define K7_NOP1  GENERIC_NOP1
 652 #define K7_NOP2 ".byte 0x8b,0xc0\n"
 653 #define K7_NOP3 ".byte 0x8d,0x04,0x20\n"
 654 #define K7_NOP4 ".byte 0x8d,0x44,0x20,0x00\n"
 655 #define K7_NOP5 K7_NOP4 ASM_NOP1
 656 #define K7_NOP6 ".byte 0x8d,0x80,0,0,0,0\n"
 657 #define K7_NOP7        ".byte 0x8D,0x04,0x05,0,0,0,0\n"
 658 #define K7_NOP8        K7_NOP7 ASM_NOP1
 659
 660 #ifdef CONFIG_MK8
 661 #define ASM_NOP1 K8_NOP1
 662 #define ASM_NOP2 K8_NOP2
 663 #define ASM_NOP3 K8_NOP3
 664 #define ASM_NOP4 K8_NOP4
 665 #define ASM_NOP5 K8_NOP5
 666 #define ASM_NOP6 K8_NOP6
 667 #define ASM_NOP7 K8_NOP7
 668 #define ASM_NOP8 K8_NOP8
 669 #elif defined(CONFIG_MK7)
 670 #define ASM_NOP1 K7_NOP1
 671 #define ASM_NOP2 K7_NOP2
 672 #define ASM_NOP3 K7_NOP3
 673 #define ASM_NOP4 K7_NOP4
 674 #define ASM_NOP5 K7_NOP5
 675 #define ASM_NOP6 K7_NOP6
 676 #define ASM_NOP7 K7_NOP7
 677 #define ASM_NOP8 K7_NOP8
 678 #else
 679 #define ASM_NOP1 GENERIC_NOP1
 680 #define ASM_NOP2 GENERIC_NOP2
 681 #define ASM_NOP3 GENERIC_NOP3
 682 #define ASM_NOP4 GENERIC_NOP4
 683 #define ASM_NOP5 GENERIC_NOP5
 684 #define ASM_NOP6 GENERIC_NOP6
 685 #define ASM_NOP7 GENERIC_NOP7
 686 #define ASM_NOP8 GENERIC_NOP8
 687 #endif
 688
 689 #define ASM_NOP_MAX 8
 690
 691 /* Prefetch instructions for Pentium III and AMD Athlon */
 692 /* It's not worth to care about 3dnow! prefetches for the K6
 693    because they are microcoded there and very slow.
 694    However we don't do prefetches for pre XP Athlons currently
 695    That should be fixed. */
 696 #define ARCH_HAS_PREFETCH
 697 static inline void prefetch(const void *x)
 698 {
 699         alternative_input(ASM_NOP4,
 700                           "prefetchnta (%1)",
 701                           X86_FEATURE_XMM,
 702                           "r" (x));
 703 }
 704
 705 #define ARCH_HAS_PREFETCH
 706 #define ARCH_HAS_PREFETCHW
 707 #define ARCH_HAS_SPINLOCK_PREFETCH
 708
 709 /* 3dnow! prefetch to get an exclusive cache line. Useful for
 710    spinlocks to avoid one state transition in the cache coherency protocol. */
 711 static inline void prefetchw(const void *x)
 712 {
 713         alternative_input(ASM_NOP4,
 714                           "prefetchw (%1)",
 715                           X86_FEATURE_3DNOW,
 716                           "r" (x));
 717 }
 718 #define spin_lock_prefetch(x)   prefetchw(x)
 719
 720 extern void select_idle_routine(const struct cpuinfo_x86 *c);
 721
 722 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
 723
 724 extern unsigned long boot_option_idle_override;
 725 extern void enable_sep_cpu(void);
 726 extern int sysenter_setup(void);
 727
 728 #endif /* __ASM_I386_PROCESSOR_H */