drivers/net/ucc_geth_phy.h

   1 /*
   2  * Copyright (C) Freescale Semicondutor, Inc. 2006. All rights reserved.
   3  *
   4  * Author: Shlomi Gridish <gridish@freescale.com>
   5  *
   6  * Description:
   7  * UCC GETH Driver -- PHY handling
   8  *
   9  * Changelog:
  10  * Jun 28, 2006 Li Yang <LeoLi@freescale.com>
  11  * - Rearrange code and style fixes
  12  *
  13  * This program is free software; you can redistribute  it and/or modify it
  14  * under  the terms of  the GNU General  Public License as published by the
  15  * Free Software Foundation;  either version 2 of the  License, or (at your
  16  * option) any later version.
  17  *
  18  */
  19 #ifndef __UCC_GETH_PHY_H__
  20 #define __UCC_GETH_PHY_H__
  21
  22 #define MII_end ((u32)-2)
  23 #define MII_read ((u32)-1)
  24
  25 #define MIIMIND_BUSY            0x00000001
  26 #define MIIMIND_NOTVALID        0x00000004
  27
  28 #define UGETH_AN_TIMEOUT        2000
  29
  30 /* 1000BT control (Marvell & BCM54xx at least) */
  31 #define MII_1000BASETCONTROL                  0x09
  32 #define MII_1000BASETCONTROL_FULLDUPLEXCAP    0x0200
  33 #define MII_1000BASETCONTROL_HALFDUPLEXCAP    0x0100
  34
  35 /* Cicada Extended Control Register 1 */
  36 #define MII_CIS8201_EXT_CON1        0x17
  37 #define MII_CIS8201_EXTCON1_INIT    0x0000
  38
  39 /* Cicada Interrupt Mask Register */
  40 #define MII_CIS8201_IMASK           0x19
  41 #define MII_CIS8201_IMASK_IEN       0x8000
  42 #define MII_CIS8201_IMASK_SPEED     0x4000
  43 #define MII_CIS8201_IMASK_LINK      0x2000
  44 #define MII_CIS8201_IMASK_DUPLEX    0x1000
  45 #define MII_CIS8201_IMASK_MASK      0xf000
  46
  47 /* Cicada Interrupt Status Register */
  48 #define MII_CIS8201_ISTAT           0x1a
  49 #define MII_CIS8201_ISTAT_STATUS    0x8000
  50 #define MII_CIS8201_ISTAT_SPEED     0x4000
  51 #define MII_CIS8201_ISTAT_LINK      0x2000
  52 #define MII_CIS8201_ISTAT_DUPLEX    0x1000
  53
  54 /* Cicada Auxiliary Control/Status Register */
  55 #define MII_CIS8201_AUX_CONSTAT        0x1c
  56 #define MII_CIS8201_AUXCONSTAT_INIT    0x0004
  57 #define MII_CIS8201_AUXCONSTAT_DUPLEX  0x0020
  58 #define MII_CIS8201_AUXCONSTAT_SPEED   0x0018
  59 #define MII_CIS8201_AUXCONSTAT_GBIT    0x0010
  60 #define MII_CIS8201_AUXCONSTAT_100     0x0008
  61
  62 /* 88E1011 PHY Status Register */
  63 #define MII_M1011_PHY_SPEC_STATUS               0x11
  64 #define MII_M1011_PHY_SPEC_STATUS_1000          0x8000
  65 #define MII_M1011_PHY_SPEC_STATUS_100           0x4000
  66 #define MII_M1011_PHY_SPEC_STATUS_SPD_MASK      0xc000
  67 #define MII_M1011_PHY_SPEC_STATUS_FULLDUPLEX    0x2000
  68 #define MII_M1011_PHY_SPEC_STATUS_RESOLVED      0x0800
  69 #define MII_M1011_PHY_SPEC_STATUS_LINK          0x0400
  70
  71 #define MII_M1011_IEVENT                0x13
  72 #define MII_M1011_IEVENT_CLEAR          0x0000
  73
  74 #define MII_M1011_IMASK                 0x12
  75 #define MII_M1011_IMASK_INIT            0x6400
  76 #define MII_M1011_IMASK_CLEAR           0x0000
  77
  78 #define MII_DM9161_SCR                  0x10
  79 #define MII_DM9161_SCR_INIT             0x0610
  80
  81 /* DM9161 Specified Configuration and Status Register */
  82 #define MII_DM9161_SCSR                 0x11
  83 #define MII_DM9161_SCSR_100F            0x8000
  84 #define MII_DM9161_SCSR_100H            0x4000
  85 #define MII_DM9161_SCSR_10F             0x2000
  86 #define MII_DM9161_SCSR_10H             0x1000
  87
  88 /* DM9161 Interrupt Register */
  89 #define MII_DM9161_INTR                 0x15
  90 #define MII_DM9161_INTR_PEND            0x8000
  91 #define MII_DM9161_INTR_DPLX_MASK       0x0800
  92 #define MII_DM9161_INTR_SPD_MASK        0x0400
  93 #define MII_DM9161_INTR_LINK_MASK       0x0200
  94 #define MII_DM9161_INTR_MASK            0x0100
  95 #define MII_DM9161_INTR_DPLX_CHANGE     0x0010
  96 #define MII_DM9161_INTR_SPD_CHANGE      0x0008
  97 #define MII_DM9161_INTR_LINK_CHANGE     0x0004
  98 #define MII_DM9161_INTR_INIT            0x0000
  99 #define MII_DM9161_INTR_STOP    \
 100 (MII_DM9161_INTR_DPLX_MASK | MII_DM9161_INTR_SPD_MASK \
 101  | MII_DM9161_INTR_LINK_MASK | MII_DM9161_INTR_MASK)
 102
 103 /* DM9161 10BT Configuration/Status */
 104 #define MII_DM9161_10BTCSR              0x12
 105 #define MII_DM9161_10BTCSR_INIT         0x7800
 106
 107 #define MII_BASIC_FEATURES    (SUPPORTED_10baseT_Half | \
 108                  SUPPORTED_10baseT_Full | \
 109                  SUPPORTED_100baseT_Half | \
 110                  SUPPORTED_100baseT_Full | \
 111                  SUPPORTED_Autoneg | \
 112                  SUPPORTED_TP | \
 113                  SUPPORTED_MII)
 114
 115 #define MII_GBIT_FEATURES    (MII_BASIC_FEATURES | \
 116                  SUPPORTED_1000baseT_Half | \
 117                  SUPPORTED_1000baseT_Full)
 118
 119 #define MII_READ_COMMAND                0x00000001
 120
 121 #define MII_INTERRUPT_DISABLED          0x0
 122 #define MII_INTERRUPT_ENABLED           0x1
 123 /* Taken from mii_if_info and sungem_phy.h */
 124 struct ugeth_mii_info {
 125         /* Information about the PHY type */
 126         /* And management functions */
 127         struct phy_info *phyinfo;
 128
 129         struct ucc_mii_mng *mii_regs;
 130
 131         /* forced speed & duplex (no autoneg)
 132          * partner speed & duplex & pause (autoneg)
 133          */
 134         int speed;
 135         int duplex;
 136         int pause;
 137
 138         /* The most recently read link state */
 139         int link;
 140
 141         /* Enabled Interrupts */
 142         u32 interrupts;
 143
 144         u32 advertising;
 145         int autoneg;
 146         int mii_id;
 147
 148         /* private data pointer */
 149         /* For use by PHYs to maintain extra state */
 150         void *priv;
 151
 152         /* Provided by host chip */
 153         struct net_device *dev;
 154
 155         /* A lock to ensure that only one thing can read/write
 156          * the MDIO bus at a time */
 157         spinlock_t mdio_lock;
 158
 159         /* Provided by ethernet driver */
 160         int (*mdio_read) (struct net_device * dev, int mii_id, int reg);
 161         void (*mdio_write) (struct net_device * dev, int mii_id, int reg,
 162                             int val);
 163 };
 164
 165 /* struct phy_info: a structure which defines attributes for a PHY
 166  *
 167  * id will contain a number which represents the PHY.  During
 168  * startup, the driver will poll the PHY to find out what its
 169  * UID--as defined by registers 2 and 3--is.  The 32-bit result
 170  * gotten from the PHY will be ANDed with phy_id_mask to
 171  * discard any bits which may change based on revision numbers
 172  * unimportant to functionality
 173  *
 174  * There are 6 commands which take a ugeth_mii_info structure.
 175  * Each PHY must declare config_aneg, and read_status.
 176  */
 177 struct phy_info {
 178         u32 phy_id;
 179         char *name;
 180         unsigned int phy_id_mask;
 181         u32 features;
 182
 183         /* Called to initialize the PHY */
 184         int (*init) (struct ugeth_mii_info * mii_info);
 185
 186         /* Called to suspend the PHY for power */
 187         int (*suspend) (struct ugeth_mii_info * mii_info);
 188
 189         /* Reconfigures autonegotiation (or disables it) */
 190         int (*config_aneg) (struct ugeth_mii_info * mii_info);
 191
 192         /* Determines the negotiated speed and duplex */
 193         int (*read_status) (struct ugeth_mii_info * mii_info);
 194
 195         /* Clears any pending interrupts */
 196         int (*ack_interrupt) (struct ugeth_mii_info * mii_info);
 197
 198         /* Enables or disables interrupts */
 199         int (*config_intr) (struct ugeth_mii_info * mii_info);
 200
 201         /* Clears up any memory if needed */
 202         void (*close) (struct ugeth_mii_info * mii_info);
 203 };
 204
 205 struct phy_info *get_phy_info(struct ugeth_mii_info *mii_info);
 206 void write_phy_reg(struct net_device *dev, int mii_id, int regnum, int value);
 207 int read_phy_reg(struct net_device *dev, int mii_id, int regnum);
 208 void mii_clear_phy_interrupt(struct ugeth_mii_info *mii_info);
 209 void mii_configure_phy_interrupt(struct ugeth_mii_info *mii_info,
 210                                  u32 interrupts);
 211
 212 struct dm9161_private {
 213         struct timer_list timer;
 214         int resetdone;
 215 };
 216
 217 #endif                          /* __UCC_GETH_PHY_H__ */