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[POWERPC] Fix apparent typo "CONFIG_SERIAL_CPM_SMC".
[usb.git] / drivers / net / meth.c
blobe1d97cdf649eeb6a8d9ac4167dfb0bd4f7dda0da
1 /*
2 * meth.c -- O2 Builtin 10/100 Ethernet driver
3 *
4 * Copyright (C) 2001-2003 Ilya Volynets
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11 #include <linux/module.h>
12 #include <linux/init.h>
13
14 #include <linux/sched.h>
15 #include <linux/kernel.h> /* printk() */
16 #include <linux/delay.h>
17 #include <linux/slab.h>
18 #include <linux/errno.h> /* error codes */
19 #include <linux/types.h> /* size_t */
20 #include <linux/interrupt.h> /* mark_bh */
21
22 #include <linux/in.h>
23 #include <linux/in6.h>
24 #include <linux/device.h> /* struct device, et al */
25 #include <linux/netdevice.h> /* struct device, and other headers */
26 #include <linux/etherdevice.h> /* eth_type_trans */
27 #include <linux/ip.h> /* struct iphdr */
28 #include <linux/tcp.h> /* struct tcphdr */
29 #include <linux/skbuff.h>
30 #include <linux/mii.h> /* MII definitions */
31
32 #include <asm/ip32/mace.h>
33 #include <asm/ip32/ip32_ints.h>
34
35 #include <asm/io.h>
36 #include <asm/scatterlist.h>
37 #include <linux/dma-mapping.h>
38
39 #include "meth.h"
40
41 #ifndef MFE_DEBUG
42 #define MFE_DEBUG 0
43 #endif
44
45 #if MFE_DEBUG>=1
46 #define DPRINTK(str,args...) printk(KERN_DEBUG "meth: %s: " str, __FUNCTION__ , ## args)
47 #define MFE_RX_DEBUG 2
48 #else
49 #define DPRINTK(str,args...)
50 #define MFE_RX_DEBUG 0
51 #endif
52
53
54 static const char *meth_str="SGI O2 Fast Ethernet";
55 MODULE_AUTHOR("Ilya Volynets <ilya@theIlya.com>");
56 MODULE_DESCRIPTION("SGI O2 Builtin Fast Ethernet driver");
57
58 #define HAVE_TX_TIMEOUT
59 /* The maximum time waited (in jiffies) before assuming a Tx failed. (400ms) */
60 #define TX_TIMEOUT (400*HZ/1000)
61
62 #ifdef HAVE_TX_TIMEOUT
63 static int timeout = TX_TIMEOUT;
64 module_param(timeout, int, 0);
65 #endif
66
67 /*
68 * This structure is private to each device. It is used to pass
69 * packets in and out, so there is place for a packet
70 */
71 struct meth_private {
72 struct net_device_stats stats;
73 /* in-memory copy of MAC Control register */
74 unsigned long mac_ctrl;
75 /* in-memory copy of DMA Control register */
76 unsigned long dma_ctrl;
77 /* address of PHY, used by mdio_* functions, initialized in mdio_probe */
78 unsigned long phy_addr;
79 tx_packet *tx_ring;
80 dma_addr_t tx_ring_dma;
81 struct sk_buff *tx_skbs[TX_RING_ENTRIES];
82 dma_addr_t tx_skb_dmas[TX_RING_ENTRIES];
83 unsigned long tx_read, tx_write, tx_count;
84
85 rx_packet *rx_ring[RX_RING_ENTRIES];
86 dma_addr_t rx_ring_dmas[RX_RING_ENTRIES];
87 struct sk_buff *rx_skbs[RX_RING_ENTRIES];
88 unsigned long rx_write;
89
90 spinlock_t meth_lock;
91 };
92
93 static void meth_tx_timeout(struct net_device *dev);
94 static irqreturn_t meth_interrupt(int irq, void *dev_id);
95
96 /* global, initialized in ip32-setup.c */
97 char o2meth_eaddr[8]={0,0,0,0,0,0,0,0};
98
99 static inline void load_eaddr(struct net_device *dev)
100 {
101 int i;
102 DPRINTK("Loading MAC Address: %02x:%02x:%02x:%02x:%02x:%02x\n",
103 (int)o2meth_eaddr[0]&0xFF,(int)o2meth_eaddr[1]&0xFF,(int)o2meth_eaddr[2]&0xFF,
104 (int)o2meth_eaddr[3]&0xFF,(int)o2meth_eaddr[4]&0xFF,(int)o2meth_eaddr[5]&0xFF);
105 for (i = 0; i < 6; i++)
106 dev->dev_addr[i] = o2meth_eaddr[i];
107 mace->eth.mac_addr = (*(unsigned long*)o2meth_eaddr) >> 16;
108 }
109
110 /*
111 * Waits for BUSY status of mdio bus to clear
112 */
113 #define WAIT_FOR_PHY(___rval) \
114 while ((___rval = mace->eth.phy_data) & MDIO_BUSY) { \
115 udelay(25); \
116 }
117 /*read phy register, return value read */
118 static unsigned long mdio_read(struct meth_private *priv, unsigned long phyreg)
119 {
120 unsigned long rval;
121 WAIT_FOR_PHY(rval);
122 mace->eth.phy_regs = (priv->phy_addr << 5) | (phyreg & 0x1f);
123 udelay(25);
124 mace->eth.phy_trans_go = 1;
125 udelay(25);
126 WAIT_FOR_PHY(rval);
127 return rval & MDIO_DATA_MASK;
128 }
129
130 static int mdio_probe(struct meth_private *priv)
131 {
132 int i;
133 unsigned long p2, p3;
134 /* check if phy is detected already */
135 if(priv->phy_addr>=0&&priv->phy_addr<32)
136 return 0;
137 spin_lock(&priv->meth_lock);
138 for (i=0;i<32;++i){
139 priv->phy_addr=i;
140 p2=mdio_read(priv,2);
141 p3=mdio_read(priv,3);
142 #if MFE_DEBUG>=2
143 switch ((p2<<12)|(p3>>4)){
144 case PHY_QS6612X:
145 DPRINTK("PHY is QS6612X\n");
146 break;
147 case PHY_ICS1889:
148 DPRINTK("PHY is ICS1889\n");
149 break;
150 case PHY_ICS1890:
151 DPRINTK("PHY is ICS1890\n");
152 break;
153 case PHY_DP83840:
154 DPRINTK("PHY is DP83840\n");
155 break;
156 }
157 #endif
158 if(p2!=0xffff&&p2!=0x0000){
159 DPRINTK("PHY code: %x\n",(p2<<12)|(p3>>4));
160 break;
161 }
162 }
163 spin_unlock(&priv->meth_lock);
164 if(priv->phy_addr<32) {
165 return 0;
166 }
167 DPRINTK("Oopsie! PHY is not known!\n");
168 priv->phy_addr=-1;
169 return -ENODEV;
170 }
171
172 static void meth_check_link(struct net_device *dev)
173 {
174 struct meth_private *priv = (struct meth_private *) dev->priv;
175 unsigned long mii_advertising = mdio_read(priv, 4);
176 unsigned long mii_partner = mdio_read(priv, 5);
177 unsigned long negotiated = mii_advertising & mii_partner;
178 unsigned long duplex, speed;
179
180 if (mii_partner == 0xffff)
181 return;
182
183 speed = (negotiated & 0x0380) ? METH_100MBIT : 0;
184 duplex = ((negotiated & 0x0100) || (negotiated & 0x01C0) == 0x0040) ?
185 METH_PHY_FDX : 0;
186
187 if ((priv->mac_ctrl & METH_PHY_FDX) ^ duplex) {
188 DPRINTK("Setting %s-duplex\n", duplex ? "full" : "half");
189 if (duplex)
190 priv->mac_ctrl |= METH_PHY_FDX;
191 else
192 priv->mac_ctrl &= ~METH_PHY_FDX;
193 mace->eth.mac_ctrl = priv->mac_ctrl;
194 }
195
196 if ((priv->mac_ctrl & METH_100MBIT) ^ speed) {
197 DPRINTK("Setting %dMbs mode\n", speed ? 100 : 10);
198 if (duplex)
199 priv->mac_ctrl |= METH_100MBIT;
200 else
201 priv->mac_ctrl &= ~METH_100MBIT;
202 mace->eth.mac_ctrl = priv->mac_ctrl;
203 }
204 }
205
206
207 static int meth_init_tx_ring(struct meth_private *priv)
208 {
209 /* Init TX ring */
210 priv->tx_ring = dma_alloc_coherent(NULL, TX_RING_BUFFER_SIZE,
211 &priv->tx_ring_dma, GFP_ATOMIC);
212 if (!priv->tx_ring)
213 return -ENOMEM;
214 memset(priv->tx_ring, 0, TX_RING_BUFFER_SIZE);
215 priv->tx_count = priv->tx_read = priv->tx_write = 0;
216 mace->eth.tx_ring_base = priv->tx_ring_dma;
217 /* Now init skb save area */
218 memset(priv->tx_skbs, 0, sizeof(priv->tx_skbs));
219 memset(priv->tx_skb_dmas, 0, sizeof(priv->tx_skb_dmas));
220 return 0;
221 }
222
223 static int meth_init_rx_ring(struct meth_private *priv)
224 {
225 int i;
226
227 for (i = 0; i < RX_RING_ENTRIES; i++) {
228 priv->rx_skbs[i] = alloc_skb(METH_RX_BUFF_SIZE, 0);
229 /* 8byte status vector + 3quad padding + 2byte padding,
230 * to put data on 64bit aligned boundary */
231 skb_reserve(priv->rx_skbs[i],METH_RX_HEAD);
232 priv->rx_ring[i]=(rx_packet*)(priv->rx_skbs[i]->head);
233 /* I'll need to re-sync it after each RX */
234 priv->rx_ring_dmas[i] =
235 dma_map_single(NULL, priv->rx_ring[i],
236 METH_RX_BUFF_SIZE, DMA_FROM_DEVICE);
237 mace->eth.rx_fifo = priv->rx_ring_dmas[i];
238 }
239 priv->rx_write = 0;
240 return 0;
241 }
242 static void meth_free_tx_ring(struct meth_private *priv)
243 {
244 int i;
245
246 /* Remove any pending skb */
247 for (i = 0; i < TX_RING_ENTRIES; i++) {
248 if (priv->tx_skbs[i])
249 dev_kfree_skb(priv->tx_skbs[i]);
250 priv->tx_skbs[i] = NULL;
251 }
252 dma_free_coherent(NULL, TX_RING_BUFFER_SIZE, priv->tx_ring,
253 priv->tx_ring_dma);
254 }
255
256 /* Presumes RX DMA engine is stopped, and RX fifo ring is reset */
257 static void meth_free_rx_ring(struct meth_private *priv)
258 {
259 int i;
260
261 for (i = 0; i < RX_RING_ENTRIES; i++) {
262 dma_unmap_single(NULL, priv->rx_ring_dmas[i],
263 METH_RX_BUFF_SIZE, DMA_FROM_DEVICE);
264 priv->rx_ring[i] = 0;
265 priv->rx_ring_dmas[i] = 0;
266 kfree_skb(priv->rx_skbs[i]);
267 }
268 }
269
270 int meth_reset(struct net_device *dev)
271 {
272 struct meth_private *priv = (struct meth_private *) dev->priv;
273
274 /* Reset card */
275 mace->eth.mac_ctrl = SGI_MAC_RESET;
276 udelay(1);
277 mace->eth.mac_ctrl = 0;
278 udelay(25);
279
280 /* Load ethernet address */
281 load_eaddr(dev);
282 /* Should load some "errata", but later */
283
284 /* Check for device */
285 if (mdio_probe(priv) < 0) {
286 DPRINTK("Unable to find PHY\n");
287 return -ENODEV;
288 }
289
290 /* Initial mode: 10 | Half-duplex | Accept normal packets */
291 priv->mac_ctrl = METH_ACCEPT_MCAST | METH_DEFAULT_IPG;
292 if (dev->flags | IFF_PROMISC)
293 priv->mac_ctrl |= METH_PROMISC;
294 mace->eth.mac_ctrl = priv->mac_ctrl;
295
296 /* Autonegotiate speed and duplex mode */
297 meth_check_link(dev);
298
299 /* Now set dma control, but don't enable DMA, yet */
300 priv->dma_ctrl = (4 << METH_RX_OFFSET_SHIFT) |
301 (RX_RING_ENTRIES << METH_RX_DEPTH_SHIFT);
302 mace->eth.dma_ctrl = priv->dma_ctrl;
303
304 return 0;
305 }
306
307 /*============End Helper Routines=====================*/
308
309 /*
310 * Open and close
311 */
312 static int meth_open(struct net_device *dev)
313 {
314 struct meth_private *priv = dev->priv;
315 int ret;
316
317 priv->phy_addr = -1; /* No PHY is known yet... */
318
319 /* Initialize the hardware */
320 ret = meth_reset(dev);
321 if (ret < 0)
322 return ret;
323
324 /* Allocate the ring buffers */
325 ret = meth_init_tx_ring(priv);
326 if (ret < 0)
327 return ret;
328 ret = meth_init_rx_ring(priv);
329 if (ret < 0)
330 goto out_free_tx_ring;
331
332 ret = request_irq(dev->irq, meth_interrupt, 0, meth_str, dev);
333 if (ret) {
334 printk(KERN_ERR "%s: Can't get irq %d\n", dev->name, dev->irq);
335 goto out_free_rx_ring;
336 }
337
338 /* Start DMA */
339 priv->dma_ctrl |= METH_DMA_TX_EN | /*METH_DMA_TX_INT_EN |*/
340 METH_DMA_RX_EN | METH_DMA_RX_INT_EN;
341 mace->eth.dma_ctrl = priv->dma_ctrl;
342
343 DPRINTK("About to start queue\n");
344 netif_start_queue(dev);
345
346 return 0;
347
348 out_free_rx_ring:
349 meth_free_rx_ring(priv);
350 out_free_tx_ring:
351 meth_free_tx_ring(priv);
352
353 return ret;
354 }
355
356 static int meth_release(struct net_device *dev)
357 {
358 struct meth_private *priv = dev->priv;
359
360 DPRINTK("Stopping queue\n");
361 netif_stop_queue(dev); /* can't transmit any more */
362 /* shut down DMA */
363 priv->dma_ctrl &= ~(METH_DMA_TX_EN | METH_DMA_TX_INT_EN |
364 METH_DMA_RX_EN | METH_DMA_RX_INT_EN);
365 mace->eth.dma_ctrl = priv->dma_ctrl;
366 free_irq(dev->irq, dev);
367 meth_free_tx_ring(priv);
368 meth_free_rx_ring(priv);
369
370 return 0;
371 }
372
373 /*
374 * Receive a packet: retrieve, encapsulate and pass over to upper levels
375 */
376 static void meth_rx(struct net_device* dev, unsigned long int_status)
377 {
378 struct sk_buff *skb;
379 unsigned long status;
380 struct meth_private *priv = (struct meth_private *) dev->priv;
381 unsigned long fifo_rptr = (int_status & METH_INT_RX_RPTR_MASK) >> 8;
382
383 spin_lock(&priv->meth_lock);
384 priv->dma_ctrl &= ~METH_DMA_RX_INT_EN;
385 mace->eth.dma_ctrl = priv->dma_ctrl;
386 spin_unlock(&priv->meth_lock);
387
388 if (int_status & METH_INT_RX_UNDERFLOW) {
389 fifo_rptr = (fifo_rptr - 1) & 0x0f;
390 }
391 while (priv->rx_write != fifo_rptr) {
392 dma_unmap_single(NULL, priv->rx_ring_dmas[priv->rx_write],
393 METH_RX_BUFF_SIZE, DMA_FROM_DEVICE);
394 status = priv->rx_ring[priv->rx_write]->status.raw;
395 #if MFE_DEBUG
396 if (!(status & METH_RX_ST_VALID)) {
397 DPRINTK("Not received? status=%016lx\n",status);
398 }
399 #endif
400 if ((!(status & METH_RX_STATUS_ERRORS)) && (status & METH_RX_ST_VALID)) {
401 int len = (status & 0xffff) - 4; /* omit CRC */
402 /* length sanity check */
403 if (len < 60 || len > 1518) {
404 printk(KERN_DEBUG "%s: bogus packet size: %ld, status=%#2lx.\n",
405 dev->name, priv->rx_write,
406 priv->rx_ring[priv->rx_write]->status.raw);
407 priv->stats.rx_errors++;
408 priv->stats.rx_length_errors++;
409 skb = priv->rx_skbs[priv->rx_write];
410 } else {
411 skb = alloc_skb(METH_RX_BUFF_SIZE, GFP_ATOMIC | GFP_DMA);
412 if (!skb) {
413 /* Ouch! No memory! Drop packet on the floor */
414 DPRINTK("No mem: dropping packet\n");
415 priv->stats.rx_dropped++;
416 skb = priv->rx_skbs[priv->rx_write];
417 } else {
418 struct sk_buff *skb_c = priv->rx_skbs[priv->rx_write];
419 /* 8byte status vector + 3quad padding + 2byte padding,
420 * to put data on 64bit aligned boundary */
421 skb_reserve(skb, METH_RX_HEAD);
422 /* Write metadata, and then pass to the receive level */
423 skb_put(skb_c, len);
424 priv->rx_skbs[priv->rx_write] = skb;
425 skb_c->dev = dev;
426 skb_c->protocol = eth_type_trans(skb_c, dev);
427 dev->last_rx = jiffies;
428 priv->stats.rx_packets++;
429 priv->stats.rx_bytes += len;
430 netif_rx(skb_c);
431 }
432 }
433 } else {
434 priv->stats.rx_errors++;
435 skb=priv->rx_skbs[priv->rx_write];
436 #if MFE_DEBUG>0
437 printk(KERN_WARNING "meth: RX error: status=0x%016lx\n",status);
438 if(status&METH_RX_ST_RCV_CODE_VIOLATION)
439 printk(KERN_WARNING "Receive Code Violation\n");
440 if(status&METH_RX_ST_CRC_ERR)
441 printk(KERN_WARNING "CRC error\n");
442 if(status&METH_RX_ST_INV_PREAMBLE_CTX)
443 printk(KERN_WARNING "Invalid Preamble Context\n");
444 if(status&METH_RX_ST_LONG_EVT_SEEN)
445 printk(KERN_WARNING "Long Event Seen...\n");
446 if(status&METH_RX_ST_BAD_PACKET)
447 printk(KERN_WARNING "Bad Packet\n");
448 if(status&METH_RX_ST_CARRIER_EVT_SEEN)
449 printk(KERN_WARNING "Carrier Event Seen\n");
450 #endif
451 }
452 priv->rx_ring[priv->rx_write] = (rx_packet*)skb->head;
453 priv->rx_ring[priv->rx_write]->status.raw = 0;
454 priv->rx_ring_dmas[priv->rx_write] =
455 dma_map_single(NULL, priv->rx_ring[priv->rx_write],
456 METH_RX_BUFF_SIZE, DMA_FROM_DEVICE);
457 mace->eth.rx_fifo = priv->rx_ring_dmas[priv->rx_write];
458 ADVANCE_RX_PTR(priv->rx_write);
459 }
460 spin_lock(&priv->meth_lock);
461 /* In case there was underflow, and Rx DMA was disabled */
462 priv->dma_ctrl |= METH_DMA_RX_INT_EN | METH_DMA_RX_EN;
463 mace->eth.dma_ctrl = priv->dma_ctrl;
464 mace->eth.int_stat = METH_INT_RX_THRESHOLD;
465 spin_unlock(&priv->meth_lock);
466 }
467
468 static int meth_tx_full(struct net_device *dev)
469 {
470 struct meth_private *priv = (struct meth_private *) dev->priv;
471
472 return (priv->tx_count >= TX_RING_ENTRIES - 1);
473 }
474
475 static void meth_tx_cleanup(struct net_device* dev, unsigned long int_status)
476 {
477 struct meth_private *priv = dev->priv;
478 unsigned long status;
479 struct sk_buff *skb;
480 unsigned long rptr = (int_status&TX_INFO_RPTR) >> 16;
481
482 spin_lock(&priv->meth_lock);
483
484 /* Stop DMA notification */
485 priv->dma_ctrl &= ~(METH_DMA_TX_INT_EN);
486 mace->eth.dma_ctrl = priv->dma_ctrl;
487
488 while (priv->tx_read != rptr) {
489 skb = priv->tx_skbs[priv->tx_read];
490 status = priv->tx_ring[priv->tx_read].header.raw;
491 #if MFE_DEBUG>=1
492 if (priv->tx_read == priv->tx_write)
493 DPRINTK("Auchi! tx_read=%d,tx_write=%d,rptr=%d?\n", priv->tx_read, priv->tx_write,rptr);
494 #endif
495 if (status & METH_TX_ST_DONE) {
496 if (status & METH_TX_ST_SUCCESS){
497 priv->stats.tx_packets++;
498 priv->stats.tx_bytes += skb->len;
499 } else {
500 priv->stats.tx_errors++;
501 #if MFE_DEBUG>=1
502 DPRINTK("TX error: status=%016lx <",status);
503 if(status & METH_TX_ST_SUCCESS)
504 printk(" SUCCESS");
505 if(status & METH_TX_ST_TOOLONG)
506 printk(" TOOLONG");
507 if(status & METH_TX_ST_UNDERRUN)
508 printk(" UNDERRUN");
509 if(status & METH_TX_ST_EXCCOLL)
510 printk(" EXCCOLL");
511 if(status & METH_TX_ST_DEFER)
512 printk(" DEFER");
513 if(status & METH_TX_ST_LATECOLL)
514 printk(" LATECOLL");
515 printk(" >\n");
516 #endif
517 }
518 } else {
519 DPRINTK("RPTR points us here, but packet not done?\n");
520 break;
521 }
522 dev_kfree_skb_irq(skb);
523 priv->tx_skbs[priv->tx_read] = NULL;
524 priv->tx_ring[priv->tx_read].header.raw = 0;
525 priv->tx_read = (priv->tx_read+1)&(TX_RING_ENTRIES-1);
526 priv->tx_count--;
527 }
528
529 /* wake up queue if it was stopped */
530 if (netif_queue_stopped(dev) && !meth_tx_full(dev)) {
531 netif_wake_queue(dev);
532 }
533
534 mace->eth.int_stat = METH_INT_TX_EMPTY | METH_INT_TX_PKT;
535 spin_unlock(&priv->meth_lock);
536 }
537
538 static void meth_error(struct net_device* dev, unsigned status)
539 {
540 struct meth_private *priv = (struct meth_private *) dev->priv;
541
542 printk(KERN_WARNING "meth: error status: 0x%08x\n",status);
543 /* check for errors too... */
544 if (status & (METH_INT_TX_LINK_FAIL))
545 printk(KERN_WARNING "meth: link failure\n");
546 /* Should I do full reset in this case? */
547 if (status & (METH_INT_MEM_ERROR))
548 printk(KERN_WARNING "meth: memory error\n");
549 if (status & (METH_INT_TX_ABORT))
550 printk(KERN_WARNING "meth: aborted\n");
551 if (status & (METH_INT_RX_OVERFLOW))
552 printk(KERN_WARNING "meth: Rx overflow\n");
553 if (status & (METH_INT_RX_UNDERFLOW)) {
554 printk(KERN_WARNING "meth: Rx underflow\n");
555 spin_lock(&priv->meth_lock);
556 mace->eth.int_stat = METH_INT_RX_UNDERFLOW;
557 /* more underflow interrupts will be delivered,
558 * effectively throwing us into an infinite loop.
559 * Thus I stop processing Rx in this case. */
560 priv->dma_ctrl &= ~METH_DMA_RX_EN;
561 mace->eth.dma_ctrl = priv->dma_ctrl;
562 DPRINTK("Disabled meth Rx DMA temporarily\n");
563 spin_unlock(&priv->meth_lock);
564 }
565 mace->eth.int_stat = METH_INT_ERROR;
566 }
567
568 /*
569 * The typical interrupt entry point
570 */
571 static irqreturn_t meth_interrupt(int irq, void *dev_id)
572 {
573 struct net_device *dev = (struct net_device *)dev_id;
574 struct meth_private *priv = (struct meth_private *) dev->priv;
575 unsigned long status;
576
577 status = mace->eth.int_stat;
578 while (status & 0xff) {
579 /* First handle errors - if we get Rx underflow,
580 * Rx DMA will be disabled, and Rx handler will reenable
581 * it. I don't think it's possible to get Rx underflow,
582 * without getting Rx interrupt */
583 if (status & METH_INT_ERROR) {
584 meth_error(dev, status);
585 }
586 if (status & (METH_INT_TX_EMPTY | METH_INT_TX_PKT)) {
587 /* a transmission is over: free the skb */
588 meth_tx_cleanup(dev, status);
589 }
590 if (status & METH_INT_RX_THRESHOLD) {
591 if (!(priv->dma_ctrl & METH_DMA_RX_INT_EN))
592 break;
593 /* send it to meth_rx for handling */
594 meth_rx(dev, status);
595 }
596 status = mace->eth.int_stat;
597 }
598
599 return IRQ_HANDLED;
600 }
601
602 /*
603 * Transmits packets that fit into TX descriptor (are <=120B)
604 */
605 static void meth_tx_short_prepare(struct meth_private *priv,
606 struct sk_buff *skb)
607 {
608 tx_packet *desc = &priv->tx_ring[priv->tx_write];
609 int len = (skb->len < ETH_ZLEN) ? ETH_ZLEN : skb->len;
610
611 desc->header.raw = METH_TX_CMD_INT_EN | (len-1) | ((128-len) << 16);
612 /* maybe I should set whole thing to 0 first... */
613 memcpy(desc->data.dt + (120 - len), skb->data, skb->len);
614 if (skb->len < len)
615 memset(desc->data.dt + 120 - len + skb->len, 0, len-skb->len);
616 }
617 #define TX_CATBUF1 BIT(25)
618 static void meth_tx_1page_prepare(struct meth_private *priv,
619 struct sk_buff *skb)
620 {
621 tx_packet *desc = &priv->tx_ring[priv->tx_write];
622 void *buffer_data = (void *)(((unsigned long)skb->data + 7) & ~7);
623 int unaligned_len = (int)((unsigned long)buffer_data - (unsigned long)skb->data);
624 int buffer_len = skb->len - unaligned_len;
625 dma_addr_t catbuf;
626
627 desc->header.raw = METH_TX_CMD_INT_EN | TX_CATBUF1 | (skb->len - 1);
628
629 /* unaligned part */
630 if (unaligned_len) {
631 memcpy(desc->data.dt + (120 - unaligned_len),
632 skb->data, unaligned_len);
633 desc->header.raw |= (128 - unaligned_len) << 16;
634 }
635
636 /* first page */
637 catbuf = dma_map_single(NULL, buffer_data, buffer_len,
638 DMA_TO_DEVICE);
639 desc->data.cat_buf[0].form.start_addr = catbuf >> 3;
640 desc->data.cat_buf[0].form.len = buffer_len - 1;
641 }
642 #define TX_CATBUF2 BIT(26)
643 static void meth_tx_2page_prepare(struct meth_private *priv,
644 struct sk_buff *skb)
645 {
646 tx_packet *desc = &priv->tx_ring[priv->tx_write];
647 void *buffer1_data = (void *)(((unsigned long)skb->data + 7) & ~7);
648 void *buffer2_data = (void *)PAGE_ALIGN((unsigned long)skb->data);
649 int unaligned_len = (int)((unsigned long)buffer1_data - (unsigned long)skb->data);
650 int buffer1_len = (int)((unsigned long)buffer2_data - (unsigned long)buffer1_data);
651 int buffer2_len = skb->len - buffer1_len - unaligned_len;
652 dma_addr_t catbuf1, catbuf2;
653
654 desc->header.raw = METH_TX_CMD_INT_EN | TX_CATBUF1 | TX_CATBUF2| (skb->len - 1);
655 /* unaligned part */
656 if (unaligned_len){
657 memcpy(desc->data.dt + (120 - unaligned_len),
658 skb->data, unaligned_len);
659 desc->header.raw |= (128 - unaligned_len) << 16;
660 }
661
662 /* first page */
663 catbuf1 = dma_map_single(NULL, buffer1_data, buffer1_len,
664 DMA_TO_DEVICE);
665 desc->data.cat_buf[0].form.start_addr = catbuf1 >> 3;
666 desc->data.cat_buf[0].form.len = buffer1_len - 1;
667 /* second page */
668 catbuf2 = dma_map_single(NULL, buffer2_data, buffer2_len,
669 DMA_TO_DEVICE);
670 desc->data.cat_buf[1].form.start_addr = catbuf2 >> 3;
671 desc->data.cat_buf[1].form.len = buffer2_len - 1;
672 }
673
674 static void meth_add_to_tx_ring(struct meth_private *priv, struct sk_buff *skb)
675 {
676 /* Remember the skb, so we can free it at interrupt time */
677 priv->tx_skbs[priv->tx_write] = skb;
678 if (skb->len <= 120) {
679 /* Whole packet fits into descriptor */
680 meth_tx_short_prepare(priv, skb);
681 } else if (PAGE_ALIGN((unsigned long)skb->data) !=
682 PAGE_ALIGN((unsigned long)skb->data + skb->len - 1)) {
683 /* Packet crosses page boundary */
684 meth_tx_2page_prepare(priv, skb);
685 } else {
686 /* Packet is in one page */
687 meth_tx_1page_prepare(priv, skb);
688 }
689 priv->tx_write = (priv->tx_write + 1) & (TX_RING_ENTRIES - 1);
690 mace->eth.tx_info = priv->tx_write;
691 priv->tx_count++;
692 }
693
694 /*
695 * Transmit a packet (called by the kernel)
696 */
697 static int meth_tx(struct sk_buff *skb, struct net_device *dev)
698 {
699 struct meth_private *priv = (struct meth_private *) dev->priv;
700 unsigned long flags;
701
702 spin_lock_irqsave(&priv->meth_lock, flags);
703 /* Stop DMA notification */
704 priv->dma_ctrl &= ~(METH_DMA_TX_INT_EN);
705 mace->eth.dma_ctrl = priv->dma_ctrl;
706
707 meth_add_to_tx_ring(priv, skb);
708 dev->trans_start = jiffies; /* save the timestamp */
709
710 /* If TX ring is full, tell the upper layer to stop sending packets */
711 if (meth_tx_full(dev)) {
712 printk(KERN_DEBUG "TX full: stopping\n");
713 netif_stop_queue(dev);
714 }
715
716 /* Restart DMA notification */
717 priv->dma_ctrl |= METH_DMA_TX_INT_EN;
718 mace->eth.dma_ctrl = priv->dma_ctrl;
719
720 spin_unlock_irqrestore(&priv->meth_lock, flags);
721
722 return 0;
723 }
724
725 /*
726 * Deal with a transmit timeout.
727 */
728 static void meth_tx_timeout(struct net_device *dev)
729 {
730 struct meth_private *priv = (struct meth_private *) dev->priv;
731 unsigned long flags;
732
733 printk(KERN_WARNING "%s: transmit timed out\n", dev->name);
734
735 /* Protect against concurrent rx interrupts */
736 spin_lock_irqsave(&priv->meth_lock,flags);
737
738 /* Try to reset the interface. */
739 meth_reset(dev);
740
741 priv->stats.tx_errors++;
742
743 /* Clear all rings */
744 meth_free_tx_ring(priv);
745 meth_free_rx_ring(priv);
746 meth_init_tx_ring(priv);
747 meth_init_rx_ring(priv);
748
749 /* Restart dma */
750 priv->dma_ctrl |= METH_DMA_TX_EN | METH_DMA_RX_EN | METH_DMA_RX_INT_EN;
751 mace->eth.dma_ctrl = priv->dma_ctrl;
752
753 /* Enable interrupt */
754 spin_unlock_irqrestore(&priv->meth_lock, flags);
755
756 dev->trans_start = jiffies;
757 netif_wake_queue(dev);
758
759 return;
760 }
761
762 /*
763 * Ioctl commands
764 */
765 static int meth_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
766 {
767 /* XXX Not yet implemented */
768 switch(cmd) {
769 case SIOCGMIIPHY:
770 case SIOCGMIIREG:
771 case SIOCSMIIREG:
772 default:
773 return -EOPNOTSUPP;
774 }
775 }
776
777 /*
778 * Return statistics to the caller
779 */
780 static struct net_device_stats *meth_stats(struct net_device *dev)
781 {
782 struct meth_private *priv = (struct meth_private *) dev->priv;
783 return &priv->stats;
784 }
785
786 /*
787 * The init function.
788 */
789 static struct net_device *meth_init(void)
790 {
791 struct net_device *dev;
792 struct meth_private *priv;
793 int ret;
794
795 dev = alloc_etherdev(sizeof(struct meth_private));
796 if (!dev)
797 return ERR_PTR(-ENOMEM);
798
799 dev->open = meth_open;
800 dev->stop = meth_release;
801 dev->hard_start_xmit = meth_tx;
802 dev->do_ioctl = meth_ioctl;
803 dev->get_stats = meth_stats;
804 #ifdef HAVE_TX_TIMEOUT
805 dev->tx_timeout = meth_tx_timeout;
806 dev->watchdog_timeo = timeout;
807 #endif
808 dev->irq = MACE_ETHERNET_IRQ;
809 dev->base_addr = (unsigned long)&mace->eth;
810
811 priv = (struct meth_private *) dev->priv;
812 spin_lock_init(&priv->meth_lock);
813
814 ret = register_netdev(dev);
815 if (ret) {
816 free_netdev(dev);
817 return ERR_PTR(ret);
818 }
819
820 printk(KERN_INFO "%s: SGI MACE Ethernet rev. %d\n",
821 dev->name, (unsigned int)(mace->eth.mac_ctrl >> 29));
822 return 0;
823 }
824
825 static struct net_device *meth_dev;
826
827 static int __init meth_init_module(void)
828 {
829 meth_dev = meth_init();
830 if (IS_ERR(meth_dev))
831 return PTR_ERR(meth_dev);
832 return 0;
833 }
834
835 static void __exit meth_exit_module(void)
836 {
837 unregister_netdev(meth_dev);
838 free_netdev(meth_dev);
839 }
840
841 module_init(meth_init_module);
842 module_exit(meth_exit_module);
USB Experimental Work