2 * sata_sil24.c - Driver for Silicon Image 3124/3132 SATA-2 controllers
4 * Copyright 2005 Tejun Heo
6 * Based on preview driver from Silicon Image.
8 * NOTE: No NCQ/ATAPI support yet. The preview driver didn't support
9 * NCQ nor ATAPI, and, unfortunately, I couldn't find out how to make
10 * those work. Enabling those shouldn't be difficult. Basic
11 * structure is all there (in libata-dev tree). If you have any
12 * information about this hardware, please contact me or linux-ide.
13 * Info is needed on...
15 * - How to issue tagged commands and turn on sactive on issue accordingly.
16 * - Where to put an ATAPI command and how to tell the device to send it.
17 * - How to enable/use 64bit.
19 * This program is free software; you can redistribute it and/or modify it
20 * under the terms of the GNU General Public License as published by the
21 * Free Software Foundation; either version 2, or (at your option) any
24 * This program is distributed in the hope that it will be useful, but
25 * WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
27 * General Public License for more details.
31 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/pci.h>
34 #include <linux/blkdev.h>
35 #include <linux/delay.h>
36 #include <linux/interrupt.h>
37 #include <linux/dma-mapping.h>
38 #include <scsi/scsi_host.h>
40 #include <linux/libata.h>
43 #define DRV_NAME "sata_sil24"
44 #define DRV_VERSION "0.22" /* Silicon Image's preview driver was 0.10 */
47 * Port request block (PRB) 32 bytes
57 * Scatter gather entry (SGE) 16 bytes
68 struct sil24_port_multiplier
{
75 * Global controller registers (128 bytes @ BAR0)
78 HOST_SLOT_STAT
= 0x00, /* 32 bit slot stat * 4 */
82 HOST_BIST_CTRL
= 0x50,
83 HOST_BIST_PTRN
= 0x54,
84 HOST_BIST_STAT
= 0x58,
85 HOST_MEM_BIST_STAT
= 0x5c,
86 HOST_FLASH_CMD
= 0x70,
88 HOST_FLASH_DATA
= 0x74,
89 HOST_TRANSITION_DETECT
= 0x75,
90 HOST_GPIO_CTRL
= 0x76,
91 HOST_I2C_ADDR
= 0x78, /* 32 bit */
93 HOST_I2C_XFER_CNT
= 0x7e,
96 /* HOST_SLOT_STAT bits */
97 HOST_SSTAT_ATTN
= (1 << 31),
101 * (8192 bytes @ +0x0000, +0x2000, +0x4000 and +0x6000 @ BAR2)
103 PORT_REGS_SIZE
= 0x2000,
104 PORT_PRB
= 0x0000, /* (32 bytes PRB + 16 bytes SGEs * 6) * 31 (3968 bytes) */
106 PORT_PM
= 0x0f80, /* 8 bytes PM * 16 (128 bytes) */
108 PORT_CTRL_STAT
= 0x1000, /* write: ctrl-set, read: stat */
109 PORT_CTRL_CLR
= 0x1004, /* write: ctrl-clear */
110 PORT_IRQ_STAT
= 0x1008, /* high: status, low: interrupt */
111 PORT_IRQ_ENABLE_SET
= 0x1010, /* write: enable-set */
112 PORT_IRQ_ENABLE_CLR
= 0x1014, /* write: enable-clear */
113 PORT_ACTIVATE_UPPER_ADDR
= 0x101c,
114 PORT_EXEC_FIFO
= 0x1020, /* command execution fifo */
115 PORT_CMD_ERR
= 0x1024, /* command error number */
116 PORT_FIS_CFG
= 0x1028,
117 PORT_FIFO_THRES
= 0x102c,
119 PORT_DECODE_ERR_CNT
= 0x1040,
120 PORT_DECODE_ERR_THRESH
= 0x1042,
121 PORT_CRC_ERR_CNT
= 0x1044,
122 PORT_CRC_ERR_THRESH
= 0x1046,
123 PORT_HSHK_ERR_CNT
= 0x1048,
124 PORT_HSHK_ERR_THRESH
= 0x104a,
126 PORT_PHY_CFG
= 0x1050,
127 PORT_SLOT_STAT
= 0x1800,
128 PORT_CMD_ACTIVATE
= 0x1c00, /* 64 bit cmd activate * 31 (248 bytes) */
129 PORT_EXEC_DIAG
= 0x1e00, /* 32bit exec diag * 16 (64 bytes, 0-10 used on 3124) */
130 PORT_PSD_DIAG
= 0x1e40, /* 32bit psd diag * 16 (64 bytes, 0-8 used on 3124) */
131 PORT_SCONTROL
= 0x1f00,
132 PORT_SSTATUS
= 0x1f04,
133 PORT_SERROR
= 0x1f08,
134 PORT_SACTIVE
= 0x1f0c,
136 /* PORT_CTRL_STAT bits */
137 PORT_CS_PORT_RST
= (1 << 0), /* port reset */
138 PORT_CS_DEV_RST
= (1 << 1), /* device reset */
139 PORT_CS_INIT
= (1 << 2), /* port initialize */
140 PORT_CS_IRQ_WOC
= (1 << 3), /* interrupt write one to clear */
141 PORT_CS_RESUME
= (1 << 6), /* port resume */
142 PORT_CS_32BIT_ACTV
= (1 << 10), /* 32-bit activation */
143 PORT_CS_PM_EN
= (1 << 13), /* port multiplier enable */
144 PORT_CS_RDY
= (1 << 31), /* port ready to accept commands */
146 /* PORT_IRQ_STAT/ENABLE_SET/CLR */
147 /* bits[11:0] are masked */
148 PORT_IRQ_COMPLETE
= (1 << 0), /* command(s) completed */
149 PORT_IRQ_ERROR
= (1 << 1), /* command execution error */
150 PORT_IRQ_PORTRDY_CHG
= (1 << 2), /* port ready change */
151 PORT_IRQ_PWR_CHG
= (1 << 3), /* power management change */
152 PORT_IRQ_PHYRDY_CHG
= (1 << 4), /* PHY ready change */
153 PORT_IRQ_COMWAKE
= (1 << 5), /* COMWAKE received */
154 PORT_IRQ_UNK_FIS
= (1 << 6), /* Unknown FIS received */
155 PORT_IRQ_SDB_FIS
= (1 << 11), /* SDB FIS received */
157 /* bits[27:16] are unmasked (raw) */
158 PORT_IRQ_RAW_SHIFT
= 16,
159 PORT_IRQ_MASKED_MASK
= 0x7ff,
160 PORT_IRQ_RAW_MASK
= (0x7ff << PORT_IRQ_RAW_SHIFT
),
162 /* ENABLE_SET/CLR specific, intr steering - 2 bit field */
163 PORT_IRQ_STEER_SHIFT
= 30,
164 PORT_IRQ_STEER_MASK
= (3 << PORT_IRQ_STEER_SHIFT
),
166 /* PORT_CMD_ERR constants */
167 PORT_CERR_DEV
= 1, /* Error bit in D2H Register FIS */
168 PORT_CERR_SDB
= 2, /* Error bit in SDB FIS */
169 PORT_CERR_DATA
= 3, /* Error in data FIS not detected by dev */
170 PORT_CERR_SEND
= 4, /* Initial cmd FIS transmission failure */
171 PORT_CERR_INCONSISTENT
= 5, /* Protocol mismatch */
172 PORT_CERR_DIRECTION
= 6, /* Data direction mismatch */
173 PORT_CERR_UNDERRUN
= 7, /* Ran out of SGEs while writing */
174 PORT_CERR_OVERRUN
= 8, /* Ran out of SGEs while reading */
175 PORT_CERR_PKT_PROT
= 11, /* DIR invalid in 1st PIO setup of ATAPI */
176 PORT_CERR_SGT_BOUNDARY
= 16, /* PLD ecode 00 - SGT not on qword boundary */
177 PORT_CERR_SGT_TGTABRT
= 17, /* PLD ecode 01 - target abort */
178 PORT_CERR_SGT_MSTABRT
= 18, /* PLD ecode 10 - master abort */
179 PORT_CERR_SGT_PCIPERR
= 19, /* PLD ecode 11 - PCI parity err while fetching SGT */
180 PORT_CERR_CMD_BOUNDARY
= 24, /* ctrl[15:13] 001 - PRB not on qword boundary */
181 PORT_CERR_CMD_TGTABRT
= 25, /* ctrl[15:13] 010 - target abort */
182 PORT_CERR_CMD_MSTABRT
= 26, /* ctrl[15:13] 100 - master abort */
183 PORT_CERR_CMD_PCIPERR
= 27, /* ctrl[15:13] 110 - PCI parity err while fetching PRB */
184 PORT_CERR_XFR_UNDEF
= 32, /* PSD ecode 00 - undefined */
185 PORT_CERR_XFR_TGTABRT
= 33, /* PSD ecode 01 - target abort */
186 PORT_CERR_XFR_MSGABRT
= 34, /* PSD ecode 10 - master abort */
187 PORT_CERR_XFR_PCIPERR
= 35, /* PSD ecode 11 - PCI prity err during transfer */
188 PORT_CERR_SENDSERVICE
= 36, /* FIS received while sending service */
193 SGE_TRM
= (1 << 31), /* Last SGE in chain */
194 PRB_SOFT_RST
= (1 << 7), /* Soft reset request (ign BSY?) */
200 IRQ_STAT_4PORTS
= 0xf,
203 struct sil24_cmd_block
{
204 struct sil24_prb prb
;
205 struct sil24_sge sge
[LIBATA_MAX_PRD
];
211 * The preview driver always returned 0 for status. We emulate it
212 * here from the previous interrupt.
214 struct sil24_port_priv
{
215 struct sil24_cmd_block
*cmd_block
; /* 32 cmd blocks */
216 dma_addr_t cmd_block_dma
; /* DMA base addr for them */
217 struct ata_taskfile tf
; /* Cached taskfile registers */
220 /* ap->host_set->private_data */
221 struct sil24_host_priv
{
222 void *host_base
; /* global controller control (128 bytes @BAR0) */
223 void *port_base
; /* port registers (4 * 8192 bytes @BAR2) */
226 static u8
sil24_check_status(struct ata_port
*ap
);
227 static u8
sil24_check_err(struct ata_port
*ap
);
228 static u32
sil24_scr_read(struct ata_port
*ap
, unsigned sc_reg
);
229 static void sil24_scr_write(struct ata_port
*ap
, unsigned sc_reg
, u32 val
);
230 static void sil24_tf_read(struct ata_port
*ap
, struct ata_taskfile
*tf
);
231 static void sil24_phy_reset(struct ata_port
*ap
);
232 static void sil24_qc_prep(struct ata_queued_cmd
*qc
);
233 static int sil24_qc_issue(struct ata_queued_cmd
*qc
);
234 static void sil24_irq_clear(struct ata_port
*ap
);
235 static void sil24_eng_timeout(struct ata_port
*ap
);
236 static irqreturn_t
sil24_interrupt(int irq
, void *dev_instance
, struct pt_regs
*regs
);
237 static int sil24_port_start(struct ata_port
*ap
);
238 static void sil24_port_stop(struct ata_port
*ap
);
239 static void sil24_host_stop(struct ata_host_set
*host_set
);
240 static int sil24_init_one(struct pci_dev
*pdev
, const struct pci_device_id
*ent
);
242 static struct pci_device_id sil24_pci_tbl
[] = {
243 { 0x1095, 0x3124, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, BID_SIL3124
},
244 { 0x1095, 0x3132, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, BID_SIL3132
},
245 { } /* terminate list */
248 static struct pci_driver sil24_pci_driver
= {
250 .id_table
= sil24_pci_tbl
,
251 .probe
= sil24_init_one
,
252 .remove
= ata_pci_remove_one
, /* safe? */
255 static Scsi_Host_Template sil24_sht
= {
256 .module
= THIS_MODULE
,
258 .ioctl
= ata_scsi_ioctl
,
259 .queuecommand
= ata_scsi_queuecmd
,
260 .eh_strategy_handler
= ata_scsi_error
,
261 .can_queue
= ATA_DEF_QUEUE
,
262 .this_id
= ATA_SHT_THIS_ID
,
263 .sg_tablesize
= LIBATA_MAX_PRD
,
264 .max_sectors
= ATA_MAX_SECTORS
,
265 .cmd_per_lun
= ATA_SHT_CMD_PER_LUN
,
266 .emulated
= ATA_SHT_EMULATED
,
267 .use_clustering
= ATA_SHT_USE_CLUSTERING
,
268 .proc_name
= DRV_NAME
,
269 .dma_boundary
= ATA_DMA_BOUNDARY
,
270 .slave_configure
= ata_scsi_slave_config
,
271 .bios_param
= ata_std_bios_param
,
272 .ordered_flush
= 1, /* NCQ not supported yet */
275 static struct ata_port_operations sil24_ops
= {
276 .port_disable
= ata_port_disable
,
278 .check_status
= sil24_check_status
,
279 .check_altstatus
= sil24_check_status
,
280 .check_err
= sil24_check_err
,
281 .dev_select
= ata_noop_dev_select
,
283 .tf_read
= sil24_tf_read
,
285 .phy_reset
= sil24_phy_reset
,
287 .qc_prep
= sil24_qc_prep
,
288 .qc_issue
= sil24_qc_issue
,
290 .eng_timeout
= sil24_eng_timeout
,
292 .irq_handler
= sil24_interrupt
,
293 .irq_clear
= sil24_irq_clear
,
295 .scr_read
= sil24_scr_read
,
296 .scr_write
= sil24_scr_write
,
298 .port_start
= sil24_port_start
,
299 .port_stop
= sil24_port_stop
,
300 .host_stop
= sil24_host_stop
,
303 static struct ata_port_info sil24_port_info
[] = {
307 .host_flags
= ATA_FLAG_SATA
| ATA_FLAG_NO_LEGACY
|
308 ATA_FLAG_SATA_RESET
| ATA_FLAG_MMIO
|
310 .pio_mask
= 0x1f, /* pio0-4 */
311 .mwdma_mask
= 0x07, /* mwdma0-2 */
312 .udma_mask
= 0x3f, /* udma0-5 */
313 .port_ops
= &sil24_ops
,
318 .host_flags
= ATA_FLAG_SATA
| ATA_FLAG_NO_LEGACY
|
319 ATA_FLAG_SATA_RESET
| ATA_FLAG_MMIO
|
321 .pio_mask
= 0x1f, /* pio0-4 */
322 .mwdma_mask
= 0x07, /* mwdma0-2 */
323 .udma_mask
= 0x3f, /* udma0-5 */
324 .port_ops
= &sil24_ops
,
328 static inline void sil24_update_tf(struct ata_port
*ap
)
330 struct sil24_port_priv
*pp
= ap
->private_data
;
331 void *port
= (void *)ap
->ioaddr
.cmd_addr
;
332 struct sil24_prb
*prb
= port
;
334 ata_tf_from_fis(prb
->fis
, &pp
->tf
);
337 static u8
sil24_check_status(struct ata_port
*ap
)
339 struct sil24_port_priv
*pp
= ap
->private_data
;
340 return pp
->tf
.command
;
343 static u8
sil24_check_err(struct ata_port
*ap
)
345 struct sil24_port_priv
*pp
= ap
->private_data
;
346 return pp
->tf
.feature
;
349 static int sil24_scr_map
[] = {
356 static u32
sil24_scr_read(struct ata_port
*ap
, unsigned sc_reg
)
358 void *scr_addr
= (void *)ap
->ioaddr
.scr_addr
;
359 if (sc_reg
< ARRAY_SIZE(sil24_scr_map
)) {
361 addr
= scr_addr
+ sil24_scr_map
[sc_reg
] * 4;
362 return readl(scr_addr
+ sil24_scr_map
[sc_reg
] * 4);
367 static void sil24_scr_write(struct ata_port
*ap
, unsigned sc_reg
, u32 val
)
369 void *scr_addr
= (void *)ap
->ioaddr
.scr_addr
;
370 if (sc_reg
< ARRAY_SIZE(sil24_scr_map
)) {
372 addr
= scr_addr
+ sil24_scr_map
[sc_reg
] * 4;
373 writel(val
, scr_addr
+ sil24_scr_map
[sc_reg
] * 4);
377 static void sil24_tf_read(struct ata_port
*ap
, struct ata_taskfile
*tf
)
379 struct sil24_port_priv
*pp
= ap
->private_data
;
383 static void sil24_phy_reset(struct ata_port
*ap
)
385 __sata_phy_reset(ap
);
387 * No ATAPI yet. Just unconditionally indicate ATA device.
388 * If ATAPI device is attached, it will fail ATA_CMD_ID_ATA
389 * and libata core will ignore the device.
391 if (!(ap
->flags
& ATA_FLAG_PORT_DISABLED
))
392 ap
->device
[0].class = ATA_DEV_ATA
;
395 static inline void sil24_fill_sg(struct ata_queued_cmd
*qc
,
396 struct sil24_cmd_block
*cb
)
398 struct scatterlist
*sg
= qc
->sg
;
399 struct sil24_sge
*sge
= cb
->sge
;
402 for (i
= 0; i
< qc
->n_elem
; i
++, sg
++, sge
++) {
403 sge
->addr
= cpu_to_le64(sg_dma_address(sg
));
404 sge
->cnt
= cpu_to_le32(sg_dma_len(sg
));
406 sge
->flags
= i
< qc
->n_elem
- 1 ? 0 : cpu_to_le32(SGE_TRM
);
410 static void sil24_qc_prep(struct ata_queued_cmd
*qc
)
412 struct ata_port
*ap
= qc
->ap
;
413 struct sil24_port_priv
*pp
= ap
->private_data
;
414 struct sil24_cmd_block
*cb
= pp
->cmd_block
+ qc
->tag
;
415 struct sil24_prb
*prb
= &cb
->prb
;
417 switch (qc
->tf
.protocol
) {
420 case ATA_PROT_NODATA
:
423 /* ATAPI isn't supported yet */
427 ata_tf_to_fis(&qc
->tf
, prb
->fis
, 0);
429 if (qc
->flags
& ATA_QCFLAG_DMAMAP
)
430 sil24_fill_sg(qc
, cb
);
433 static int sil24_qc_issue(struct ata_queued_cmd
*qc
)
435 struct ata_port
*ap
= qc
->ap
;
436 void *port
= (void *)ap
->ioaddr
.cmd_addr
;
437 struct sil24_port_priv
*pp
= ap
->private_data
;
438 dma_addr_t paddr
= pp
->cmd_block_dma
+ qc
->tag
* sizeof(*pp
->cmd_block
);
440 writel((u32
)paddr
, port
+ PORT_CMD_ACTIVATE
);
444 static void sil24_irq_clear(struct ata_port
*ap
)
449 static int __sil24_reset_controller(void *port
)
454 /* Reset controller state. Is this correct? */
455 writel(PORT_CS_DEV_RST
, port
+ PORT_CTRL_STAT
);
456 readl(port
+ PORT_CTRL_STAT
); /* sync */
459 for (cnt
= 0; cnt
< 1000; cnt
++) {
461 tmp
= readl(port
+ PORT_CTRL_STAT
);
462 if (!(tmp
& PORT_CS_DEV_RST
))
466 if (tmp
& PORT_CS_DEV_RST
)
471 static void sil24_reset_controller(struct ata_port
*ap
)
473 printk(KERN_NOTICE DRV_NAME
474 " ata%u: resetting controller...\n", ap
->id
);
475 if (__sil24_reset_controller((void *)ap
->ioaddr
.cmd_addr
))
476 printk(KERN_ERR DRV_NAME
477 " ata%u: failed to reset controller\n", ap
->id
);
480 static void sil24_eng_timeout(struct ata_port
*ap
)
482 struct ata_queued_cmd
*qc
;
484 qc
= ata_qc_from_tag(ap
, ap
->active_tag
);
486 printk(KERN_ERR
"ata%u: BUG: tiemout without command\n",
492 * hack alert! We cannot use the supplied completion
493 * function from inside the ->eh_strategy_handler() thread.
494 * libata is the only user of ->eh_strategy_handler() in
495 * any kernel, so the default scsi_done() assumes it is
496 * not being called from the SCSI EH.
498 printk(KERN_ERR
"ata%u: command timeout\n", ap
->id
);
499 qc
->scsidone
= scsi_finish_command
;
500 ata_qc_complete(qc
, ATA_ERR
);
502 sil24_reset_controller(ap
);
505 static void sil24_error_intr(struct ata_port
*ap
, u32 slot_stat
)
507 struct ata_queued_cmd
*qc
= ata_qc_from_tag(ap
, ap
->active_tag
);
508 struct sil24_port_priv
*pp
= ap
->private_data
;
509 void *port
= (void *)ap
->ioaddr
.cmd_addr
;
510 u32 irq_stat
, cmd_err
, sstatus
, serror
;
512 irq_stat
= readl(port
+ PORT_IRQ_STAT
);
513 writel(irq_stat
, port
+ PORT_IRQ_STAT
); /* clear irq */
515 if (!(irq_stat
& PORT_IRQ_ERROR
)) {
516 /* ignore non-completion, non-error irqs for now */
517 printk(KERN_WARNING DRV_NAME
518 "ata%u: non-error exception irq (irq_stat %x)\n",
523 cmd_err
= readl(port
+ PORT_CMD_ERR
);
524 sstatus
= readl(port
+ PORT_SSTATUS
);
525 serror
= readl(port
+ PORT_SERROR
);
527 writel(serror
, port
+ PORT_SERROR
);
529 printk(KERN_ERR DRV_NAME
" ata%u: error interrupt on port%d\n"
530 " stat=0x%x irq=0x%x cmd_err=%d sstatus=0x%x serror=0x%x\n",
531 ap
->id
, ap
->port_no
, slot_stat
, irq_stat
, cmd_err
, sstatus
, serror
);
533 if (cmd_err
== PORT_CERR_DEV
|| cmd_err
== PORT_CERR_SDB
) {
535 * Device is reporting error, tf registers are valid.
540 * Other errors. libata currently doesn't have any
541 * mechanism to report these errors. Just turn on
544 pp
->tf
.command
= ATA_ERR
;
548 ata_qc_complete(qc
, pp
->tf
.command
);
550 sil24_reset_controller(ap
);
553 static inline void sil24_host_intr(struct ata_port
*ap
)
555 struct ata_queued_cmd
*qc
= ata_qc_from_tag(ap
, ap
->active_tag
);
556 void *port
= (void *)ap
->ioaddr
.cmd_addr
;
559 slot_stat
= readl(port
+ PORT_SLOT_STAT
);
560 if (!(slot_stat
& HOST_SSTAT_ATTN
)) {
561 struct sil24_port_priv
*pp
= ap
->private_data
;
563 * !HOST_SSAT_ATTN guarantees successful completion,
564 * so reading back tf registers is unnecessary for
565 * most commands. TODO: read tf registers for
566 * commands which require these values on successful
567 * completion (EXECUTE DEVICE DIAGNOSTIC, CHECK POWER,
568 * DEVICE RESET and READ PORT MULTIPLIER (any more?).
573 ata_qc_complete(qc
, pp
->tf
.command
);
575 sil24_error_intr(ap
, slot_stat
);
578 static irqreturn_t
sil24_interrupt(int irq
, void *dev_instance
, struct pt_regs
*regs
)
580 struct ata_host_set
*host_set
= dev_instance
;
581 struct sil24_host_priv
*hpriv
= host_set
->private_data
;
582 unsigned handled
= 0;
586 status
= readl(hpriv
->host_base
+ HOST_IRQ_STAT
);
588 if (status
== 0xffffffff) {
589 printk(KERN_ERR DRV_NAME
": IRQ status == 0xffffffff, "
590 "PCI fault or device removal?\n");
594 if (!(status
& IRQ_STAT_4PORTS
))
597 spin_lock(&host_set
->lock
);
599 for (i
= 0; i
< host_set
->n_ports
; i
++)
600 if (status
& (1 << i
)) {
601 struct ata_port
*ap
= host_set
->ports
[i
];
602 if (ap
&& !(ap
->flags
& ATA_FLAG_PORT_DISABLED
)) {
603 sil24_host_intr(host_set
->ports
[i
]);
606 printk(KERN_ERR DRV_NAME
607 ": interrupt from disabled port %d\n", i
);
610 spin_unlock(&host_set
->lock
);
612 return IRQ_RETVAL(handled
);
615 static int sil24_port_start(struct ata_port
*ap
)
617 struct device
*dev
= ap
->host_set
->dev
;
618 struct sil24_port_priv
*pp
;
619 struct sil24_cmd_block
*cb
;
620 size_t cb_size
= sizeof(*cb
);
623 pp
= kmalloc(sizeof(*pp
), GFP_KERNEL
);
626 memset(pp
, 0, sizeof(*pp
));
628 pp
->tf
.command
= ATA_DRDY
;
630 cb
= dma_alloc_coherent(dev
, cb_size
, &cb_dma
, GFP_KERNEL
);
635 memset(cb
, 0, cb_size
);
638 pp
->cmd_block_dma
= cb_dma
;
640 ap
->private_data
= pp
;
645 static void sil24_port_stop(struct ata_port
*ap
)
647 struct device
*dev
= ap
->host_set
->dev
;
648 struct sil24_port_priv
*pp
= ap
->private_data
;
649 size_t cb_size
= sizeof(*pp
->cmd_block
);
651 dma_free_coherent(dev
, cb_size
, pp
->cmd_block
, pp
->cmd_block_dma
);
655 static void sil24_host_stop(struct ata_host_set
*host_set
)
657 struct sil24_host_priv
*hpriv
= host_set
->private_data
;
659 iounmap(hpriv
->host_base
);
660 iounmap(hpriv
->port_base
);
664 static int sil24_init_one(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
666 static int printed_version
= 0;
667 unsigned int board_id
= (unsigned int)ent
->driver_data
;
668 struct ata_probe_ent
*probe_ent
= NULL
;
669 struct sil24_host_priv
*hpriv
= NULL
;
670 void *host_base
= NULL
, *port_base
= NULL
;
673 if (!printed_version
++)
674 printk(KERN_DEBUG DRV_NAME
" version " DRV_VERSION
"\n");
676 rc
= pci_enable_device(pdev
);
680 rc
= pci_request_regions(pdev
, DRV_NAME
);
685 /* ioremap mmio registers */
686 host_base
= ioremap(pci_resource_start(pdev
, 0),
687 pci_resource_len(pdev
, 0));
690 port_base
= ioremap(pci_resource_start(pdev
, 2),
691 pci_resource_len(pdev
, 2));
695 /* allocate & init probe_ent and hpriv */
696 probe_ent
= kmalloc(sizeof(*probe_ent
), GFP_KERNEL
);
700 hpriv
= kmalloc(sizeof(*hpriv
), GFP_KERNEL
);
704 memset(probe_ent
, 0, sizeof(*probe_ent
));
705 probe_ent
->dev
= pci_dev_to_dev(pdev
);
706 INIT_LIST_HEAD(&probe_ent
->node
);
708 probe_ent
->sht
= sil24_port_info
[board_id
].sht
;
709 probe_ent
->host_flags
= sil24_port_info
[board_id
].host_flags
;
710 probe_ent
->pio_mask
= sil24_port_info
[board_id
].pio_mask
;
711 probe_ent
->udma_mask
= sil24_port_info
[board_id
].udma_mask
;
712 probe_ent
->port_ops
= sil24_port_info
[board_id
].port_ops
;
713 probe_ent
->n_ports
= (board_id
== BID_SIL3124
) ? 4 : 2;
715 probe_ent
->irq
= pdev
->irq
;
716 probe_ent
->irq_flags
= SA_SHIRQ
;
717 probe_ent
->mmio_base
= port_base
;
718 probe_ent
->private_data
= hpriv
;
720 memset(hpriv
, 0, sizeof(*hpriv
));
721 hpriv
->host_base
= host_base
;
722 hpriv
->port_base
= port_base
;
725 * Configure the device
728 * FIXME: This device is certainly 64-bit capable. We just
729 * don't know how to use it. After fixing 32bit activation in
730 * this function, enable 64bit masks here.
732 rc
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
);
734 printk(KERN_ERR DRV_NAME
"(%s): 32-bit DMA enable failed\n",
738 rc
= pci_set_consistent_dma_mask(pdev
, DMA_32BIT_MASK
);
740 printk(KERN_ERR DRV_NAME
"(%s): 32-bit consistent DMA enable failed\n",
746 writel(0, host_base
+ HOST_FLASH_CMD
);
748 /* Mask interrupts during initialization */
749 writel(0, host_base
+ HOST_CTRL
);
751 for (i
= 0; i
< probe_ent
->n_ports
; i
++) {
752 void *port
= port_base
+ i
* PORT_REGS_SIZE
;
753 unsigned long portu
= (unsigned long)port
;
757 probe_ent
->port
[i
].cmd_addr
= portu
+ PORT_PRB
;
758 probe_ent
->port
[i
].scr_addr
= portu
+ PORT_SCONTROL
;
760 ata_std_ports(&probe_ent
->port
[i
]);
762 /* Initial PHY setting */
763 writel(0x20c, port
+ PORT_PHY_CFG
);
766 tmp
= readl(port
+ PORT_CTRL_STAT
);
767 if (tmp
& PORT_CS_PORT_RST
) {
768 writel(PORT_CS_PORT_RST
, port
+ PORT_CTRL_CLR
);
769 readl(port
+ PORT_CTRL_STAT
); /* sync */
770 for (cnt
= 0; cnt
< 10; cnt
++) {
772 tmp
= readl(port
+ PORT_CTRL_STAT
);
773 if (!(tmp
& PORT_CS_PORT_RST
))
776 if (tmp
& PORT_CS_PORT_RST
)
777 printk(KERN_ERR DRV_NAME
778 "(%s): failed to clear port RST\n",
782 /* Zero error counters. */
783 writel(0x8000, port
+ PORT_DECODE_ERR_THRESH
);
784 writel(0x8000, port
+ PORT_CRC_ERR_THRESH
);
785 writel(0x8000, port
+ PORT_HSHK_ERR_THRESH
);
786 writel(0x0000, port
+ PORT_DECODE_ERR_CNT
);
787 writel(0x0000, port
+ PORT_CRC_ERR_CNT
);
788 writel(0x0000, port
+ PORT_HSHK_ERR_CNT
);
790 /* FIXME: 32bit activation? */
791 writel(0, port
+ PORT_ACTIVATE_UPPER_ADDR
);
792 writel(PORT_CS_32BIT_ACTV
, port
+ PORT_CTRL_STAT
);
794 /* Configure interrupts */
795 writel(0xffff, port
+ PORT_IRQ_ENABLE_CLR
);
796 writel(PORT_IRQ_COMPLETE
| PORT_IRQ_ERROR
| PORT_IRQ_SDB_FIS
,
797 port
+ PORT_IRQ_ENABLE_SET
);
799 /* Clear interrupts */
800 writel(0x0fff0fff, port
+ PORT_IRQ_STAT
);
801 writel(PORT_CS_IRQ_WOC
, port
+ PORT_CTRL_CLR
);
803 /* Clear port multiplier enable and resume bits */
804 writel(PORT_CS_PM_EN
| PORT_CS_RESUME
, port
+ PORT_CTRL_CLR
);
807 if (__sil24_reset_controller(port
))
808 printk(KERN_ERR DRV_NAME
809 "(%s): failed to reset controller\n",
813 /* Turn on interrupts */
814 writel(IRQ_STAT_4PORTS
, host_base
+ HOST_CTRL
);
816 pci_set_master(pdev
);
818 /* FIXME: check ata_device_add return value */
819 ata_device_add(probe_ent
);
831 pci_release_regions(pdev
);
833 pci_disable_device(pdev
);
837 static int __init
sil24_init(void)
839 return pci_module_init(&sil24_pci_driver
);
842 static void __exit
sil24_exit(void)
844 pci_unregister_driver(&sil24_pci_driver
);
847 MODULE_AUTHOR("Tejun Heo");
848 MODULE_DESCRIPTION("Silicon Image 3124/3132 SATA low-level driver");
849 MODULE_LICENSE("GPL");
850 MODULE_DEVICE_TABLE(pci
, sil24_pci_tbl
);
852 module_init(sil24_init
);
853 module_exit(sil24_exit
);