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sched: fix CONFIG_SCHED_DEBUG dependency of lockdep sysctls
[usb.git] / drivers / mmc / host / sdhci.c
blob20a7d89e01bac08032fa874ecc081fc7a44a322d
1 /*
2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
3 *
4 * Copyright (C) 2005-2007 Pierre Ossman, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
10 */
11
12 #include <linux/delay.h>
13 #include <linux/highmem.h>
14 #include <linux/pci.h>
15 #include <linux/dma-mapping.h>
16
17 #include <linux/mmc/host.h>
18
19 #include <asm/scatterlist.h>
20
21 #include "sdhci.h"
22
23 #define DRIVER_NAME "sdhci"
24
25 #define DBG(f, x...) \
26 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
27
28 static unsigned int debug_nodma = 0;
29 static unsigned int debug_forcedma = 0;
30 static unsigned int debug_quirks = 0;
31
32 #define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0)
33 #define SDHCI_QUIRK_FORCE_DMA (1<<1)
34 /* Controller doesn't like some resets when there is no card inserted. */
35 #define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<2)
36 #define SDHCI_QUIRK_SINGLE_POWER_WRITE (1<<3)
37 #define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS (1<<4)
38
39 static const struct pci_device_id pci_ids[] __devinitdata = {
40 {
41 .vendor = PCI_VENDOR_ID_RICOH,
42 .device = PCI_DEVICE_ID_RICOH_R5C822,
43 .subvendor = PCI_VENDOR_ID_IBM,
44 .subdevice = PCI_ANY_ID,
45 .driver_data = SDHCI_QUIRK_CLOCK_BEFORE_RESET |
46 SDHCI_QUIRK_FORCE_DMA,
47 },
48
49 {
50 .vendor = PCI_VENDOR_ID_RICOH,
51 .device = PCI_DEVICE_ID_RICOH_R5C822,
52 .subvendor = PCI_ANY_ID,
53 .subdevice = PCI_ANY_ID,
54 .driver_data = SDHCI_QUIRK_FORCE_DMA |
55 SDHCI_QUIRK_NO_CARD_NO_RESET,
56 },
57
58 {
59 .vendor = PCI_VENDOR_ID_TI,
60 .device = PCI_DEVICE_ID_TI_XX21_XX11_SD,
61 .subvendor = PCI_ANY_ID,
62 .subdevice = PCI_ANY_ID,
63 .driver_data = SDHCI_QUIRK_FORCE_DMA,
64 },
65
66 {
67 .vendor = PCI_VENDOR_ID_ENE,
68 .device = PCI_DEVICE_ID_ENE_CB712_SD,
69 .subvendor = PCI_ANY_ID,
70 .subdevice = PCI_ANY_ID,
71 .driver_data = SDHCI_QUIRK_SINGLE_POWER_WRITE,
72 },
73
74 {
75 .vendor = PCI_VENDOR_ID_ENE,
76 .device = PCI_DEVICE_ID_ENE_CB712_SD_2,
77 .subvendor = PCI_ANY_ID,
78 .subdevice = PCI_ANY_ID,
79 .driver_data = SDHCI_QUIRK_SINGLE_POWER_WRITE,
80 },
81
82 {
83 .vendor = PCI_VENDOR_ID_ENE,
84 .device = PCI_DEVICE_ID_ENE_CB714_SD,
85 .subvendor = PCI_ANY_ID,
86 .subdevice = PCI_ANY_ID,
87 .driver_data = SDHCI_QUIRK_SINGLE_POWER_WRITE |
88 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS,
89 },
90
91 {
92 .vendor = PCI_VENDOR_ID_ENE,
93 .device = PCI_DEVICE_ID_ENE_CB714_SD_2,
94 .subvendor = PCI_ANY_ID,
95 .subdevice = PCI_ANY_ID,
96 .driver_data = SDHCI_QUIRK_SINGLE_POWER_WRITE |
97 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS,
98 },
99
100 { /* Generic SD host controller */
101 PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)
102 },
103
104 { /* end: all zeroes */ },
105 };
106
107 MODULE_DEVICE_TABLE(pci, pci_ids);
108
109 static void sdhci_prepare_data(struct sdhci_host *, struct mmc_data *);
110 static void sdhci_finish_data(struct sdhci_host *);
111
112 static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
113 static void sdhci_finish_command(struct sdhci_host *);
114
115 static void sdhci_dumpregs(struct sdhci_host *host)
116 {
117 printk(KERN_DEBUG DRIVER_NAME ": ============== REGISTER DUMP ==============\n");
118
119 printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
120 readl(host->ioaddr + SDHCI_DMA_ADDRESS),
121 readw(host->ioaddr + SDHCI_HOST_VERSION));
122 printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
123 readw(host->ioaddr + SDHCI_BLOCK_SIZE),
124 readw(host->ioaddr + SDHCI_BLOCK_COUNT));
125 printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
126 readl(host->ioaddr + SDHCI_ARGUMENT),
127 readw(host->ioaddr + SDHCI_TRANSFER_MODE));
128 printk(KERN_DEBUG DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
129 readl(host->ioaddr + SDHCI_PRESENT_STATE),
130 readb(host->ioaddr + SDHCI_HOST_CONTROL));
131 printk(KERN_DEBUG DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
132 readb(host->ioaddr + SDHCI_POWER_CONTROL),
133 readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL));
134 printk(KERN_DEBUG DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
135 readb(host->ioaddr + SDHCI_WALK_UP_CONTROL),
136 readw(host->ioaddr + SDHCI_CLOCK_CONTROL));
137 printk(KERN_DEBUG DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
138 readb(host->ioaddr + SDHCI_TIMEOUT_CONTROL),
139 readl(host->ioaddr + SDHCI_INT_STATUS));
140 printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
141 readl(host->ioaddr + SDHCI_INT_ENABLE),
142 readl(host->ioaddr + SDHCI_SIGNAL_ENABLE));
143 printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
144 readw(host->ioaddr + SDHCI_ACMD12_ERR),
145 readw(host->ioaddr + SDHCI_SLOT_INT_STATUS));
146 printk(KERN_DEBUG DRIVER_NAME ": Caps: 0x%08x | Max curr: 0x%08x\n",
147 readl(host->ioaddr + SDHCI_CAPABILITIES),
148 readl(host->ioaddr + SDHCI_MAX_CURRENT));
149
150 printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
151 }
152
153 /*****************************************************************************\
154 * *
155 * Low level functions *
156 * *
157 \*****************************************************************************/
158
159 static void sdhci_reset(struct sdhci_host *host, u8 mask)
160 {
161 unsigned long timeout;
162
163 if (host->chip->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
164 if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) &
165 SDHCI_CARD_PRESENT))
166 return;
167 }
168
169 writeb(mask, host->ioaddr + SDHCI_SOFTWARE_RESET);
170
171 if (mask & SDHCI_RESET_ALL)
172 host->clock = 0;
173
174 /* Wait max 100 ms */
175 timeout = 100;
176
177 /* hw clears the bit when it's done */
178 while (readb(host->ioaddr + SDHCI_SOFTWARE_RESET) & mask) {
179 if (timeout == 0) {
180 printk(KERN_ERR "%s: Reset 0x%x never completed.\n",
181 mmc_hostname(host->mmc), (int)mask);
182 sdhci_dumpregs(host);
183 return;
184 }
185 timeout--;
186 mdelay(1);
187 }
188 }
189
190 static void sdhci_init(struct sdhci_host *host)
191 {
192 u32 intmask;
193
194 sdhci_reset(host, SDHCI_RESET_ALL);
195
196 intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
197 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
198 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
199 SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT |
200 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
201 SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE;
202
203 writel(intmask, host->ioaddr + SDHCI_INT_ENABLE);
204 writel(intmask, host->ioaddr + SDHCI_SIGNAL_ENABLE);
205 }
206
207 static void sdhci_activate_led(struct sdhci_host *host)
208 {
209 u8 ctrl;
210
211 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
212 ctrl |= SDHCI_CTRL_LED;
213 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
214 }
215
216 static void sdhci_deactivate_led(struct sdhci_host *host)
217 {
218 u8 ctrl;
219
220 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
221 ctrl &= ~SDHCI_CTRL_LED;
222 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
223 }
224
225 /*****************************************************************************\
226 * *
227 * Core functions *
228 * *
229 \*****************************************************************************/
230
231 static inline char* sdhci_sg_to_buffer(struct sdhci_host* host)
232 {
233 return page_address(host->cur_sg->page) + host->cur_sg->offset;
234 }
235
236 static inline int sdhci_next_sg(struct sdhci_host* host)
237 {
238 /*
239 * Skip to next SG entry.
240 */
241 host->cur_sg++;
242 host->num_sg--;
243
244 /*
245 * Any entries left?
246 */
247 if (host->num_sg > 0) {
248 host->offset = 0;
249 host->remain = host->cur_sg->length;
250 }
251
252 return host->num_sg;
253 }
254
255 static void sdhci_read_block_pio(struct sdhci_host *host)
256 {
257 int blksize, chunk_remain;
258 u32 data;
259 char *buffer;
260 int size;
261
262 DBG("PIO reading\n");
263
264 blksize = host->data->blksz;
265 chunk_remain = 0;
266 data = 0;
267
268 buffer = sdhci_sg_to_buffer(host) + host->offset;
269
270 while (blksize) {
271 if (chunk_remain == 0) {
272 data = readl(host->ioaddr + SDHCI_BUFFER);
273 chunk_remain = min(blksize, 4);
274 }
275
276 size = min(host->remain, chunk_remain);
277
278 chunk_remain -= size;
279 blksize -= size;
280 host->offset += size;
281 host->remain -= size;
282
283 while (size) {
284 *buffer = data & 0xFF;
285 buffer++;
286 data >>= 8;
287 size--;
288 }
289
290 if (host->remain == 0) {
291 if (sdhci_next_sg(host) == 0) {
292 BUG_ON(blksize != 0);
293 return;
294 }
295 buffer = sdhci_sg_to_buffer(host);
296 }
297 }
298 }
299
300 static void sdhci_write_block_pio(struct sdhci_host *host)
301 {
302 int blksize, chunk_remain;
303 u32 data;
304 char *buffer;
305 int bytes, size;
306
307 DBG("PIO writing\n");
308
309 blksize = host->data->blksz;
310 chunk_remain = 4;
311 data = 0;
312
313 bytes = 0;
314 buffer = sdhci_sg_to_buffer(host) + host->offset;
315
316 while (blksize) {
317 size = min(host->remain, chunk_remain);
318
319 chunk_remain -= size;
320 blksize -= size;
321 host->offset += size;
322 host->remain -= size;
323
324 while (size) {
325 data >>= 8;
326 data |= (u32)*buffer << 24;
327 buffer++;
328 size--;
329 }
330
331 if (chunk_remain == 0) {
332 writel(data, host->ioaddr + SDHCI_BUFFER);
333 chunk_remain = min(blksize, 4);
334 }
335
336 if (host->remain == 0) {
337 if (sdhci_next_sg(host) == 0) {
338 BUG_ON(blksize != 0);
339 return;
340 }
341 buffer = sdhci_sg_to_buffer(host);
342 }
343 }
344 }
345
346 static void sdhci_transfer_pio(struct sdhci_host *host)
347 {
348 u32 mask;
349
350 BUG_ON(!host->data);
351
352 if (host->num_sg == 0)
353 return;
354
355 if (host->data->flags & MMC_DATA_READ)
356 mask = SDHCI_DATA_AVAILABLE;
357 else
358 mask = SDHCI_SPACE_AVAILABLE;
359
360 while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) {
361 if (host->data->flags & MMC_DATA_READ)
362 sdhci_read_block_pio(host);
363 else
364 sdhci_write_block_pio(host);
365
366 if (host->num_sg == 0)
367 break;
368 }
369
370 DBG("PIO transfer complete.\n");
371 }
372
373 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data)
374 {
375 u8 count;
376 unsigned target_timeout, current_timeout;
377
378 WARN_ON(host->data);
379
380 if (data == NULL)
381 return;
382
383 /* Sanity checks */
384 BUG_ON(data->blksz * data->blocks > 524288);
385 BUG_ON(data->blksz > host->mmc->max_blk_size);
386 BUG_ON(data->blocks > 65535);
387
388 host->data = data;
389 host->data_early = 0;
390
391 /* timeout in us */
392 target_timeout = data->timeout_ns / 1000 +
393 data->timeout_clks / host->clock;
394
395 /*
396 * Figure out needed cycles.
397 * We do this in steps in order to fit inside a 32 bit int.
398 * The first step is the minimum timeout, which will have a
399 * minimum resolution of 6 bits:
400 * (1) 2^13*1000 > 2^22,
401 * (2) host->timeout_clk < 2^16
402 * =>
403 * (1) / (2) > 2^6
404 */
405 count = 0;
406 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
407 while (current_timeout < target_timeout) {
408 count++;
409 current_timeout <<= 1;
410 if (count >= 0xF)
411 break;
412 }
413
414 if (count >= 0xF) {
415 printk(KERN_WARNING "%s: Too large timeout requested!\n",
416 mmc_hostname(host->mmc));
417 count = 0xE;
418 }
419
420 writeb(count, host->ioaddr + SDHCI_TIMEOUT_CONTROL);
421
422 if (host->flags & SDHCI_USE_DMA) {
423 int count;
424
425 count = pci_map_sg(host->chip->pdev, data->sg, data->sg_len,
426 (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE);
427 BUG_ON(count != 1);
428
429 writel(sg_dma_address(data->sg), host->ioaddr + SDHCI_DMA_ADDRESS);
430 } else {
431 host->cur_sg = data->sg;
432 host->num_sg = data->sg_len;
433
434 host->offset = 0;
435 host->remain = host->cur_sg->length;
436 }
437
438 /* We do not handle DMA boundaries, so set it to max (512 KiB) */
439 writew(SDHCI_MAKE_BLKSZ(7, data->blksz),
440 host->ioaddr + SDHCI_BLOCK_SIZE);
441 writew(data->blocks, host->ioaddr + SDHCI_BLOCK_COUNT);
442 }
443
444 static void sdhci_set_transfer_mode(struct sdhci_host *host,
445 struct mmc_data *data)
446 {
447 u16 mode;
448
449 if (data == NULL)
450 return;
451
452 WARN_ON(!host->data);
453
454 mode = SDHCI_TRNS_BLK_CNT_EN;
455 if (data->blocks > 1)
456 mode |= SDHCI_TRNS_MULTI;
457 if (data->flags & MMC_DATA_READ)
458 mode |= SDHCI_TRNS_READ;
459 if (host->flags & SDHCI_USE_DMA)
460 mode |= SDHCI_TRNS_DMA;
461
462 writew(mode, host->ioaddr + SDHCI_TRANSFER_MODE);
463 }
464
465 static void sdhci_finish_data(struct sdhci_host *host)
466 {
467 struct mmc_data *data;
468 u16 blocks;
469
470 BUG_ON(!host->data);
471
472 data = host->data;
473 host->data = NULL;
474
475 if (host->flags & SDHCI_USE_DMA) {
476 pci_unmap_sg(host->chip->pdev, data->sg, data->sg_len,
477 (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE);
478 }
479
480 /*
481 * Controller doesn't count down when in single block mode.
482 */
483 if (data->blocks == 1)
484 blocks = (data->error == MMC_ERR_NONE) ? 0 : 1;
485 else
486 blocks = readw(host->ioaddr + SDHCI_BLOCK_COUNT);
487 data->bytes_xfered = data->blksz * (data->blocks - blocks);
488
489 if ((data->error == MMC_ERR_NONE) && blocks) {
490 printk(KERN_ERR "%s: Controller signalled completion even "
491 "though there were blocks left.\n",
492 mmc_hostname(host->mmc));
493 data->error = MMC_ERR_FAILED;
494 }
495
496 if (data->stop) {
497 /*
498 * The controller needs a reset of internal state machines
499 * upon error conditions.
500 */
501 if (data->error != MMC_ERR_NONE) {
502 sdhci_reset(host, SDHCI_RESET_CMD);
503 sdhci_reset(host, SDHCI_RESET_DATA);
504 }
505
506 sdhci_send_command(host, data->stop);
507 } else
508 tasklet_schedule(&host->finish_tasklet);
509 }
510
511 static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
512 {
513 int flags;
514 u32 mask;
515 unsigned long timeout;
516
517 WARN_ON(host->cmd);
518
519 /* Wait max 10 ms */
520 timeout = 10;
521
522 mask = SDHCI_CMD_INHIBIT;
523 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
524 mask |= SDHCI_DATA_INHIBIT;
525
526 /* We shouldn't wait for data inihibit for stop commands, even
527 though they might use busy signaling */
528 if (host->mrq->data && (cmd == host->mrq->data->stop))
529 mask &= ~SDHCI_DATA_INHIBIT;
530
531 while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) {
532 if (timeout == 0) {
533 printk(KERN_ERR "%s: Controller never released "
534 "inhibit bit(s).\n", mmc_hostname(host->mmc));
535 sdhci_dumpregs(host);
536 cmd->error = MMC_ERR_FAILED;
537 tasklet_schedule(&host->finish_tasklet);
538 return;
539 }
540 timeout--;
541 mdelay(1);
542 }
543
544 mod_timer(&host->timer, jiffies + 10 * HZ);
545
546 host->cmd = cmd;
547
548 sdhci_prepare_data(host, cmd->data);
549
550 writel(cmd->arg, host->ioaddr + SDHCI_ARGUMENT);
551
552 sdhci_set_transfer_mode(host, cmd->data);
553
554 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
555 printk(KERN_ERR "%s: Unsupported response type!\n",
556 mmc_hostname(host->mmc));
557 cmd->error = MMC_ERR_INVALID;
558 tasklet_schedule(&host->finish_tasklet);
559 return;
560 }
561
562 if (!(cmd->flags & MMC_RSP_PRESENT))
563 flags = SDHCI_CMD_RESP_NONE;
564 else if (cmd->flags & MMC_RSP_136)
565 flags = SDHCI_CMD_RESP_LONG;
566 else if (cmd->flags & MMC_RSP_BUSY)
567 flags = SDHCI_CMD_RESP_SHORT_BUSY;
568 else
569 flags = SDHCI_CMD_RESP_SHORT;
570
571 if (cmd->flags & MMC_RSP_CRC)
572 flags |= SDHCI_CMD_CRC;
573 if (cmd->flags & MMC_RSP_OPCODE)
574 flags |= SDHCI_CMD_INDEX;
575 if (cmd->data)
576 flags |= SDHCI_CMD_DATA;
577
578 writew(SDHCI_MAKE_CMD(cmd->opcode, flags),
579 host->ioaddr + SDHCI_COMMAND);
580 }
581
582 static void sdhci_finish_command(struct sdhci_host *host)
583 {
584 int i;
585
586 BUG_ON(host->cmd == NULL);
587
588 if (host->cmd->flags & MMC_RSP_PRESENT) {
589 if (host->cmd->flags & MMC_RSP_136) {
590 /* CRC is stripped so we need to do some shifting. */
591 for (i = 0;i < 4;i++) {
592 host->cmd->resp[i] = readl(host->ioaddr +
593 SDHCI_RESPONSE + (3-i)*4) << 8;
594 if (i != 3)
595 host->cmd->resp[i] |=
596 readb(host->ioaddr +
597 SDHCI_RESPONSE + (3-i)*4-1);
598 }
599 } else {
600 host->cmd->resp[0] = readl(host->ioaddr + SDHCI_RESPONSE);
601 }
602 }
603
604 host->cmd->error = MMC_ERR_NONE;
605
606 if (host->data && host->data_early)
607 sdhci_finish_data(host);
608
609 if (!host->cmd->data)
610 tasklet_schedule(&host->finish_tasklet);
611
612 host->cmd = NULL;
613 }
614
615 static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
616 {
617 int div;
618 u16 clk;
619 unsigned long timeout;
620
621 if (clock == host->clock)
622 return;
623
624 writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
625
626 if (clock == 0)
627 goto out;
628
629 for (div = 1;div < 256;div *= 2) {
630 if ((host->max_clk / div) <= clock)
631 break;
632 }
633 div >>= 1;
634
635 clk = div << SDHCI_DIVIDER_SHIFT;
636 clk |= SDHCI_CLOCK_INT_EN;
637 writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
638
639 /* Wait max 10 ms */
640 timeout = 10;
641 while (!((clk = readw(host->ioaddr + SDHCI_CLOCK_CONTROL))
642 & SDHCI_CLOCK_INT_STABLE)) {
643 if (timeout == 0) {
644 printk(KERN_ERR "%s: Internal clock never "
645 "stabilised.\n", mmc_hostname(host->mmc));
646 sdhci_dumpregs(host);
647 return;
648 }
649 timeout--;
650 mdelay(1);
651 }
652
653 clk |= SDHCI_CLOCK_CARD_EN;
654 writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
655
656 out:
657 host->clock = clock;
658 }
659
660 static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
661 {
662 u8 pwr;
663
664 if (host->power == power)
665 return;
666
667 if (power == (unsigned short)-1) {
668 writeb(0, host->ioaddr + SDHCI_POWER_CONTROL);
669 goto out;
670 }
671
672 /*
673 * Spec says that we should clear the power reg before setting
674 * a new value. Some controllers don't seem to like this though.
675 */
676 if (!(host->chip->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
677 writeb(0, host->ioaddr + SDHCI_POWER_CONTROL);
678
679 pwr = SDHCI_POWER_ON;
680
681 switch (1 << power) {
682 case MMC_VDD_165_195:
683 pwr |= SDHCI_POWER_180;
684 break;
685 case MMC_VDD_29_30:
686 case MMC_VDD_30_31:
687 pwr |= SDHCI_POWER_300;
688 break;
689 case MMC_VDD_32_33:
690 case MMC_VDD_33_34:
691 pwr |= SDHCI_POWER_330;
692 break;
693 default:
694 BUG();
695 }
696
697 writeb(pwr, host->ioaddr + SDHCI_POWER_CONTROL);
698
699 out:
700 host->power = power;
701 }
702
703 /*****************************************************************************\
704 * *
705 * MMC callbacks *
706 * *
707 \*****************************************************************************/
708
709 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
710 {
711 struct sdhci_host *host;
712 unsigned long flags;
713
714 host = mmc_priv(mmc);
715
716 spin_lock_irqsave(&host->lock, flags);
717
718 WARN_ON(host->mrq != NULL);
719
720 sdhci_activate_led(host);
721
722 host->mrq = mrq;
723
724 if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
725 host->mrq->cmd->error = MMC_ERR_TIMEOUT;
726 tasklet_schedule(&host->finish_tasklet);
727 } else
728 sdhci_send_command(host, mrq->cmd);
729
730 mmiowb();
731 spin_unlock_irqrestore(&host->lock, flags);
732 }
733
734 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
735 {
736 struct sdhci_host *host;
737 unsigned long flags;
738 u8 ctrl;
739
740 host = mmc_priv(mmc);
741
742 spin_lock_irqsave(&host->lock, flags);
743
744 /*
745 * Reset the chip on each power off.
746 * Should clear out any weird states.
747 */
748 if (ios->power_mode == MMC_POWER_OFF) {
749 writel(0, host->ioaddr + SDHCI_SIGNAL_ENABLE);
750 sdhci_init(host);
751 }
752
753 sdhci_set_clock(host, ios->clock);
754
755 if (ios->power_mode == MMC_POWER_OFF)
756 sdhci_set_power(host, -1);
757 else
758 sdhci_set_power(host, ios->vdd);
759
760 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
761
762 if (ios->bus_width == MMC_BUS_WIDTH_4)
763 ctrl |= SDHCI_CTRL_4BITBUS;
764 else
765 ctrl &= ~SDHCI_CTRL_4BITBUS;
766
767 if (ios->timing == MMC_TIMING_SD_HS)
768 ctrl |= SDHCI_CTRL_HISPD;
769 else
770 ctrl &= ~SDHCI_CTRL_HISPD;
771
772 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
773
774 /*
775 * Some (ENE) controllers go apeshit on some ios operation,
776 * signalling timeout and CRC errors even on CMD0. Resetting
777 * it on each ios seems to solve the problem.
778 */
779 if(host->chip->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
780 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
781
782 mmiowb();
783 spin_unlock_irqrestore(&host->lock, flags);
784 }
785
786 static int sdhci_get_ro(struct mmc_host *mmc)
787 {
788 struct sdhci_host *host;
789 unsigned long flags;
790 int present;
791
792 host = mmc_priv(mmc);
793
794 spin_lock_irqsave(&host->lock, flags);
795
796 present = readl(host->ioaddr + SDHCI_PRESENT_STATE);
797
798 spin_unlock_irqrestore(&host->lock, flags);
799
800 return !(present & SDHCI_WRITE_PROTECT);
801 }
802
803 static const struct mmc_host_ops sdhci_ops = {
804 .request = sdhci_request,
805 .set_ios = sdhci_set_ios,
806 .get_ro = sdhci_get_ro,
807 };
808
809 /*****************************************************************************\
810 * *
811 * Tasklets *
812 * *
813 \*****************************************************************************/
814
815 static void sdhci_tasklet_card(unsigned long param)
816 {
817 struct sdhci_host *host;
818 unsigned long flags;
819
820 host = (struct sdhci_host*)param;
821
822 spin_lock_irqsave(&host->lock, flags);
823
824 if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
825 if (host->mrq) {
826 printk(KERN_ERR "%s: Card removed during transfer!\n",
827 mmc_hostname(host->mmc));
828 printk(KERN_ERR "%s: Resetting controller.\n",
829 mmc_hostname(host->mmc));
830
831 sdhci_reset(host, SDHCI_RESET_CMD);
832 sdhci_reset(host, SDHCI_RESET_DATA);
833
834 host->mrq->cmd->error = MMC_ERR_FAILED;
835 tasklet_schedule(&host->finish_tasklet);
836 }
837 }
838
839 spin_unlock_irqrestore(&host->lock, flags);
840
841 mmc_detect_change(host->mmc, msecs_to_jiffies(500));
842 }
843
844 static void sdhci_tasklet_finish(unsigned long param)
845 {
846 struct sdhci_host *host;
847 unsigned long flags;
848 struct mmc_request *mrq;
849
850 host = (struct sdhci_host*)param;
851
852 spin_lock_irqsave(&host->lock, flags);
853
854 del_timer(&host->timer);
855
856 mrq = host->mrq;
857
858 /*
859 * The controller needs a reset of internal state machines
860 * upon error conditions.
861 */
862 if ((mrq->cmd->error != MMC_ERR_NONE) ||
863 (mrq->data && ((mrq->data->error != MMC_ERR_NONE) ||
864 (mrq->data->stop && (mrq->data->stop->error != MMC_ERR_NONE))))) {
865
866 /* Some controllers need this kick or reset won't work here */
867 if (host->chip->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
868 unsigned int clock;
869
870 /* This is to force an update */
871 clock = host->clock;
872 host->clock = 0;
873 sdhci_set_clock(host, clock);
874 }
875
876 /* Spec says we should do both at the same time, but Ricoh
877 controllers do not like that. */
878 sdhci_reset(host, SDHCI_RESET_CMD);
879 sdhci_reset(host, SDHCI_RESET_DATA);
880 }
881
882 host->mrq = NULL;
883 host->cmd = NULL;
884 host->data = NULL;
885
886 sdhci_deactivate_led(host);
887
888 mmiowb();
889 spin_unlock_irqrestore(&host->lock, flags);
890
891 mmc_request_done(host->mmc, mrq);
892 }
893
894 static void sdhci_timeout_timer(unsigned long data)
895 {
896 struct sdhci_host *host;
897 unsigned long flags;
898
899 host = (struct sdhci_host*)data;
900
901 spin_lock_irqsave(&host->lock, flags);
902
903 if (host->mrq) {
904 printk(KERN_ERR "%s: Timeout waiting for hardware "
905 "interrupt.\n", mmc_hostname(host->mmc));
906 sdhci_dumpregs(host);
907
908 if (host->data) {
909 host->data->error = MMC_ERR_TIMEOUT;
910 sdhci_finish_data(host);
911 } else {
912 if (host->cmd)
913 host->cmd->error = MMC_ERR_TIMEOUT;
914 else
915 host->mrq->cmd->error = MMC_ERR_TIMEOUT;
916
917 tasklet_schedule(&host->finish_tasklet);
918 }
919 }
920
921 mmiowb();
922 spin_unlock_irqrestore(&host->lock, flags);
923 }
924
925 /*****************************************************************************\
926 * *
927 * Interrupt handling *
928 * *
929 \*****************************************************************************/
930
931 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
932 {
933 BUG_ON(intmask == 0);
934
935 if (!host->cmd) {
936 printk(KERN_ERR "%s: Got command interrupt 0x%08x even "
937 "though no command operation was in progress.\n",
938 mmc_hostname(host->mmc), (unsigned)intmask);
939 sdhci_dumpregs(host);
940 return;
941 }
942
943 if (intmask & SDHCI_INT_TIMEOUT)
944 host->cmd->error = MMC_ERR_TIMEOUT;
945 else if (intmask & SDHCI_INT_CRC)
946 host->cmd->error = MMC_ERR_BADCRC;
947 else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX))
948 host->cmd->error = MMC_ERR_FAILED;
949
950 if (host->cmd->error != MMC_ERR_NONE)
951 tasklet_schedule(&host->finish_tasklet);
952 else if (intmask & SDHCI_INT_RESPONSE)
953 sdhci_finish_command(host);
954 }
955
956 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
957 {
958 BUG_ON(intmask == 0);
959
960 if (!host->data) {
961 /*
962 * A data end interrupt is sent together with the response
963 * for the stop command.
964 */
965 if (intmask & SDHCI_INT_DATA_END)
966 return;
967
968 printk(KERN_ERR "%s: Got data interrupt 0x%08x even "
969 "though no data operation was in progress.\n",
970 mmc_hostname(host->mmc), (unsigned)intmask);
971 sdhci_dumpregs(host);
972
973 return;
974 }
975
976 if (intmask & SDHCI_INT_DATA_TIMEOUT)
977 host->data->error = MMC_ERR_TIMEOUT;
978 else if (intmask & SDHCI_INT_DATA_CRC)
979 host->data->error = MMC_ERR_BADCRC;
980 else if (intmask & SDHCI_INT_DATA_END_BIT)
981 host->data->error = MMC_ERR_FAILED;
982
983 if (host->data->error != MMC_ERR_NONE)
984 sdhci_finish_data(host);
985 else {
986 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
987 sdhci_transfer_pio(host);
988
989 /*
990 * We currently don't do anything fancy with DMA
991 * boundaries, but as we can't disable the feature
992 * we need to at least restart the transfer.
993 */
994 if (intmask & SDHCI_INT_DMA_END)
995 writel(readl(host->ioaddr + SDHCI_DMA_ADDRESS),
996 host->ioaddr + SDHCI_DMA_ADDRESS);
997
998 if (intmask & SDHCI_INT_DATA_END) {
999 if (host->cmd) {
1000 /*
1001 * Data managed to finish before the
1002 * command completed. Make sure we do
1003 * things in the proper order.
1004 */
1005 host->data_early = 1;
1006 } else {
1007 sdhci_finish_data(host);
1008 }
1009 }
1010 }
1011 }
1012
1013 static irqreturn_t sdhci_irq(int irq, void *dev_id)
1014 {
1015 irqreturn_t result;
1016 struct sdhci_host* host = dev_id;
1017 u32 intmask;
1018
1019 spin_lock(&host->lock);
1020
1021 intmask = readl(host->ioaddr + SDHCI_INT_STATUS);
1022
1023 if (!intmask || intmask == 0xffffffff) {
1024 result = IRQ_NONE;
1025 goto out;
1026 }
1027
1028 DBG("*** %s got interrupt: 0x%08x\n", host->slot_descr, intmask);
1029
1030 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
1031 writel(intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE),
1032 host->ioaddr + SDHCI_INT_STATUS);
1033 tasklet_schedule(&host->card_tasklet);
1034 }
1035
1036 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
1037
1038 if (intmask & SDHCI_INT_CMD_MASK) {
1039 writel(intmask & SDHCI_INT_CMD_MASK,
1040 host->ioaddr + SDHCI_INT_STATUS);
1041 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
1042 }
1043
1044 if (intmask & SDHCI_INT_DATA_MASK) {
1045 writel(intmask & SDHCI_INT_DATA_MASK,
1046 host->ioaddr + SDHCI_INT_STATUS);
1047 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
1048 }
1049
1050 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
1051
1052 intmask &= ~SDHCI_INT_ERROR;
1053
1054 if (intmask & SDHCI_INT_BUS_POWER) {
1055 printk(KERN_ERR "%s: Card is consuming too much power!\n",
1056 mmc_hostname(host->mmc));
1057 writel(SDHCI_INT_BUS_POWER, host->ioaddr + SDHCI_INT_STATUS);
1058 }
1059
1060 intmask &= ~SDHCI_INT_BUS_POWER;
1061
1062 if (intmask) {
1063 printk(KERN_ERR "%s: Unexpected interrupt 0x%08x.\n",
1064 mmc_hostname(host->mmc), intmask);
1065 sdhci_dumpregs(host);
1066
1067 writel(intmask, host->ioaddr + SDHCI_INT_STATUS);
1068 }
1069
1070 result = IRQ_HANDLED;
1071
1072 mmiowb();
1073 out:
1074 spin_unlock(&host->lock);
1075
1076 return result;
1077 }
1078
1079 /*****************************************************************************\
1080 * *
1081 * Suspend/resume *
1082 * *
1083 \*****************************************************************************/
1084
1085 #ifdef CONFIG_PM
1086
1087 static int sdhci_suspend (struct pci_dev *pdev, pm_message_t state)
1088 {
1089 struct sdhci_chip *chip;
1090 int i, ret;
1091
1092 chip = pci_get_drvdata(pdev);
1093 if (!chip)
1094 return 0;
1095
1096 DBG("Suspending...\n");
1097
1098 for (i = 0;i < chip->num_slots;i++) {
1099 if (!chip->hosts[i])
1100 continue;
1101 ret = mmc_suspend_host(chip->hosts[i]->mmc, state);
1102 if (ret) {
1103 for (i--;i >= 0;i--)
1104 mmc_resume_host(chip->hosts[i]->mmc);
1105 return ret;
1106 }
1107 }
1108
1109 pci_save_state(pdev);
1110 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
1111
1112 for (i = 0;i < chip->num_slots;i++) {
1113 if (!chip->hosts[i])
1114 continue;
1115 free_irq(chip->hosts[i]->irq, chip->hosts[i]);
1116 }
1117
1118 pci_disable_device(pdev);
1119 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1120
1121 return 0;
1122 }
1123
1124 static int sdhci_resume (struct pci_dev *pdev)
1125 {
1126 struct sdhci_chip *chip;
1127 int i, ret;
1128
1129 chip = pci_get_drvdata(pdev);
1130 if (!chip)
1131 return 0;
1132
1133 DBG("Resuming...\n");
1134
1135 pci_set_power_state(pdev, PCI_D0);
1136 pci_restore_state(pdev);
1137 ret = pci_enable_device(pdev);
1138 if (ret)
1139 return ret;
1140
1141 for (i = 0;i < chip->num_slots;i++) {
1142 if (!chip->hosts[i])
1143 continue;
1144 if (chip->hosts[i]->flags & SDHCI_USE_DMA)
1145 pci_set_master(pdev);
1146 ret = request_irq(chip->hosts[i]->irq, sdhci_irq,
1147 IRQF_SHARED, chip->hosts[i]->slot_descr,
1148 chip->hosts[i]);
1149 if (ret)
1150 return ret;
1151 sdhci_init(chip->hosts[i]);
1152 mmiowb();
1153 ret = mmc_resume_host(chip->hosts[i]->mmc);
1154 if (ret)
1155 return ret;
1156 }
1157
1158 return 0;
1159 }
1160
1161 #else /* CONFIG_PM */
1162
1163 #define sdhci_suspend NULL
1164 #define sdhci_resume NULL
1165
1166 #endif /* CONFIG_PM */
1167
1168 /*****************************************************************************\
1169 * *
1170 * Device probing/removal *
1171 * *
1172 \*****************************************************************************/
1173
1174 static int __devinit sdhci_probe_slot(struct pci_dev *pdev, int slot)
1175 {
1176 int ret;
1177 unsigned int version;
1178 struct sdhci_chip *chip;
1179 struct mmc_host *mmc;
1180 struct sdhci_host *host;
1181
1182 u8 first_bar;
1183 unsigned int caps;
1184
1185 chip = pci_get_drvdata(pdev);
1186 BUG_ON(!chip);
1187
1188 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
1189 if (ret)
1190 return ret;
1191
1192 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
1193
1194 if (first_bar > 5) {
1195 printk(KERN_ERR DRIVER_NAME ": Invalid first BAR. Aborting.\n");
1196 return -ENODEV;
1197 }
1198
1199 if (!(pci_resource_flags(pdev, first_bar + slot) & IORESOURCE_MEM)) {
1200 printk(KERN_ERR DRIVER_NAME ": BAR is not iomem. Aborting.\n");
1201 return -ENODEV;
1202 }
1203
1204 if (pci_resource_len(pdev, first_bar + slot) != 0x100) {
1205 printk(KERN_ERR DRIVER_NAME ": Invalid iomem size. "
1206 "You may experience problems.\n");
1207 }
1208
1209 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1210 printk(KERN_ERR DRIVER_NAME ": Vendor specific interface. Aborting.\n");
1211 return -ENODEV;
1212 }
1213
1214 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
1215 printk(KERN_ERR DRIVER_NAME ": Unknown interface. Aborting.\n");
1216 return -ENODEV;
1217 }
1218
1219 mmc = mmc_alloc_host(sizeof(struct sdhci_host), &pdev->dev);
1220 if (!mmc)
1221 return -ENOMEM;
1222
1223 host = mmc_priv(mmc);
1224 host->mmc = mmc;
1225
1226 host->chip = chip;
1227 chip->hosts[slot] = host;
1228
1229 host->bar = first_bar + slot;
1230
1231 host->addr = pci_resource_start(pdev, host->bar);
1232 host->irq = pdev->irq;
1233
1234 DBG("slot %d at 0x%08lx, irq %d\n", slot, host->addr, host->irq);
1235
1236 snprintf(host->slot_descr, 20, "sdhci:slot%d", slot);
1237
1238 ret = pci_request_region(pdev, host->bar, host->slot_descr);
1239 if (ret)
1240 goto free;
1241
1242 host->ioaddr = ioremap_nocache(host->addr,
1243 pci_resource_len(pdev, host->bar));
1244 if (!host->ioaddr) {
1245 ret = -ENOMEM;
1246 goto release;
1247 }
1248
1249 sdhci_reset(host, SDHCI_RESET_ALL);
1250
1251 version = readw(host->ioaddr + SDHCI_HOST_VERSION);
1252 version = (version & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
1253 if (version != 0) {
1254 printk(KERN_ERR "%s: Unknown controller version (%d). "
1255 "You may experience problems.\n", host->slot_descr,
1256 version);
1257 }
1258
1259 caps = readl(host->ioaddr + SDHCI_CAPABILITIES);
1260
1261 if (debug_nodma)
1262 DBG("DMA forced off\n");
1263 else if (debug_forcedma) {
1264 DBG("DMA forced on\n");
1265 host->flags |= SDHCI_USE_DMA;
1266 } else if (chip->quirks & SDHCI_QUIRK_FORCE_DMA)
1267 host->flags |= SDHCI_USE_DMA;
1268 else if ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA)
1269 DBG("Controller doesn't have DMA interface\n");
1270 else if (!(caps & SDHCI_CAN_DO_DMA))
1271 DBG("Controller doesn't have DMA capability\n");
1272 else
1273 host->flags |= SDHCI_USE_DMA;
1274
1275 if (host->flags & SDHCI_USE_DMA) {
1276 if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
1277 printk(KERN_WARNING "%s: No suitable DMA available. "
1278 "Falling back to PIO.\n", host->slot_descr);
1279 host->flags &= ~SDHCI_USE_DMA;
1280 }
1281 }
1282
1283 if (host->flags & SDHCI_USE_DMA)
1284 pci_set_master(pdev);
1285 else /* XXX: Hack to get MMC layer to avoid highmem */
1286 pdev->dma_mask = 0;
1287
1288 host->max_clk =
1289 (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
1290 if (host->max_clk == 0) {
1291 printk(KERN_ERR "%s: Hardware doesn't specify base clock "
1292 "frequency.\n", host->slot_descr);
1293 ret = -ENODEV;
1294 goto unmap;
1295 }
1296 host->max_clk *= 1000000;
1297
1298 host->timeout_clk =
1299 (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
1300 if (host->timeout_clk == 0) {
1301 printk(KERN_ERR "%s: Hardware doesn't specify timeout clock "
1302 "frequency.\n", host->slot_descr);
1303 ret = -ENODEV;
1304 goto unmap;
1305 }
1306 if (caps & SDHCI_TIMEOUT_CLK_UNIT)
1307 host->timeout_clk *= 1000;
1308
1309 /*
1310 * Set host parameters.
1311 */
1312 mmc->ops = &sdhci_ops;
1313 mmc->f_min = host->max_clk / 256;
1314 mmc->f_max = host->max_clk;
1315 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_MULTIWRITE | MMC_CAP_BYTEBLOCK;
1316
1317 if (caps & SDHCI_CAN_DO_HISPD)
1318 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
1319
1320 mmc->ocr_avail = 0;
1321 if (caps & SDHCI_CAN_VDD_330)
1322 mmc->ocr_avail |= MMC_VDD_32_33|MMC_VDD_33_34;
1323 if (caps & SDHCI_CAN_VDD_300)
1324 mmc->ocr_avail |= MMC_VDD_29_30|MMC_VDD_30_31;
1325 if (caps & SDHCI_CAN_VDD_180)
1326 mmc->ocr_avail |= MMC_VDD_165_195;
1327
1328 if (mmc->ocr_avail == 0) {
1329 printk(KERN_ERR "%s: Hardware doesn't report any "
1330 "support voltages.\n", host->slot_descr);
1331 ret = -ENODEV;
1332 goto unmap;
1333 }
1334
1335 spin_lock_init(&host->lock);
1336
1337 /*
1338 * Maximum number of segments. Hardware cannot do scatter lists.
1339 */
1340 if (host->flags & SDHCI_USE_DMA)
1341 mmc->max_hw_segs = 1;
1342 else
1343 mmc->max_hw_segs = 16;
1344 mmc->max_phys_segs = 16;
1345
1346 /*
1347 * Maximum number of sectors in one transfer. Limited by DMA boundary
1348 * size (512KiB).
1349 */
1350 mmc->max_req_size = 524288;
1351
1352 /*
1353 * Maximum segment size. Could be one segment with the maximum number
1354 * of bytes.
1355 */
1356 mmc->max_seg_size = mmc->max_req_size;
1357
1358 /*
1359 * Maximum block size. This varies from controller to controller and
1360 * is specified in the capabilities register.
1361 */
1362 mmc->max_blk_size = (caps & SDHCI_MAX_BLOCK_MASK) >> SDHCI_MAX_BLOCK_SHIFT;
1363 if (mmc->max_blk_size >= 3) {
1364 printk(KERN_WARNING "%s: Invalid maximum block size, assuming 512\n",
1365 host->slot_descr);
1366 mmc->max_blk_size = 512;
1367 } else
1368 mmc->max_blk_size = 512 << mmc->max_blk_size;
1369
1370 /*
1371 * Maximum block count.
1372 */
1373 mmc->max_blk_count = 65535;
1374
1375 /*
1376 * Init tasklets.
1377 */
1378 tasklet_init(&host->card_tasklet,
1379 sdhci_tasklet_card, (unsigned long)host);
1380 tasklet_init(&host->finish_tasklet,
1381 sdhci_tasklet_finish, (unsigned long)host);
1382
1383 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
1384
1385 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
1386 host->slot_descr, host);
1387 if (ret)
1388 goto untasklet;
1389
1390 sdhci_init(host);
1391
1392 #ifdef CONFIG_MMC_DEBUG
1393 sdhci_dumpregs(host);
1394 #endif
1395
1396 mmiowb();
1397
1398 mmc_add_host(mmc);
1399
1400 printk(KERN_INFO "%s: SDHCI at 0x%08lx irq %d %s\n", mmc_hostname(mmc),
1401 host->addr, host->irq,
1402 (host->flags & SDHCI_USE_DMA)?"DMA":"PIO");
1403
1404 return 0;
1405
1406 untasklet:
1407 tasklet_kill(&host->card_tasklet);
1408 tasklet_kill(&host->finish_tasklet);
1409 unmap:
1410 iounmap(host->ioaddr);
1411 release:
1412 pci_release_region(pdev, host->bar);
1413 free:
1414 mmc_free_host(mmc);
1415
1416 return ret;
1417 }
1418
1419 static void sdhci_remove_slot(struct pci_dev *pdev, int slot)
1420 {
1421 struct sdhci_chip *chip;
1422 struct mmc_host *mmc;
1423 struct sdhci_host *host;
1424
1425 chip = pci_get_drvdata(pdev);
1426 host = chip->hosts[slot];
1427 mmc = host->mmc;
1428
1429 chip->hosts[slot] = NULL;
1430
1431 mmc_remove_host(mmc);
1432
1433 sdhci_reset(host, SDHCI_RESET_ALL);
1434
1435 free_irq(host->irq, host);
1436
1437 del_timer_sync(&host->timer);
1438
1439 tasklet_kill(&host->card_tasklet);
1440 tasklet_kill(&host->finish_tasklet);
1441
1442 iounmap(host->ioaddr);
1443
1444 pci_release_region(pdev, host->bar);
1445
1446 mmc_free_host(mmc);
1447 }
1448
1449 static int __devinit sdhci_probe(struct pci_dev *pdev,
1450 const struct pci_device_id *ent)
1451 {
1452 int ret, i;
1453 u8 slots, rev;
1454 struct sdhci_chip *chip;
1455
1456 BUG_ON(pdev == NULL);
1457 BUG_ON(ent == NULL);
1458
1459 pci_read_config_byte(pdev, PCI_CLASS_REVISION, &rev);
1460
1461 printk(KERN_INFO DRIVER_NAME
1462 ": SDHCI controller found at %s [%04x:%04x] (rev %x)\n",
1463 pci_name(pdev), (int)pdev->vendor, (int)pdev->device,
1464 (int)rev);
1465
1466 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
1467 if (ret)
1468 return ret;
1469
1470 slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
1471 DBG("found %d slot(s)\n", slots);
1472 if (slots == 0)
1473 return -ENODEV;
1474
1475 ret = pci_enable_device(pdev);
1476 if (ret)
1477 return ret;
1478
1479 chip = kzalloc(sizeof(struct sdhci_chip) +
1480 sizeof(struct sdhci_host*) * slots, GFP_KERNEL);
1481 if (!chip) {
1482 ret = -ENOMEM;
1483 goto err;
1484 }
1485
1486 chip->pdev = pdev;
1487 chip->quirks = ent->driver_data;
1488
1489 if (debug_quirks)
1490 chip->quirks = debug_quirks;
1491
1492 chip->num_slots = slots;
1493 pci_set_drvdata(pdev, chip);
1494
1495 for (i = 0;i < slots;i++) {
1496 ret = sdhci_probe_slot(pdev, i);
1497 if (ret) {
1498 for (i--;i >= 0;i--)
1499 sdhci_remove_slot(pdev, i);
1500 goto free;
1501 }
1502 }
1503
1504 return 0;
1505
1506 free:
1507 pci_set_drvdata(pdev, NULL);
1508 kfree(chip);
1509
1510 err:
1511 pci_disable_device(pdev);
1512 return ret;
1513 }
1514
1515 static void __devexit sdhci_remove(struct pci_dev *pdev)
1516 {
1517 int i;
1518 struct sdhci_chip *chip;
1519
1520 chip = pci_get_drvdata(pdev);
1521
1522 if (chip) {
1523 for (i = 0;i < chip->num_slots;i++)
1524 sdhci_remove_slot(pdev, i);
1525
1526 pci_set_drvdata(pdev, NULL);
1527
1528 kfree(chip);
1529 }
1530
1531 pci_disable_device(pdev);
1532 }
1533
1534 static struct pci_driver sdhci_driver = {
1535 .name = DRIVER_NAME,
1536 .id_table = pci_ids,
1537 .probe = sdhci_probe,
1538 .remove = __devexit_p(sdhci_remove),
1539 .suspend = sdhci_suspend,
1540 .resume = sdhci_resume,
1541 };
1542
1543 /*****************************************************************************\
1544 * *
1545 * Driver init/exit *
1546 * *
1547 \*****************************************************************************/
1548
1549 static int __init sdhci_drv_init(void)
1550 {
1551 printk(KERN_INFO DRIVER_NAME
1552 ": Secure Digital Host Controller Interface driver\n");
1553 printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
1554
1555 return pci_register_driver(&sdhci_driver);
1556 }
1557
1558 static void __exit sdhci_drv_exit(void)
1559 {
1560 DBG("Exiting\n");
1561
1562 pci_unregister_driver(&sdhci_driver);
1563 }
1564
1565 module_init(sdhci_drv_init);
1566 module_exit(sdhci_drv_exit);
1567
1568 module_param(debug_nodma, uint, 0444);
1569 module_param(debug_forcedma, uint, 0444);
1570 module_param(debug_quirks, uint, 0444);
1571
1572 MODULE_AUTHOR("Pierre Ossman <drzeus@drzeus.cx>");
1573 MODULE_DESCRIPTION("Secure Digital Host Controller Interface driver");
1574 MODULE_LICENSE("GPL");
1575
1576 MODULE_PARM_DESC(debug_nodma, "Forcefully disable DMA transfers. (default 0)");
1577 MODULE_PARM_DESC(debug_forcedma, "Forcefully enable DMA transfers. (default 0)");
1578 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
USB Experimental Work