?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
[PATCH] USB: new devices for the Option driver
[usb.git] / drivers / net / dl2k.c
blob038447fb5c5ee82ef17110189497e029c01d42fd
1 /* D-Link DL2000-based Gigabit Ethernet Adapter Linux driver */
2 /*
3 Copyright (c) 2001, 2002 by D-Link Corporation
4 Written by Edward Peng.<edward_peng@dlink.com.tw>
5 Created 03-May-2001, base on Linux' sundance.c.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11 */
12 /*
13 Rev Date Description
14 ==========================================================================
15 0.01 2001/05/03 Created DL2000-based linux driver
16 0.02 2001/05/21 Added VLAN and hardware checksum support.
17 1.00 2001/06/26 Added jumbo frame support.
18 1.01 2001/08/21 Added two parameters, rx_coalesce and rx_timeout.
19 1.02 2001/10/08 Supported fiber media.
20 Added flow control parameters.
21 1.03 2001/10/12 Changed the default media to 1000mbps_fd for
22 the fiber devices.
23 1.04 2001/11/08 Fixed Tx stopped when tx very busy.
24 1.05 2001/11/22 Fixed Tx stopped when unidirectional tx busy.
25 1.06 2001/12/13 Fixed disconnect bug at 10Mbps mode.
26 Fixed tx_full flag incorrect.
27 Added tx_coalesce paramter.
28 1.07 2002/01/03 Fixed miscount of RX frame error.
29 1.08 2002/01/17 Fixed the multicast bug.
30 1.09 2002/03/07 Move rx-poll-now to re-fill loop.
31 Added rio_timer() to watch rx buffers.
32 1.10 2002/04/16 Fixed miscount of carrier error.
33 1.11 2002/05/23 Added ISR schedule scheme
34 Fixed miscount of rx frame error for DGE-550SX.
35 Fixed VLAN bug.
36 1.12 2002/06/13 Lock tx_coalesce=1 on 10/100Mbps mode.
37 1.13 2002/08/13 1. Fix disconnection (many tx:carrier/rx:frame
38 errs) with some mainboards.
39 2. Use definition "DRV_NAME" "DRV_VERSION"
40 "DRV_RELDATE" for flexibility.
41 1.14 2002/08/14 Support ethtool.
42 1.15 2002/08/27 Changed the default media to Auto-Negotiation
43 for the fiber devices.
44 1.16 2002/09/04 More power down time for fiber devices auto-
45 negotiation.
46 Fix disconnect bug after ifup and ifdown.
47 1.17 2002/10/03 Fix RMON statistics overflow.
48 Always use I/O mapping to access eeprom,
49 avoid system freezing with some chipsets.
50
51 */
52 #define DRV_NAME "D-Link DL2000-based linux driver"
53 #define DRV_VERSION "v1.17b"
54 #define DRV_RELDATE "2006/03/10"
55 #include "dl2k.h"
56 #include <linux/dma-mapping.h>
57
58 static char version[] __devinitdata =
59 KERN_INFO DRV_NAME " " DRV_VERSION " " DRV_RELDATE "\n";
60 #define MAX_UNITS 8
61 static int mtu[MAX_UNITS];
62 static int vlan[MAX_UNITS];
63 static int jumbo[MAX_UNITS];
64 static char *media[MAX_UNITS];
65 static int tx_flow=-1;
66 static int rx_flow=-1;
67 static int copy_thresh;
68 static int rx_coalesce=10; /* Rx frame count each interrupt */
69 static int rx_timeout=200; /* Rx DMA wait time in 640ns increments */
70 static int tx_coalesce=16; /* HW xmit count each TxDMAComplete */
71
72
73 MODULE_AUTHOR ("Edward Peng");
74 MODULE_DESCRIPTION ("D-Link DL2000-based Gigabit Ethernet Adapter");
75 MODULE_LICENSE("GPL");
76 module_param_array(mtu, int, NULL, 0);
77 module_param_array(media, charp, NULL, 0);
78 module_param_array(vlan, int, NULL, 0);
79 module_param_array(jumbo, int, NULL, 0);
80 module_param(tx_flow, int, 0);
81 module_param(rx_flow, int, 0);
82 module_param(copy_thresh, int, 0);
83 module_param(rx_coalesce, int, 0); /* Rx frame count each interrupt */
84 module_param(rx_timeout, int, 0); /* Rx DMA wait time in 64ns increments */
85 module_param(tx_coalesce, int, 0); /* HW xmit count each TxDMAComplete */
86
87
88 /* Enable the default interrupts */
89 #define DEFAULT_INTR (RxDMAComplete | HostError | IntRequested | TxDMAComplete| \
90 UpdateStats | LinkEvent)
91 #define EnableInt() \
92 writew(DEFAULT_INTR, ioaddr + IntEnable)
93
94 static const int max_intrloop = 50;
95 static const int multicast_filter_limit = 0x40;
96
97 static int rio_open (struct net_device *dev);
98 static void rio_timer (unsigned long data);
99 static void rio_tx_timeout (struct net_device *dev);
100 static void alloc_list (struct net_device *dev);
101 static int start_xmit (struct sk_buff *skb, struct net_device *dev);
102 static irqreturn_t rio_interrupt (int irq, void *dev_instance, struct pt_regs *regs);
103 static void rio_free_tx (struct net_device *dev, int irq);
104 static void tx_error (struct net_device *dev, int tx_status);
105 static int receive_packet (struct net_device *dev);
106 static void rio_error (struct net_device *dev, int int_status);
107 static int change_mtu (struct net_device *dev, int new_mtu);
108 static void set_multicast (struct net_device *dev);
109 static struct net_device_stats *get_stats (struct net_device *dev);
110 static int clear_stats (struct net_device *dev);
111 static int rio_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);
112 static int rio_close (struct net_device *dev);
113 static int find_miiphy (struct net_device *dev);
114 static int parse_eeprom (struct net_device *dev);
115 static int read_eeprom (long ioaddr, int eep_addr);
116 static int mii_wait_link (struct net_device *dev, int wait);
117 static int mii_set_media (struct net_device *dev);
118 static int mii_get_media (struct net_device *dev);
119 static int mii_set_media_pcs (struct net_device *dev);
120 static int mii_get_media_pcs (struct net_device *dev);
121 static int mii_read (struct net_device *dev, int phy_addr, int reg_num);
122 static int mii_write (struct net_device *dev, int phy_addr, int reg_num,
123 u16 data);
124
125 static struct ethtool_ops ethtool_ops;
126
127 static int __devinit
128 rio_probe1 (struct pci_dev *pdev, const struct pci_device_id *ent)
129 {
130 struct net_device *dev;
131 struct netdev_private *np;
132 static int card_idx;
133 int chip_idx = ent->driver_data;
134 int err, irq;
135 long ioaddr;
136 static int version_printed;
137 void *ring_space;
138 dma_addr_t ring_dma;
139
140 if (!version_printed++)
141 printk ("%s", version);
142
143 err = pci_enable_device (pdev);
144 if (err)
145 return err;
146
147 irq = pdev->irq;
148 err = pci_request_regions (pdev, "dl2k");
149 if (err)
150 goto err_out_disable;
151
152 pci_set_master (pdev);
153 dev = alloc_etherdev (sizeof (*np));
154 if (!dev) {
155 err = -ENOMEM;
156 goto err_out_res;
157 }
158 SET_MODULE_OWNER (dev);
159 SET_NETDEV_DEV(dev, &pdev->dev);
160
161 #ifdef MEM_MAPPING
162 ioaddr = pci_resource_start (pdev, 1);
163 ioaddr = (long) ioremap (ioaddr, RIO_IO_SIZE);
164 if (!ioaddr) {
165 err = -ENOMEM;
166 goto err_out_dev;
167 }
168 #else
169 ioaddr = pci_resource_start (pdev, 0);
170 #endif
171 dev->base_addr = ioaddr;
172 dev->irq = irq;
173 np = netdev_priv(dev);
174 np->chip_id = chip_idx;
175 np->pdev = pdev;
176 spin_lock_init (&np->tx_lock);
177 spin_lock_init (&np->rx_lock);
178
179 /* Parse manual configuration */
180 np->an_enable = 1;
181 np->tx_coalesce = 1;
182 if (card_idx < MAX_UNITS) {
183 if (media[card_idx] != NULL) {
184 np->an_enable = 0;
185 if (strcmp (media[card_idx], "auto") == 0 ||
186 strcmp (media[card_idx], "autosense") == 0 ||
187 strcmp (media[card_idx], "0") == 0 ) {
188 np->an_enable = 2;
189 } else if (strcmp (media[card_idx], "100mbps_fd") == 0 ||
190 strcmp (media[card_idx], "4") == 0) {
191 np->speed = 100;
192 np->full_duplex = 1;
193 } else if (strcmp (media[card_idx], "100mbps_hd") == 0
194 || strcmp (media[card_idx], "3") == 0) {
195 np->speed = 100;
196 np->full_duplex = 0;
197 } else if (strcmp (media[card_idx], "10mbps_fd") == 0 ||
198 strcmp (media[card_idx], "2") == 0) {
199 np->speed = 10;
200 np->full_duplex = 1;
201 } else if (strcmp (media[card_idx], "10mbps_hd") == 0 ||
202 strcmp (media[card_idx], "1") == 0) {
203 np->speed = 10;
204 np->full_duplex = 0;
205 } else if (strcmp (media[card_idx], "1000mbps_fd") == 0 ||
206 strcmp (media[card_idx], "6") == 0) {
207 np->speed=1000;
208 np->full_duplex=1;
209 } else if (strcmp (media[card_idx], "1000mbps_hd") == 0 ||
210 strcmp (media[card_idx], "5") == 0) {
211 np->speed = 1000;
212 np->full_duplex = 0;
213 } else {
214 np->an_enable = 1;
215 }
216 }
217 if (jumbo[card_idx] != 0) {
218 np->jumbo = 1;
219 dev->mtu = MAX_JUMBO;
220 } else {
221 np->jumbo = 0;
222 if (mtu[card_idx] > 0 && mtu[card_idx] < PACKET_SIZE)
223 dev->mtu = mtu[card_idx];
224 }
225 np->vlan = (vlan[card_idx] > 0 && vlan[card_idx] < 4096) ?
226 vlan[card_idx] : 0;
227 if (rx_coalesce > 0 && rx_timeout > 0) {
228 np->rx_coalesce = rx_coalesce;
229 np->rx_timeout = rx_timeout;
230 np->coalesce = 1;
231 }
232 np->tx_flow = (tx_flow == 0) ? 0 : 1;
233 np->rx_flow = (rx_flow == 0) ? 0 : 1;
234
235 if (tx_coalesce < 1)
236 tx_coalesce = 1;
237 else if (tx_coalesce > TX_RING_SIZE-1)
238 tx_coalesce = TX_RING_SIZE - 1;
239 }
240 dev->open = &rio_open;
241 dev->hard_start_xmit = &start_xmit;
242 dev->stop = &rio_close;
243 dev->get_stats = &get_stats;
244 dev->set_multicast_list = &set_multicast;
245 dev->do_ioctl = &rio_ioctl;
246 dev->tx_timeout = &rio_tx_timeout;
247 dev->watchdog_timeo = TX_TIMEOUT;
248 dev->change_mtu = &change_mtu;
249 SET_ETHTOOL_OPS(dev, &ethtool_ops);
250 #if 0
251 dev->features = NETIF_F_IP_CSUM;
252 #endif
253 pci_set_drvdata (pdev, dev);
254
255 ring_space = pci_alloc_consistent (pdev, TX_TOTAL_SIZE, &ring_dma);
256 if (!ring_space)
257 goto err_out_iounmap;
258 np->tx_ring = (struct netdev_desc *) ring_space;
259 np->tx_ring_dma = ring_dma;
260
261 ring_space = pci_alloc_consistent (pdev, RX_TOTAL_SIZE, &ring_dma);
262 if (!ring_space)
263 goto err_out_unmap_tx;
264 np->rx_ring = (struct netdev_desc *) ring_space;
265 np->rx_ring_dma = ring_dma;
266
267 /* Parse eeprom data */
268 parse_eeprom (dev);
269
270 /* Find PHY address */
271 err = find_miiphy (dev);
272 if (err)
273 goto err_out_unmap_rx;
274
275 /* Fiber device? */
276 np->phy_media = (readw(ioaddr + ASICCtrl) & PhyMedia) ? 1 : 0;
277 np->link_status = 0;
278 /* Set media and reset PHY */
279 if (np->phy_media) {
280 /* default Auto-Negotiation for fiber deivices */
281 if (np->an_enable == 2) {
282 np->an_enable = 1;
283 }
284 mii_set_media_pcs (dev);
285 } else {
286 /* Auto-Negotiation is mandatory for 1000BASE-T,
287 IEEE 802.3ab Annex 28D page 14 */
288 if (np->speed == 1000)
289 np->an_enable = 1;
290 mii_set_media (dev);
291 }
292 pci_read_config_byte(pdev, PCI_REVISION_ID, &np->pci_rev_id);
293
294 err = register_netdev (dev);
295 if (err)
296 goto err_out_unmap_rx;
297
298 card_idx++;
299
300 printk (KERN_INFO "%s: %s, %02x:%02x:%02x:%02x:%02x:%02x, IRQ %d\n",
301 dev->name, np->name,
302 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
303 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5], irq);
304 if (tx_coalesce > 1)
305 printk(KERN_INFO "tx_coalesce:\t%d packets\n",
306 tx_coalesce);
307 if (np->coalesce)
308 printk(KERN_INFO "rx_coalesce:\t%d packets\n"
309 KERN_INFO "rx_timeout: \t%d ns\n",
310 np->rx_coalesce, np->rx_timeout*640);
311 if (np->vlan)
312 printk(KERN_INFO "vlan(id):\t%d\n", np->vlan);
313 return 0;
314
315 err_out_unmap_rx:
316 pci_free_consistent (pdev, RX_TOTAL_SIZE, np->rx_ring, np->rx_ring_dma);
317 err_out_unmap_tx:
318 pci_free_consistent (pdev, TX_TOTAL_SIZE, np->tx_ring, np->tx_ring_dma);
319 err_out_iounmap:
320 #ifdef MEM_MAPPING
321 iounmap ((void *) ioaddr);
322
323 err_out_dev:
324 #endif
325 free_netdev (dev);
326
327 err_out_res:
328 pci_release_regions (pdev);
329
330 err_out_disable:
331 pci_disable_device (pdev);
332 return err;
333 }
334
335 int
336 find_miiphy (struct net_device *dev)
337 {
338 int i, phy_found = 0;
339 struct netdev_private *np;
340 long ioaddr;
341 np = netdev_priv(dev);
342 ioaddr = dev->base_addr;
343 np->phy_addr = 1;
344
345 for (i = 31; i >= 0; i--) {
346 int mii_status = mii_read (dev, i, 1);
347 if (mii_status != 0xffff && mii_status != 0x0000) {
348 np->phy_addr = i;
349 phy_found++;
350 }
351 }
352 if (!phy_found) {
353 printk (KERN_ERR "%s: No MII PHY found!\n", dev->name);
354 return -ENODEV;
355 }
356 return 0;
357 }
358
359 int
360 parse_eeprom (struct net_device *dev)
361 {
362 int i, j;
363 long ioaddr = dev->base_addr;
364 u8 sromdata[256];
365 u8 *psib;
366 u32 crc;
367 PSROM_t psrom = (PSROM_t) sromdata;
368 struct netdev_private *np = netdev_priv(dev);
369
370 int cid, next;
371
372 #ifdef MEM_MAPPING
373 ioaddr = pci_resource_start (np->pdev, 0);
374 #endif
375 /* Read eeprom */
376 for (i = 0; i < 128; i++) {
377 ((u16 *) sromdata)[i] = le16_to_cpu (read_eeprom (ioaddr, i));
378 }
379 #ifdef MEM_MAPPING
380 ioaddr = dev->base_addr;
381 #endif
382 /* Check CRC */
383 crc = ~ether_crc_le (256 - 4, sromdata);
384 if (psrom->crc != crc) {
385 printk (KERN_ERR "%s: EEPROM data CRC error.\n", dev->name);
386 return -1;
387 }
388
389 /* Set MAC address */
390 for (i = 0; i < 6; i++)
391 dev->dev_addr[i] = psrom->mac_addr[i];
392
393 /* Parse Software Infomation Block */
394 i = 0x30;
395 psib = (u8 *) sromdata;
396 do {
397 cid = psib[i++];
398 next = psib[i++];
399 if ((cid == 0 && next == 0) || (cid == 0xff && next == 0xff)) {
400 printk (KERN_ERR "Cell data error\n");
401 return -1;
402 }
403 switch (cid) {
404 case 0: /* Format version */
405 break;
406 case 1: /* End of cell */
407 return 0;
408 case 2: /* Duplex Polarity */
409 np->duplex_polarity = psib[i];
410 writeb (readb (ioaddr + PhyCtrl) | psib[i],
411 ioaddr + PhyCtrl);
412 break;
413 case 3: /* Wake Polarity */
414 np->wake_polarity = psib[i];
415 break;
416 case 9: /* Adapter description */
417 j = (next - i > 255) ? 255 : next - i;
418 memcpy (np->name, &(psib[i]), j);
419 break;
420 case 4:
421 case 5:
422 case 6:
423 case 7:
424 case 8: /* Reversed */
425 break;
426 default: /* Unknown cell */
427 return -1;
428 }
429 i = next;
430 } while (1);
431
432 return 0;
433 }
434
435 static int
436 rio_open (struct net_device *dev)
437 {
438 struct netdev_private *np = netdev_priv(dev);
439 long ioaddr = dev->base_addr;
440 int i;
441 u16 macctrl;
442
443 i = request_irq (dev->irq, &rio_interrupt, SA_SHIRQ, dev->name, dev);
444 if (i)
445 return i;
446
447 /* Reset all logic functions */
448 writew (GlobalReset | DMAReset | FIFOReset | NetworkReset | HostReset,
449 ioaddr + ASICCtrl + 2);
450 mdelay(10);
451
452 /* DebugCtrl bit 4, 5, 9 must set */
453 writel (readl (ioaddr + DebugCtrl) | 0x0230, ioaddr + DebugCtrl);
454
455 /* Jumbo frame */
456 if (np->jumbo != 0)
457 writew (MAX_JUMBO+14, ioaddr + MaxFrameSize);
458
459 alloc_list (dev);
460
461 /* Get station address */
462 for (i = 0; i < 6; i++)
463 writeb (dev->dev_addr[i], ioaddr + StationAddr0 + i);
464
465 set_multicast (dev);
466 if (np->coalesce) {
467 writel (np->rx_coalesce | np->rx_timeout << 16,
468 ioaddr + RxDMAIntCtrl);
469 }
470 /* Set RIO to poll every N*320nsec. */
471 writeb (0x20, ioaddr + RxDMAPollPeriod);
472 writeb (0xff, ioaddr + TxDMAPollPeriod);
473 writeb (0x30, ioaddr + RxDMABurstThresh);
474 writeb (0x30, ioaddr + RxDMAUrgentThresh);
475 writel (0x0007ffff, ioaddr + RmonStatMask);
476 /* clear statistics */
477 clear_stats (dev);
478
479 /* VLAN supported */
480 if (np->vlan) {
481 /* priority field in RxDMAIntCtrl */
482 writel (readl(ioaddr + RxDMAIntCtrl) | 0x7 << 10,
483 ioaddr + RxDMAIntCtrl);
484 /* VLANId */
485 writew (np->vlan, ioaddr + VLANId);
486 /* Length/Type should be 0x8100 */
487 writel (0x8100 << 16 | np->vlan, ioaddr + VLANTag);
488 /* Enable AutoVLANuntagging, but disable AutoVLANtagging.
489 VLAN information tagged by TFC' VID, CFI fields. */
490 writel (readl (ioaddr + MACCtrl) | AutoVLANuntagging,
491 ioaddr + MACCtrl);
492 }
493
494 init_timer (&np->timer);
495 np->timer.expires = jiffies + 1*HZ;
496 np->timer.data = (unsigned long) dev;
497 np->timer.function = &rio_timer;
498 add_timer (&np->timer);
499
500 /* Start Tx/Rx */
501 writel (readl (ioaddr + MACCtrl) | StatsEnable | RxEnable | TxEnable,
502 ioaddr + MACCtrl);
503
504 macctrl = 0;
505 macctrl |= (np->vlan) ? AutoVLANuntagging : 0;
506 macctrl |= (np->full_duplex) ? DuplexSelect : 0;
507 macctrl |= (np->tx_flow) ? TxFlowControlEnable : 0;
508 macctrl |= (np->rx_flow) ? RxFlowControlEnable : 0;
509 writew(macctrl, ioaddr + MACCtrl);
510
511 netif_start_queue (dev);
512
513 /* Enable default interrupts */
514 EnableInt ();
515 return 0;
516 }
517
518 static void
519 rio_timer (unsigned long data)
520 {
521 struct net_device *dev = (struct net_device *)data;
522 struct netdev_private *np = netdev_priv(dev);
523 unsigned int entry;
524 int next_tick = 1*HZ;
525 unsigned long flags;
526
527 spin_lock_irqsave(&np->rx_lock, flags);
528 /* Recover rx ring exhausted error */
529 if (np->cur_rx - np->old_rx >= RX_RING_SIZE) {
530 printk(KERN_INFO "Try to recover rx ring exhausted...\n");
531 /* Re-allocate skbuffs to fill the descriptor ring */
532 for (; np->cur_rx - np->old_rx > 0; np->old_rx++) {
533 struct sk_buff *skb;
534 entry = np->old_rx % RX_RING_SIZE;
535 /* Dropped packets don't need to re-allocate */
536 if (np->rx_skbuff[entry] == NULL) {
537 skb = dev_alloc_skb (np->rx_buf_sz);
538 if (skb == NULL) {
539 np->rx_ring[entry].fraginfo = 0;
540 printk (KERN_INFO
541 "%s: Still unable to re-allocate Rx skbuff.#%d\n",
542 dev->name, entry);
543 break;
544 }
545 np->rx_skbuff[entry] = skb;
546 skb->dev = dev;
547 /* 16 byte align the IP header */
548 skb_reserve (skb, 2);
549 np->rx_ring[entry].fraginfo =
550 cpu_to_le64 (pci_map_single
551 (np->pdev, skb->data, np->rx_buf_sz,
552 PCI_DMA_FROMDEVICE));
553 }
554 np->rx_ring[entry].fraginfo |=
555 cpu_to_le64 (np->rx_buf_sz) << 48;
556 np->rx_ring[entry].status = 0;
557 } /* end for */
558 } /* end if */
559 spin_unlock_irqrestore (&np->rx_lock, flags);
560 np->timer.expires = jiffies + next_tick;
561 add_timer(&np->timer);
562 }
563
564 static void
565 rio_tx_timeout (struct net_device *dev)
566 {
567 long ioaddr = dev->base_addr;
568
569 printk (KERN_INFO "%s: Tx timed out (%4.4x), is buffer full?\n",
570 dev->name, readl (ioaddr + TxStatus));
571 rio_free_tx(dev, 0);
572 dev->if_port = 0;
573 dev->trans_start = jiffies;
574 }
575
576 /* allocate and initialize Tx and Rx descriptors */
577 static void
578 alloc_list (struct net_device *dev)
579 {
580 struct netdev_private *np = netdev_priv(dev);
581 int i;
582
583 np->cur_rx = np->cur_tx = 0;
584 np->old_rx = np->old_tx = 0;
585 np->rx_buf_sz = (dev->mtu <= 1500 ? PACKET_SIZE : dev->mtu + 32);
586
587 /* Initialize Tx descriptors, TFDListPtr leaves in start_xmit(). */
588 for (i = 0; i < TX_RING_SIZE; i++) {
589 np->tx_skbuff[i] = NULL;
590 np->tx_ring[i].status = cpu_to_le64 (TFDDone);
591 np->tx_ring[i].next_desc = cpu_to_le64 (np->tx_ring_dma +
592 ((i+1)%TX_RING_SIZE) *
593 sizeof (struct netdev_desc));
594 }
595
596 /* Initialize Rx descriptors */
597 for (i = 0; i < RX_RING_SIZE; i++) {
598 np->rx_ring[i].next_desc = cpu_to_le64 (np->rx_ring_dma +
599 ((i + 1) % RX_RING_SIZE) *
600 sizeof (struct netdev_desc));
601 np->rx_ring[i].status = 0;
602 np->rx_ring[i].fraginfo = 0;
603 np->rx_skbuff[i] = NULL;
604 }
605
606 /* Allocate the rx buffers */
607 for (i = 0; i < RX_RING_SIZE; i++) {
608 /* Allocated fixed size of skbuff */
609 struct sk_buff *skb = dev_alloc_skb (np->rx_buf_sz);
610 np->rx_skbuff[i] = skb;
611 if (skb == NULL) {
612 printk (KERN_ERR
613 "%s: alloc_list: allocate Rx buffer error! ",
614 dev->name);
615 break;
616 }
617 skb->dev = dev; /* Mark as being used by this device. */
618 skb_reserve (skb, 2); /* 16 byte align the IP header. */
619 /* Rubicon now supports 40 bits of addressing space. */
620 np->rx_ring[i].fraginfo =
621 cpu_to_le64 ( pci_map_single (
622 np->pdev, skb->data, np->rx_buf_sz,
623 PCI_DMA_FROMDEVICE));
624 np->rx_ring[i].fraginfo |= cpu_to_le64 (np->rx_buf_sz) << 48;
625 }
626
627 /* Set RFDListPtr */
628 writel (cpu_to_le32 (np->rx_ring_dma), dev->base_addr + RFDListPtr0);
629 writel (0, dev->base_addr + RFDListPtr1);
630
631 return;
632 }
633
634 static int
635 start_xmit (struct sk_buff *skb, struct net_device *dev)
636 {
637 struct netdev_private *np = netdev_priv(dev);
638 struct netdev_desc *txdesc;
639 unsigned entry;
640 u32 ioaddr;
641 u64 tfc_vlan_tag = 0;
642
643 if (np->link_status == 0) { /* Link Down */
644 dev_kfree_skb(skb);
645 return 0;
646 }
647 ioaddr = dev->base_addr;
648 entry = np->cur_tx % TX_RING_SIZE;
649 np->tx_skbuff[entry] = skb;
650 txdesc = &np->tx_ring[entry];
651
652 #if 0
653 if (skb->ip_summed == CHECKSUM_HW) {
654 txdesc->status |=
655 cpu_to_le64 (TCPChecksumEnable | UDPChecksumEnable |
656 IPChecksumEnable);
657 }
658 #endif
659 if (np->vlan) {
660 tfc_vlan_tag =
661 cpu_to_le64 (VLANTagInsert) |
662 (cpu_to_le64 (np->vlan) << 32) |
663 (cpu_to_le64 (skb->priority) << 45);
664 }
665 txdesc->fraginfo = cpu_to_le64 (pci_map_single (np->pdev, skb->data,
666 skb->len,
667 PCI_DMA_TODEVICE));
668 txdesc->fraginfo |= cpu_to_le64 (skb->len) << 48;
669
670 /* DL2K bug: DMA fails to get next descriptor ptr in 10Mbps mode
671 * Work around: Always use 1 descriptor in 10Mbps mode */
672 if (entry % np->tx_coalesce == 0 || np->speed == 10)
673 txdesc->status = cpu_to_le64 (entry | tfc_vlan_tag |
674 WordAlignDisable |
675 TxDMAIndicate |
676 (1 << FragCountShift));
677 else
678 txdesc->status = cpu_to_le64 (entry | tfc_vlan_tag |
679 WordAlignDisable |
680 (1 << FragCountShift));
681
682 /* TxDMAPollNow */
683 writel (readl (ioaddr + DMACtrl) | 0x00001000, ioaddr + DMACtrl);
684 /* Schedule ISR */
685 writel(10000, ioaddr + CountDown);
686 np->cur_tx = (np->cur_tx + 1) % TX_RING_SIZE;
687 if ((np->cur_tx - np->old_tx + TX_RING_SIZE) % TX_RING_SIZE
688 < TX_QUEUE_LEN - 1 && np->speed != 10) {
689 /* do nothing */
690 } else if (!netif_queue_stopped(dev)) {
691 netif_stop_queue (dev);
692 }
693
694 /* The first TFDListPtr */
695 if (readl (dev->base_addr + TFDListPtr0) == 0) {
696 writel (np->tx_ring_dma + entry * sizeof (struct netdev_desc),
697 dev->base_addr + TFDListPtr0);
698 writel (0, dev->base_addr + TFDListPtr1);
699 }
700
701 /* NETDEV WATCHDOG timer */
702 dev->trans_start = jiffies;
703 return 0;
704 }
705
706 static irqreturn_t
707 rio_interrupt (int irq, void *dev_instance, struct pt_regs *rgs)
708 {
709 struct net_device *dev = dev_instance;
710 struct netdev_private *np;
711 unsigned int_status;
712 long ioaddr;
713 int cnt = max_intrloop;
714 int handled = 0;
715
716 ioaddr = dev->base_addr;
717 np = netdev_priv(dev);
718 while (1) {
719 int_status = readw (ioaddr + IntStatus);
720 writew (int_status, ioaddr + IntStatus);
721 int_status &= DEFAULT_INTR;
722 if (int_status == 0 || --cnt < 0)
723 break;
724 handled = 1;
725 /* Processing received packets */
726 if (int_status & RxDMAComplete)
727 receive_packet (dev);
728 /* TxDMAComplete interrupt */
729 if ((int_status & (TxDMAComplete|IntRequested))) {
730 int tx_status;
731 tx_status = readl (ioaddr + TxStatus);
732 if (tx_status & 0x01)
733 tx_error (dev, tx_status);
734 /* Free used tx skbuffs */
735 rio_free_tx (dev, 1);
736 }
737
738 /* Handle uncommon events */
739 if (int_status &
740 (HostError | LinkEvent | UpdateStats))
741 rio_error (dev, int_status);
742 }
743 if (np->cur_tx != np->old_tx)
744 writel (100, ioaddr + CountDown);
745 return IRQ_RETVAL(handled);
746 }
747
748 static void
749 rio_free_tx (struct net_device *dev, int irq)
750 {
751 struct netdev_private *np = netdev_priv(dev);
752 int entry = np->old_tx % TX_RING_SIZE;
753 int tx_use = 0;
754 unsigned long flag = 0;
755
756 if (irq)
757 spin_lock(&np->tx_lock);
758 else
759 spin_lock_irqsave(&np->tx_lock, flag);
760
761 /* Free used tx skbuffs */
762 while (entry != np->cur_tx) {
763 struct sk_buff *skb;
764
765 if (!(np->tx_ring[entry].status & TFDDone))
766 break;
767 skb = np->tx_skbuff[entry];
768 pci_unmap_single (np->pdev,
769 np->tx_ring[entry].fraginfo & DMA_48BIT_MASK,
770 skb->len, PCI_DMA_TODEVICE);
771 if (irq)
772 dev_kfree_skb_irq (skb);
773 else
774 dev_kfree_skb (skb);
775
776 np->tx_skbuff[entry] = NULL;
777 entry = (entry + 1) % TX_RING_SIZE;
778 tx_use++;
779 }
780 if (irq)
781 spin_unlock(&np->tx_lock);
782 else
783 spin_unlock_irqrestore(&np->tx_lock, flag);
784 np->old_tx = entry;
785
786 /* If the ring is no longer full, clear tx_full and
787 call netif_wake_queue() */
788
789 if (netif_queue_stopped(dev) &&
790 ((np->cur_tx - np->old_tx + TX_RING_SIZE) % TX_RING_SIZE
791 < TX_QUEUE_LEN - 1 || np->speed == 10)) {
792 netif_wake_queue (dev);
793 }
794 }
795
796 static void
797 tx_error (struct net_device *dev, int tx_status)
798 {
799 struct netdev_private *np;
800 long ioaddr = dev->base_addr;
801 int frame_id;
802 int i;
803
804 np = netdev_priv(dev);
805
806 frame_id = (tx_status & 0xffff0000);
807 printk (KERN_ERR "%s: Transmit error, TxStatus %4.4x, FrameId %d.\n",
808 dev->name, tx_status, frame_id);
809 np->stats.tx_errors++;
810 /* Ttransmit Underrun */
811 if (tx_status & 0x10) {
812 np->stats.tx_fifo_errors++;
813 writew (readw (ioaddr + TxStartThresh) + 0x10,
814 ioaddr + TxStartThresh);
815 /* Transmit Underrun need to set TxReset, DMARest, FIFOReset */
816 writew (TxReset | DMAReset | FIFOReset | NetworkReset,
817 ioaddr + ASICCtrl + 2);
818 /* Wait for ResetBusy bit clear */
819 for (i = 50; i > 0; i--) {
820 if ((readw (ioaddr + ASICCtrl + 2) & ResetBusy) == 0)
821 break;
822 mdelay (1);
823 }
824 rio_free_tx (dev, 1);
825 /* Reset TFDListPtr */
826 writel (np->tx_ring_dma +
827 np->old_tx * sizeof (struct netdev_desc),
828 dev->base_addr + TFDListPtr0);
829 writel (0, dev->base_addr + TFDListPtr1);
830
831 /* Let TxStartThresh stay default value */
832 }
833 /* Late Collision */
834 if (tx_status & 0x04) {
835 np->stats.tx_fifo_errors++;
836 /* TxReset and clear FIFO */
837 writew (TxReset | FIFOReset, ioaddr + ASICCtrl + 2);
838 /* Wait reset done */
839 for (i = 50; i > 0; i--) {
840 if ((readw (ioaddr + ASICCtrl + 2) & ResetBusy) == 0)
841 break;
842 mdelay (1);
843 }
844 /* Let TxStartThresh stay default value */
845 }
846 /* Maximum Collisions */
847 #ifdef ETHER_STATS
848 if (tx_status & 0x08)
849 np->stats.collisions16++;
850 #else
851 if (tx_status & 0x08)
852 np->stats.collisions++;
853 #endif
854 /* Restart the Tx */
855 writel (readw (dev->base_addr + MACCtrl) | TxEnable, ioaddr + MACCtrl);
856 }
857
858 static int
859 receive_packet (struct net_device *dev)
860 {
861 struct netdev_private *np = netdev_priv(dev);
862 int entry = np->cur_rx % RX_RING_SIZE;
863 int cnt = 30;
864
865 /* If RFDDone, FrameStart and FrameEnd set, there is a new packet in. */
866 while (1) {
867 struct netdev_desc *desc = &np->rx_ring[entry];
868 int pkt_len;
869 u64 frame_status;
870
871 if (!(desc->status & RFDDone) ||
872 !(desc->status & FrameStart) || !(desc->status & FrameEnd))
873 break;
874
875 /* Chip omits the CRC. */
876 pkt_len = le64_to_cpu (desc->status & 0xffff);
877 frame_status = le64_to_cpu (desc->status);
878 if (--cnt < 0)
879 break;
880 /* Update rx error statistics, drop packet. */
881 if (frame_status & RFS_Errors) {
882 np->stats.rx_errors++;
883 if (frame_status & (RxRuntFrame | RxLengthError))
884 np->stats.rx_length_errors++;
885 if (frame_status & RxFCSError)
886 np->stats.rx_crc_errors++;
887 if (frame_status & RxAlignmentError && np->speed != 1000)
888 np->stats.rx_frame_errors++;
889 if (frame_status & RxFIFOOverrun)
890 np->stats.rx_fifo_errors++;
891 } else {
892 struct sk_buff *skb;
893
894 /* Small skbuffs for short packets */
895 if (pkt_len > copy_thresh) {
896 pci_unmap_single (np->pdev,
897 desc->fraginfo & DMA_48BIT_MASK,
898 np->rx_buf_sz,
899 PCI_DMA_FROMDEVICE);
900 skb_put (skb = np->rx_skbuff[entry], pkt_len);
901 np->rx_skbuff[entry] = NULL;
902 } else if ((skb = dev_alloc_skb (pkt_len + 2)) != NULL) {
903 pci_dma_sync_single_for_cpu(np->pdev,
904 desc->fraginfo &
905 DMA_48BIT_MASK,
906 np->rx_buf_sz,
907 PCI_DMA_FROMDEVICE);
908 skb->dev = dev;
909 /* 16 byte align the IP header */
910 skb_reserve (skb, 2);
911 eth_copy_and_sum (skb,
912 np->rx_skbuff[entry]->data,
913 pkt_len, 0);
914 skb_put (skb, pkt_len);
915 pci_dma_sync_single_for_device(np->pdev,
916 desc->fraginfo &
917 DMA_48BIT_MASK,
918 np->rx_buf_sz,
919 PCI_DMA_FROMDEVICE);
920 }
921 skb->protocol = eth_type_trans (skb, dev);
922 #if 0
923 /* Checksum done by hw, but csum value unavailable. */
924 if (np->pci_rev_id >= 0x0c &&
925 !(frame_status & (TCPError | UDPError | IPError))) {
926 skb->ip_summed = CHECKSUM_UNNECESSARY;
927 }
928 #endif
929 netif_rx (skb);
930 dev->last_rx = jiffies;
931 }
932 entry = (entry + 1) % RX_RING_SIZE;
933 }
934 spin_lock(&np->rx_lock);
935 np->cur_rx = entry;
936 /* Re-allocate skbuffs to fill the descriptor ring */
937 entry = np->old_rx;
938 while (entry != np->cur_rx) {
939 struct sk_buff *skb;
940 /* Dropped packets don't need to re-allocate */
941 if (np->rx_skbuff[entry] == NULL) {
942 skb = dev_alloc_skb (np->rx_buf_sz);
943 if (skb == NULL) {
944 np->rx_ring[entry].fraginfo = 0;
945 printk (KERN_INFO
946 "%s: receive_packet: "
947 "Unable to re-allocate Rx skbuff.#%d\n",
948 dev->name, entry);
949 break;
950 }
951 np->rx_skbuff[entry] = skb;
952 skb->dev = dev;
953 /* 16 byte align the IP header */
954 skb_reserve (skb, 2);
955 np->rx_ring[entry].fraginfo =
956 cpu_to_le64 (pci_map_single
957 (np->pdev, skb->data, np->rx_buf_sz,
958 PCI_DMA_FROMDEVICE));
959 }
960 np->rx_ring[entry].fraginfo |=
961 cpu_to_le64 (np->rx_buf_sz) << 48;
962 np->rx_ring[entry].status = 0;
963 entry = (entry + 1) % RX_RING_SIZE;
964 }
965 np->old_rx = entry;
966 spin_unlock(&np->rx_lock);
967 return 0;
968 }
969
970 static void
971 rio_error (struct net_device *dev, int int_status)
972 {
973 long ioaddr = dev->base_addr;
974 struct netdev_private *np = netdev_priv(dev);
975 u16 macctrl;
976
977 /* Link change event */
978 if (int_status & LinkEvent) {
979 if (mii_wait_link (dev, 10) == 0) {
980 printk (KERN_INFO "%s: Link up\n", dev->name);
981 if (np->phy_media)
982 mii_get_media_pcs (dev);
983 else
984 mii_get_media (dev);
985 if (np->speed == 1000)
986 np->tx_coalesce = tx_coalesce;
987 else
988 np->tx_coalesce = 1;
989 macctrl = 0;
990 macctrl |= (np->vlan) ? AutoVLANuntagging : 0;
991 macctrl |= (np->full_duplex) ? DuplexSelect : 0;
992 macctrl |= (np->tx_flow) ?
993 TxFlowControlEnable : 0;
994 macctrl |= (np->rx_flow) ?
995 RxFlowControlEnable : 0;
996 writew(macctrl, ioaddr + MACCtrl);
997 np->link_status = 1;
998 netif_carrier_on(dev);
999 } else {
1000 printk (KERN_INFO "%s: Link off\n", dev->name);
1001 np->link_status = 0;
1002 netif_carrier_off(dev);
1003 }
1004 }
1005
1006 /* UpdateStats statistics registers */
1007 if (int_status & UpdateStats) {
1008 get_stats (dev);
1009 }
1010
1011 /* PCI Error, a catastronphic error related to the bus interface
1012 occurs, set GlobalReset and HostReset to reset. */
1013 if (int_status & HostError) {
1014 printk (KERN_ERR "%s: HostError! IntStatus %4.4x.\n",
1015 dev->name, int_status);
1016 writew (GlobalReset | HostReset, ioaddr + ASICCtrl + 2);
1017 mdelay (500);
1018 }
1019 }
1020
1021 static struct net_device_stats *
1022 get_stats (struct net_device *dev)
1023 {
1024 long ioaddr = dev->base_addr;
1025 struct netdev_private *np = netdev_priv(dev);
1026 #ifdef MEM_MAPPING
1027 int i;
1028 #endif
1029 unsigned int stat_reg;
1030
1031 /* All statistics registers need to be acknowledged,
1032 else statistic overflow could cause problems */
1033
1034 np->stats.rx_packets += readl (ioaddr + FramesRcvOk);
1035 np->stats.tx_packets += readl (ioaddr + FramesXmtOk);
1036 np->stats.rx_bytes += readl (ioaddr + OctetRcvOk);
1037 np->stats.tx_bytes += readl (ioaddr + OctetXmtOk);
1038
1039 np->stats.multicast = readl (ioaddr + McstFramesRcvdOk);
1040 np->stats.collisions += readl (ioaddr + SingleColFrames)
1041 + readl (ioaddr + MultiColFrames);
1042
1043 /* detailed tx errors */
1044 stat_reg = readw (ioaddr + FramesAbortXSColls);
1045 np->stats.tx_aborted_errors += stat_reg;
1046 np->stats.tx_errors += stat_reg;
1047
1048 stat_reg = readw (ioaddr + CarrierSenseErrors);
1049 np->stats.tx_carrier_errors += stat_reg;
1050 np->stats.tx_errors += stat_reg;
1051
1052 /* Clear all other statistic register. */
1053 readl (ioaddr + McstOctetXmtOk);
1054 readw (ioaddr + BcstFramesXmtdOk);
1055 readl (ioaddr + McstFramesXmtdOk);
1056 readw (ioaddr + BcstFramesRcvdOk);
1057 readw (ioaddr + MacControlFramesRcvd);
1058 readw (ioaddr + FrameTooLongErrors);
1059 readw (ioaddr + InRangeLengthErrors);
1060 readw (ioaddr + FramesCheckSeqErrors);
1061 readw (ioaddr + FramesLostRxErrors);
1062 readl (ioaddr + McstOctetXmtOk);
1063 readl (ioaddr + BcstOctetXmtOk);
1064 readl (ioaddr + McstFramesXmtdOk);
1065 readl (ioaddr + FramesWDeferredXmt);
1066 readl (ioaddr + LateCollisions);
1067 readw (ioaddr + BcstFramesXmtdOk);
1068 readw (ioaddr + MacControlFramesXmtd);
1069 readw (ioaddr + FramesWEXDeferal);
1070
1071 #ifdef MEM_MAPPING
1072 for (i = 0x100; i <= 0x150; i += 4)
1073 readl (ioaddr + i);
1074 #endif
1075 readw (ioaddr + TxJumboFrames);
1076 readw (ioaddr + RxJumboFrames);
1077 readw (ioaddr + TCPCheckSumErrors);
1078 readw (ioaddr + UDPCheckSumErrors);
1079 readw (ioaddr + IPCheckSumErrors);
1080 return &np->stats;
1081 }
1082
1083 static int
1084 clear_stats (struct net_device *dev)
1085 {
1086 long ioaddr = dev->base_addr;
1087 #ifdef MEM_MAPPING
1088 int i;
1089 #endif
1090
1091 /* All statistics registers need to be acknowledged,
1092 else statistic overflow could cause problems */
1093 readl (ioaddr + FramesRcvOk);
1094 readl (ioaddr + FramesXmtOk);
1095 readl (ioaddr + OctetRcvOk);
1096 readl (ioaddr + OctetXmtOk);
1097
1098 readl (ioaddr + McstFramesRcvdOk);
1099 readl (ioaddr + SingleColFrames);
1100 readl (ioaddr + MultiColFrames);
1101 readl (ioaddr + LateCollisions);
1102 /* detailed rx errors */
1103 readw (ioaddr + FrameTooLongErrors);
1104 readw (ioaddr + InRangeLengthErrors);
1105 readw (ioaddr + FramesCheckSeqErrors);
1106 readw (ioaddr + FramesLostRxErrors);
1107
1108 /* detailed tx errors */
1109 readw (ioaddr + FramesAbortXSColls);
1110 readw (ioaddr + CarrierSenseErrors);
1111
1112 /* Clear all other statistic register. */
1113 readl (ioaddr + McstOctetXmtOk);
1114 readw (ioaddr + BcstFramesXmtdOk);
1115 readl (ioaddr + McstFramesXmtdOk);
1116 readw (ioaddr + BcstFramesRcvdOk);
1117 readw (ioaddr + MacControlFramesRcvd);
1118 readl (ioaddr + McstOctetXmtOk);
1119 readl (ioaddr + BcstOctetXmtOk);
1120 readl (ioaddr + McstFramesXmtdOk);
1121 readl (ioaddr + FramesWDeferredXmt);
1122 readw (ioaddr + BcstFramesXmtdOk);
1123 readw (ioaddr + MacControlFramesXmtd);
1124 readw (ioaddr + FramesWEXDeferal);
1125 #ifdef MEM_MAPPING
1126 for (i = 0x100; i <= 0x150; i += 4)
1127 readl (ioaddr + i);
1128 #endif
1129 readw (ioaddr + TxJumboFrames);
1130 readw (ioaddr + RxJumboFrames);
1131 readw (ioaddr + TCPCheckSumErrors);
1132 readw (ioaddr + UDPCheckSumErrors);
1133 readw (ioaddr + IPCheckSumErrors);
1134 return 0;
1135 }
1136
1137
1138 int
1139 change_mtu (struct net_device *dev, int new_mtu)
1140 {
1141 struct netdev_private *np = netdev_priv(dev);
1142 int max = (np->jumbo) ? MAX_JUMBO : 1536;
1143
1144 if ((new_mtu < 68) || (new_mtu > max)) {
1145 return -EINVAL;
1146 }
1147
1148 dev->mtu = new_mtu;
1149
1150 return 0;
1151 }
1152
1153 static void
1154 set_multicast (struct net_device *dev)
1155 {
1156 long ioaddr = dev->base_addr;
1157 u32 hash_table[2];
1158 u16 rx_mode = 0;
1159 struct netdev_private *np = netdev_priv(dev);
1160
1161 hash_table[0] = hash_table[1] = 0;
1162 /* RxFlowcontrol DA: 01-80-C2-00-00-01. Hash index=0x39 */
1163 hash_table[1] |= cpu_to_le32(0x02000000);
1164 if (dev->flags & IFF_PROMISC) {
1165 /* Receive all frames promiscuously. */
1166 rx_mode = ReceiveAllFrames;
1167 } else if ((dev->flags & IFF_ALLMULTI) ||
1168 (dev->mc_count > multicast_filter_limit)) {
1169 /* Receive broadcast and multicast frames */
1170 rx_mode = ReceiveBroadcast | ReceiveMulticast | ReceiveUnicast;
1171 } else if (dev->mc_count > 0) {
1172 int i;
1173 struct dev_mc_list *mclist;
1174 /* Receive broadcast frames and multicast frames filtering
1175 by Hashtable */
1176 rx_mode =
1177 ReceiveBroadcast | ReceiveMulticastHash | ReceiveUnicast;
1178 for (i=0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1179 i++, mclist=mclist->next)
1180 {
1181 int bit, index = 0;
1182 int crc = ether_crc_le (ETH_ALEN, mclist->dmi_addr);
1183 /* The inverted high significant 6 bits of CRC are
1184 used as an index to hashtable */
1185 for (bit = 0; bit < 6; bit++)
1186 if (crc & (1 << (31 - bit)))
1187 index |= (1 << bit);
1188 hash_table[index / 32] |= (1 << (index % 32));
1189 }
1190 } else {
1191 rx_mode = ReceiveBroadcast | ReceiveUnicast;
1192 }
1193 if (np->vlan) {
1194 /* ReceiveVLANMatch field in ReceiveMode */
1195 rx_mode |= ReceiveVLANMatch;
1196 }
1197
1198 writel (hash_table[0], ioaddr + HashTable0);
1199 writel (hash_table[1], ioaddr + HashTable1);
1200 writew (rx_mode, ioaddr + ReceiveMode);
1201 }
1202
1203 static void rio_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1204 {
1205 struct netdev_private *np = netdev_priv(dev);
1206 strcpy(info->driver, "dl2k");
1207 strcpy(info->version, DRV_VERSION);
1208 strcpy(info->bus_info, pci_name(np->pdev));
1209 }
1210
1211 static int rio_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1212 {
1213 struct netdev_private *np = netdev_priv(dev);
1214 if (np->phy_media) {
1215 /* fiber device */
1216 cmd->supported = SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1217 cmd->advertising= ADVERTISED_Autoneg | ADVERTISED_FIBRE;
1218 cmd->port = PORT_FIBRE;
1219 cmd->transceiver = XCVR_INTERNAL;
1220 } else {
1221 /* copper device */
1222 cmd->supported = SUPPORTED_10baseT_Half |
1223 SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Half
1224 | SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full |
1225 SUPPORTED_Autoneg | SUPPORTED_MII;
1226 cmd->advertising = ADVERTISED_10baseT_Half |
1227 ADVERTISED_10baseT_Full | ADVERTISED_100baseT_Half |
1228 ADVERTISED_100baseT_Full | ADVERTISED_1000baseT_Full|
1229 ADVERTISED_Autoneg | ADVERTISED_MII;
1230 cmd->port = PORT_MII;
1231 cmd->transceiver = XCVR_INTERNAL;
1232 }
1233 if ( np->link_status ) {
1234 cmd->speed = np->speed;
1235 cmd->duplex = np->full_duplex ? DUPLEX_FULL : DUPLEX_HALF;
1236 } else {
1237 cmd->speed = -1;
1238 cmd->duplex = -1;
1239 }
1240 if ( np->an_enable)
1241 cmd->autoneg = AUTONEG_ENABLE;
1242 else
1243 cmd->autoneg = AUTONEG_DISABLE;
1244
1245 cmd->phy_address = np->phy_addr;
1246 return 0;
1247 }
1248
1249 static int rio_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1250 {
1251 struct netdev_private *np = netdev_priv(dev);
1252 netif_carrier_off(dev);
1253 if (cmd->autoneg == AUTONEG_ENABLE) {
1254 if (np->an_enable)
1255 return 0;
1256 else {
1257 np->an_enable = 1;
1258 mii_set_media(dev);
1259 return 0;
1260 }
1261 } else {
1262 np->an_enable = 0;
1263 if (np->speed == 1000) {
1264 cmd->speed = SPEED_100;
1265 cmd->duplex = DUPLEX_FULL;
1266 printk("Warning!! Can't disable Auto negotiation in 1000Mbps, change to Manual 100Mbps, Full duplex.\n");
1267 }
1268 switch(cmd->speed + cmd->duplex) {
1269
1270 case SPEED_10 + DUPLEX_HALF:
1271 np->speed = 10;
1272 np->full_duplex = 0;
1273 break;
1274
1275 case SPEED_10 + DUPLEX_FULL:
1276 np->speed = 10;
1277 np->full_duplex = 1;
1278 break;
1279 case SPEED_100 + DUPLEX_HALF:
1280 np->speed = 100;
1281 np->full_duplex = 0;
1282 break;
1283 case SPEED_100 + DUPLEX_FULL:
1284 np->speed = 100;
1285 np->full_duplex = 1;
1286 break;
1287 case SPEED_1000 + DUPLEX_HALF:/* not supported */
1288 case SPEED_1000 + DUPLEX_FULL:/* not supported */
1289 default:
1290 return -EINVAL;
1291 }
1292 mii_set_media(dev);
1293 }
1294 return 0;
1295 }
1296
1297 static u32 rio_get_link(struct net_device *dev)
1298 {
1299 struct netdev_private *np = netdev_priv(dev);
1300 return np->link_status;
1301 }
1302
1303 static struct ethtool_ops ethtool_ops = {
1304 .get_drvinfo = rio_get_drvinfo,
1305 .get_settings = rio_get_settings,
1306 .set_settings = rio_set_settings,
1307 .get_link = rio_get_link,
1308 };
1309
1310 static int
1311 rio_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
1312 {
1313 int phy_addr;
1314 struct netdev_private *np = netdev_priv(dev);
1315 struct mii_data *miidata = (struct mii_data *) &rq->ifr_ifru;
1316
1317 struct netdev_desc *desc;
1318 int i;
1319
1320 phy_addr = np->phy_addr;
1321 switch (cmd) {
1322 case SIOCDEVPRIVATE:
1323 break;
1324
1325 case SIOCDEVPRIVATE + 1:
1326 miidata->out_value = mii_read (dev, phy_addr, miidata->reg_num);
1327 break;
1328 case SIOCDEVPRIVATE + 2:
1329 mii_write (dev, phy_addr, miidata->reg_num, miidata->in_value);
1330 break;
1331 case SIOCDEVPRIVATE + 3:
1332 break;
1333 case SIOCDEVPRIVATE + 4:
1334 break;
1335 case SIOCDEVPRIVATE + 5:
1336 netif_stop_queue (dev);
1337 break;
1338 case SIOCDEVPRIVATE + 6:
1339 netif_wake_queue (dev);
1340 break;
1341 case SIOCDEVPRIVATE + 7:
1342 printk
1343 ("tx_full=%x cur_tx=%lx old_tx=%lx cur_rx=%lx old_rx=%lx\n",
1344 netif_queue_stopped(dev), np->cur_tx, np->old_tx, np->cur_rx,
1345 np->old_rx);
1346 break;
1347 case SIOCDEVPRIVATE + 8:
1348 printk("TX ring:\n");
1349 for (i = 0; i < TX_RING_SIZE; i++) {
1350 desc = &np->tx_ring[i];
1351 printk
1352 ("%02x:cur:%08x next:%08x status:%08x frag1:%08x frag0:%08x",
1353 i,
1354 (u32) (np->tx_ring_dma + i * sizeof (*desc)),
1355 (u32) desc->next_desc,
1356 (u32) desc->status, (u32) (desc->fraginfo >> 32),
1357 (u32) desc->fraginfo);
1358 printk ("\n");
1359 }
1360 printk ("\n");
1361 break;
1362
1363 default:
1364 return -EOPNOTSUPP;
1365 }
1366 return 0;
1367 }
1368
1369 #define EEP_READ 0x0200
1370 #define EEP_BUSY 0x8000
1371 /* Read the EEPROM word */
1372 /* We use I/O instruction to read/write eeprom to avoid fail on some machines */
1373 int
1374 read_eeprom (long ioaddr, int eep_addr)
1375 {
1376 int i = 1000;
1377 outw (EEP_READ | (eep_addr & 0xff), ioaddr + EepromCtrl);
1378 while (i-- > 0) {
1379 if (!(inw (ioaddr + EepromCtrl) & EEP_BUSY)) {
1380 return inw (ioaddr + EepromData);
1381 }
1382 }
1383 return 0;
1384 }
1385
1386 enum phy_ctrl_bits {
1387 MII_READ = 0x00, MII_CLK = 0x01, MII_DATA1 = 0x02, MII_WRITE = 0x04,
1388 MII_DUPLEX = 0x08,
1389 };
1390
1391 #define mii_delay() readb(ioaddr)
1392 static void
1393 mii_sendbit (struct net_device *dev, u32 data)
1394 {
1395 long ioaddr = dev->base_addr + PhyCtrl;
1396 data = (data) ? MII_DATA1 : 0;
1397 data |= MII_WRITE;
1398 data |= (readb (ioaddr) & 0xf8) | MII_WRITE;
1399 writeb (data, ioaddr);
1400 mii_delay ();
1401 writeb (data | MII_CLK, ioaddr);
1402 mii_delay ();
1403 }
1404
1405 static int
1406 mii_getbit (struct net_device *dev)
1407 {
1408 long ioaddr = dev->base_addr + PhyCtrl;
1409 u8 data;
1410
1411 data = (readb (ioaddr) & 0xf8) | MII_READ;
1412 writeb (data, ioaddr);
1413 mii_delay ();
1414 writeb (data | MII_CLK, ioaddr);
1415 mii_delay ();
1416 return ((readb (ioaddr) >> 1) & 1);
1417 }
1418
1419 static void
1420 mii_send_bits (struct net_device *dev, u32 data, int len)
1421 {
1422 int i;
1423 for (i = len - 1; i >= 0; i--) {
1424 mii_sendbit (dev, data & (1 << i));
1425 }
1426 }
1427
1428 static int
1429 mii_read (struct net_device *dev, int phy_addr, int reg_num)
1430 {
1431 u32 cmd;
1432 int i;
1433 u32 retval = 0;
1434
1435 /* Preamble */
1436 mii_send_bits (dev, 0xffffffff, 32);
1437 /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
1438 /* ST,OP = 0110'b for read operation */
1439 cmd = (0x06 << 10 | phy_addr << 5 | reg_num);
1440 mii_send_bits (dev, cmd, 14);
1441 /* Turnaround */
1442 if (mii_getbit (dev))
1443 goto err_out;
1444 /* Read data */
1445 for (i = 0; i < 16; i++) {
1446 retval |= mii_getbit (dev);
1447 retval <<= 1;
1448 }
1449 /* End cycle */
1450 mii_getbit (dev);
1451 return (retval >> 1) & 0xffff;
1452
1453 err_out:
1454 return 0;
1455 }
1456 static int
1457 mii_write (struct net_device *dev, int phy_addr, int reg_num, u16 data)
1458 {
1459 u32 cmd;
1460
1461 /* Preamble */
1462 mii_send_bits (dev, 0xffffffff, 32);
1463 /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
1464 /* ST,OP,AAAAA,RRRRR,TA = 0101xxxxxxxxxx10'b = 0x5002 for write */
1465 cmd = (0x5002 << 16) | (phy_addr << 23) | (reg_num << 18) | data;
1466 mii_send_bits (dev, cmd, 32);
1467 /* End cycle */
1468 mii_getbit (dev);
1469 return 0;
1470 }
1471 static int
1472 mii_wait_link (struct net_device *dev, int wait)
1473 {
1474 BMSR_t bmsr;
1475 int phy_addr;
1476 struct netdev_private *np;
1477
1478 np = netdev_priv(dev);
1479 phy_addr = np->phy_addr;
1480
1481 do {
1482 bmsr.image = mii_read (dev, phy_addr, MII_BMSR);
1483 if (bmsr.bits.link_status)
1484 return 0;
1485 mdelay (1);
1486 } while (--wait > 0);
1487 return -1;
1488 }
1489 static int
1490 mii_get_media (struct net_device *dev)
1491 {
1492 ANAR_t negotiate;
1493 BMSR_t bmsr;
1494 BMCR_t bmcr;
1495 MSCR_t mscr;
1496 MSSR_t mssr;
1497 int phy_addr;
1498 struct netdev_private *np;
1499
1500 np = netdev_priv(dev);
1501 phy_addr = np->phy_addr;
1502
1503 bmsr.image = mii_read (dev, phy_addr, MII_BMSR);
1504 if (np->an_enable) {
1505 if (!bmsr.bits.an_complete) {
1506 /* Auto-Negotiation not completed */
1507 return -1;
1508 }
1509 negotiate.image = mii_read (dev, phy_addr, MII_ANAR) &
1510 mii_read (dev, phy_addr, MII_ANLPAR);
1511 mscr.image = mii_read (dev, phy_addr, MII_MSCR);
1512 mssr.image = mii_read (dev, phy_addr, MII_MSSR);
1513 if (mscr.bits.media_1000BT_FD & mssr.bits.lp_1000BT_FD) {
1514 np->speed = 1000;
1515 np->full_duplex = 1;
1516 printk (KERN_INFO "Auto 1000 Mbps, Full duplex\n");
1517 } else if (mscr.bits.media_1000BT_HD & mssr.bits.lp_1000BT_HD) {
1518 np->speed = 1000;
1519 np->full_duplex = 0;
1520 printk (KERN_INFO "Auto 1000 Mbps, Half duplex\n");
1521 } else if (negotiate.bits.media_100BX_FD) {
1522 np->speed = 100;
1523 np->full_duplex = 1;
1524 printk (KERN_INFO "Auto 100 Mbps, Full duplex\n");
1525 } else if (negotiate.bits.media_100BX_HD) {
1526 np->speed = 100;
1527 np->full_duplex = 0;
1528 printk (KERN_INFO "Auto 100 Mbps, Half duplex\n");
1529 } else if (negotiate.bits.media_10BT_FD) {
1530 np->speed = 10;
1531 np->full_duplex = 1;
1532 printk (KERN_INFO "Auto 10 Mbps, Full duplex\n");
1533 } else if (negotiate.bits.media_10BT_HD) {
1534 np->speed = 10;
1535 np->full_duplex = 0;
1536 printk (KERN_INFO "Auto 10 Mbps, Half duplex\n");
1537 }
1538 if (negotiate.bits.pause) {
1539 np->tx_flow &= 1;
1540 np->rx_flow &= 1;
1541 } else if (negotiate.bits.asymmetric) {
1542 np->tx_flow = 0;
1543 np->rx_flow &= 1;
1544 }
1545 /* else tx_flow, rx_flow = user select */
1546 } else {
1547 bmcr.image = mii_read (dev, phy_addr, MII_BMCR);
1548 if (bmcr.bits.speed100 == 1 && bmcr.bits.speed1000 == 0) {
1549 printk (KERN_INFO "Operating at 100 Mbps, ");
1550 } else if (bmcr.bits.speed100 == 0 && bmcr.bits.speed1000 == 0) {
1551 printk (KERN_INFO "Operating at 10 Mbps, ");
1552 } else if (bmcr.bits.speed100 == 0 && bmcr.bits.speed1000 == 1) {
1553 printk (KERN_INFO "Operating at 1000 Mbps, ");
1554 }
1555 if (bmcr.bits.duplex_mode) {
1556 printk ("Full duplex\n");
1557 } else {
1558 printk ("Half duplex\n");
1559 }
1560 }
1561 if (np->tx_flow)
1562 printk(KERN_INFO "Enable Tx Flow Control\n");
1563 else
1564 printk(KERN_INFO "Disable Tx Flow Control\n");
1565 if (np->rx_flow)
1566 printk(KERN_INFO "Enable Rx Flow Control\n");
1567 else
1568 printk(KERN_INFO "Disable Rx Flow Control\n");
1569
1570 return 0;
1571 }
1572
1573 static int
1574 mii_set_media (struct net_device *dev)
1575 {
1576 PHY_SCR_t pscr;
1577 BMCR_t bmcr;
1578 BMSR_t bmsr;
1579 ANAR_t anar;
1580 int phy_addr;
1581 struct netdev_private *np;
1582 np = netdev_priv(dev);
1583 phy_addr = np->phy_addr;
1584
1585 /* Does user set speed? */
1586 if (np->an_enable) {
1587 /* Advertise capabilities */
1588 bmsr.image = mii_read (dev, phy_addr, MII_BMSR);
1589 anar.image = mii_read (dev, phy_addr, MII_ANAR);
1590 anar.bits.media_100BX_FD = bmsr.bits.media_100BX_FD;
1591 anar.bits.media_100BX_HD = bmsr.bits.media_100BX_HD;
1592 anar.bits.media_100BT4 = bmsr.bits.media_100BT4;
1593 anar.bits.media_10BT_FD = bmsr.bits.media_10BT_FD;
1594 anar.bits.media_10BT_HD = bmsr.bits.media_10BT_HD;
1595 anar.bits.pause = 1;
1596 anar.bits.asymmetric = 1;
1597 mii_write (dev, phy_addr, MII_ANAR, anar.image);
1598
1599 /* Enable Auto crossover */
1600 pscr.image = mii_read (dev, phy_addr, MII_PHY_SCR);
1601 pscr.bits.mdi_crossover_mode = 3; /* 11'b */
1602 mii_write (dev, phy_addr, MII_PHY_SCR, pscr.image);
1603
1604 /* Soft reset PHY */
1605 mii_write (dev, phy_addr, MII_BMCR, MII_BMCR_RESET);
1606 bmcr.image = 0;
1607 bmcr.bits.an_enable = 1;
1608 bmcr.bits.restart_an = 1;
1609 bmcr.bits.reset = 1;
1610 mii_write (dev, phy_addr, MII_BMCR, bmcr.image);
1611 mdelay(1);
1612 } else {
1613 /* Force speed setting */
1614 /* 1) Disable Auto crossover */
1615 pscr.image = mii_read (dev, phy_addr, MII_PHY_SCR);
1616 pscr.bits.mdi_crossover_mode = 0;
1617 mii_write (dev, phy_addr, MII_PHY_SCR, pscr.image);
1618
1619 /* 2) PHY Reset */
1620 bmcr.image = mii_read (dev, phy_addr, MII_BMCR);
1621 bmcr.bits.reset = 1;
1622 mii_write (dev, phy_addr, MII_BMCR, bmcr.image);
1623
1624 /* 3) Power Down */
1625 bmcr.image = 0x1940; /* must be 0x1940 */
1626 mii_write (dev, phy_addr, MII_BMCR, bmcr.image);
1627 mdelay (100); /* wait a certain time */
1628
1629 /* 4) Advertise nothing */
1630 mii_write (dev, phy_addr, MII_ANAR, 0);
1631
1632 /* 5) Set media and Power Up */
1633 bmcr.image = 0;
1634 bmcr.bits.power_down = 1;
1635 if (np->speed == 100) {
1636 bmcr.bits.speed100 = 1;
1637 bmcr.bits.speed1000 = 0;
1638 printk (KERN_INFO "Manual 100 Mbps, ");
1639 } else if (np->speed == 10) {
1640 bmcr.bits.speed100 = 0;
1641 bmcr.bits.speed1000 = 0;
1642 printk (KERN_INFO "Manual 10 Mbps, ");
1643 }
1644 if (np->full_duplex) {
1645 bmcr.bits.duplex_mode = 1;
1646 printk ("Full duplex\n");
1647 } else {
1648 bmcr.bits.duplex_mode = 0;
1649 printk ("Half duplex\n");
1650 }
1651 #if 0
1652 /* Set 1000BaseT Master/Slave setting */
1653 mscr.image = mii_read (dev, phy_addr, MII_MSCR);
1654 mscr.bits.cfg_enable = 1;
1655 mscr.bits.cfg_value = 0;
1656 #endif
1657 mii_write (dev, phy_addr, MII_BMCR, bmcr.image);
1658 mdelay(10);
1659 }
1660 return 0;
1661 }
1662
1663 static int
1664 mii_get_media_pcs (struct net_device *dev)
1665 {
1666 ANAR_PCS_t negotiate;
1667 BMSR_t bmsr;
1668 BMCR_t bmcr;
1669 int phy_addr;
1670 struct netdev_private *np;
1671
1672 np = netdev_priv(dev);
1673 phy_addr = np->phy_addr;
1674
1675 bmsr.image = mii_read (dev, phy_addr, PCS_BMSR);
1676 if (np->an_enable) {
1677 if (!bmsr.bits.an_complete) {
1678 /* Auto-Negotiation not completed */
1679 return -1;
1680 }
1681 negotiate.image = mii_read (dev, phy_addr, PCS_ANAR) &
1682 mii_read (dev, phy_addr, PCS_ANLPAR);
1683 np->speed = 1000;
1684 if (negotiate.bits.full_duplex) {
1685 printk (KERN_INFO "Auto 1000 Mbps, Full duplex\n");
1686 np->full_duplex = 1;
1687 } else {
1688 printk (KERN_INFO "Auto 1000 Mbps, half duplex\n");
1689 np->full_duplex = 0;
1690 }
1691 if (negotiate.bits.pause) {
1692 np->tx_flow &= 1;
1693 np->rx_flow &= 1;
1694 } else if (negotiate.bits.asymmetric) {
1695 np->tx_flow = 0;
1696 np->rx_flow &= 1;
1697 }
1698 /* else tx_flow, rx_flow = user select */
1699 } else {
1700 bmcr.image = mii_read (dev, phy_addr, PCS_BMCR);
1701 printk (KERN_INFO "Operating at 1000 Mbps, ");
1702 if (bmcr.bits.duplex_mode) {
1703 printk ("Full duplex\n");
1704 } else {
1705 printk ("Half duplex\n");
1706 }
1707 }
1708 if (np->tx_flow)
1709 printk(KERN_INFO "Enable Tx Flow Control\n");
1710 else
1711 printk(KERN_INFO "Disable Tx Flow Control\n");
1712 if (np->rx_flow)
1713 printk(KERN_INFO "Enable Rx Flow Control\n");
1714 else
1715 printk(KERN_INFO "Disable Rx Flow Control\n");
1716
1717 return 0;
1718 }
1719
1720 static int
1721 mii_set_media_pcs (struct net_device *dev)
1722 {
1723 BMCR_t bmcr;
1724 ESR_t esr;
1725 ANAR_PCS_t anar;
1726 int phy_addr;
1727 struct netdev_private *np;
1728 np = netdev_priv(dev);
1729 phy_addr = np->phy_addr;
1730
1731 /* Auto-Negotiation? */
1732 if (np->an_enable) {
1733 /* Advertise capabilities */
1734 esr.image = mii_read (dev, phy_addr, PCS_ESR);
1735 anar.image = mii_read (dev, phy_addr, MII_ANAR);
1736 anar.bits.half_duplex =
1737 esr.bits.media_1000BT_HD | esr.bits.media_1000BX_HD;
1738 anar.bits.full_duplex =
1739 esr.bits.media_1000BT_FD | esr.bits.media_1000BX_FD;
1740 anar.bits.pause = 1;
1741 anar.bits.asymmetric = 1;
1742 mii_write (dev, phy_addr, MII_ANAR, anar.image);
1743
1744 /* Soft reset PHY */
1745 mii_write (dev, phy_addr, MII_BMCR, MII_BMCR_RESET);
1746 bmcr.image = 0;
1747 bmcr.bits.an_enable = 1;
1748 bmcr.bits.restart_an = 1;
1749 bmcr.bits.reset = 1;
1750 mii_write (dev, phy_addr, MII_BMCR, bmcr.image);
1751 mdelay(1);
1752 } else {
1753 /* Force speed setting */
1754 /* PHY Reset */
1755 bmcr.image = 0;
1756 bmcr.bits.reset = 1;
1757 mii_write (dev, phy_addr, MII_BMCR, bmcr.image);
1758 mdelay(10);
1759 bmcr.image = 0;
1760 bmcr.bits.an_enable = 0;
1761 if (np->full_duplex) {
1762 bmcr.bits.duplex_mode = 1;
1763 printk (KERN_INFO "Manual full duplex\n");
1764 } else {
1765 bmcr.bits.duplex_mode = 0;
1766 printk (KERN_INFO "Manual half duplex\n");
1767 }
1768 mii_write (dev, phy_addr, MII_BMCR, bmcr.image);
1769 mdelay(10);
1770
1771 /* Advertise nothing */
1772 mii_write (dev, phy_addr, MII_ANAR, 0);
1773 }
1774 return 0;
1775 }
1776
1777
1778 static int
1779 rio_close (struct net_device *dev)
1780 {
1781 long ioaddr = dev->base_addr;
1782 struct netdev_private *np = netdev_priv(dev);
1783 struct sk_buff *skb;
1784 int i;
1785
1786 netif_stop_queue (dev);
1787
1788 /* Disable interrupts */
1789 writew (0, ioaddr + IntEnable);
1790
1791 /* Stop Tx and Rx logics */
1792 writel (TxDisable | RxDisable | StatsDisable, ioaddr + MACCtrl);
1793 synchronize_irq (dev->irq);
1794 free_irq (dev->irq, dev);
1795 del_timer_sync (&np->timer);
1796
1797 /* Free all the skbuffs in the queue. */
1798 for (i = 0; i < RX_RING_SIZE; i++) {
1799 np->rx_ring[i].status = 0;
1800 np->rx_ring[i].fraginfo = 0;
1801 skb = np->rx_skbuff[i];
1802 if (skb) {
1803 pci_unmap_single(np->pdev,
1804 np->rx_ring[i].fraginfo & DMA_48BIT_MASK,
1805 skb->len, PCI_DMA_FROMDEVICE);
1806 dev_kfree_skb (skb);
1807 np->rx_skbuff[i] = NULL;
1808 }
1809 }
1810 for (i = 0; i < TX_RING_SIZE; i++) {
1811 skb = np->tx_skbuff[i];
1812 if (skb) {
1813 pci_unmap_single(np->pdev,
1814 np->tx_ring[i].fraginfo & DMA_48BIT_MASK,
1815 skb->len, PCI_DMA_TODEVICE);
1816 dev_kfree_skb (skb);
1817 np->tx_skbuff[i] = NULL;
1818 }
1819 }
1820
1821 return 0;
1822 }
1823
1824 static void __devexit
1825 rio_remove1 (struct pci_dev *pdev)
1826 {
1827 struct net_device *dev = pci_get_drvdata (pdev);
1828
1829 if (dev) {
1830 struct netdev_private *np = netdev_priv(dev);
1831
1832 unregister_netdev (dev);
1833 pci_free_consistent (pdev, RX_TOTAL_SIZE, np->rx_ring,
1834 np->rx_ring_dma);
1835 pci_free_consistent (pdev, TX_TOTAL_SIZE, np->tx_ring,
1836 np->tx_ring_dma);
1837 #ifdef MEM_MAPPING
1838 iounmap ((char *) (dev->base_addr));
1839 #endif
1840 free_netdev (dev);
1841 pci_release_regions (pdev);
1842 pci_disable_device (pdev);
1843 }
1844 pci_set_drvdata (pdev, NULL);
1845 }
1846
1847 static struct pci_driver rio_driver = {
1848 .name = "dl2k",
1849 .id_table = rio_pci_tbl,
1850 .probe = rio_probe1,
1851 .remove = __devexit_p(rio_remove1),
1852 };
1853
1854 static int __init
1855 rio_init (void)
1856 {
1857 return pci_module_init (&rio_driver);
1858 }
1859
1860 static void __exit
1861 rio_exit (void)
1862 {
1863 pci_unregister_driver (&rio_driver);
1864 }
1865
1866 module_init (rio_init);
1867 module_exit (rio_exit);
1868
1869 /*
1870
1871 Compile command:
1872
1873 gcc -D__KERNEL__ -DMODULE -I/usr/src/linux/include -Wall -Wstrict-prototypes -O2 -c dl2k.c
1874
1875 Read Documentation/networking/dl2k.txt for details.
1876
1877 */
1878
USB Experimental Work