2 * linux/arch/arm/plat-omap/dma.c
4 * Copyright (C) 2003 Nokia Corporation
5 * Author: Juha Yrjölä <juha.yrjola@nokia.com>
6 * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
7 * Graphics DMA and LCD DMA graphics tranformations
8 * by Imre Deak <imre.deak@nokia.com>
9 * OMAP2 support Copyright (C) 2004-2005 Texas Instruments, Inc.
10 * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com>
11 * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
13 * Support functions for the OMAP internal DMA channels.
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
21 #include <linux/module.h>
22 #include <linux/init.h>
23 #include <linux/sched.h>
24 #include <linux/spinlock.h>
25 #include <linux/errno.h>
26 #include <linux/interrupt.h>
27 #include <linux/irq.h>
29 #include <asm/system.h>
30 #include <asm/hardware.h>
34 #include <asm/arch/tc.h>
39 #define debug_printk(x) printk x
41 #define debug_printk(x)
44 #define OMAP_DMA_ACTIVE 0x01
45 #define OMAP_DMA_CCR_EN (1 << 7)
46 #define OMAP2_DMA_CSR_CLEAR_MASK 0xffe
48 #define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec)
50 static int enable_1510_mode
= 0;
58 void (* callback
)(int lch
, u16 ch_status
, void *data
);
63 static int dma_chan_count
;
65 static spinlock_t dma_chan_lock
;
66 static struct omap_dma_lch dma_chan
[OMAP_LOGICAL_DMA_CH_COUNT
];
68 static const u8 omap1_dma_irq
[OMAP_LOGICAL_DMA_CH_COUNT
] = {
69 INT_DMA_CH0_6
, INT_DMA_CH1_7
, INT_DMA_CH2_8
, INT_DMA_CH3
,
70 INT_DMA_CH4
, INT_DMA_CH5
, INT_1610_DMA_CH6
, INT_1610_DMA_CH7
,
71 INT_1610_DMA_CH8
, INT_1610_DMA_CH9
, INT_1610_DMA_CH10
,
72 INT_1610_DMA_CH11
, INT_1610_DMA_CH12
, INT_1610_DMA_CH13
,
73 INT_1610_DMA_CH14
, INT_1610_DMA_CH15
, INT_DMA_LCD
76 #define REVISIT_24XX() printk(KERN_ERR "FIXME: no %s on 24xx\n", \
79 #ifdef CONFIG_ARCH_OMAP15XX
80 /* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
81 int omap_dma_in_1510_mode(void)
83 return enable_1510_mode
;
86 #define omap_dma_in_1510_mode() 0
89 #ifdef CONFIG_ARCH_OMAP1
90 static inline int get_gdma_dev(int req
)
92 u32 reg
= OMAP_FUNC_MUX_ARM_BASE
+ ((req
- 1) / 5) * 4;
93 int shift
= ((req
- 1) % 5) * 6;
95 return ((omap_readl(reg
) >> shift
) & 0x3f) + 1;
98 static inline void set_gdma_dev(int req
, int dev
)
100 u32 reg
= OMAP_FUNC_MUX_ARM_BASE
+ ((req
- 1) / 5) * 4;
101 int shift
= ((req
- 1) % 5) * 6;
105 l
&= ~(0x3f << shift
);
106 l
|= (dev
- 1) << shift
;
110 #define set_gdma_dev(req, dev) do {} while (0)
113 static void clear_lch_regs(int lch
)
116 u32 lch_base
= OMAP_DMA_BASE
+ lch
* 0x40;
118 for (i
= 0; i
< 0x2c; i
+= 2)
119 omap_writew(0, lch_base
+ i
);
122 void omap_set_dma_priority(int dst_port
, int priority
)
128 case OMAP_DMA_PORT_OCP_T1
: /* FFFECC00 */
129 reg
= OMAP_TC_OCPT1_PRIOR
;
131 case OMAP_DMA_PORT_OCP_T2
: /* FFFECCD0 */
132 reg
= OMAP_TC_OCPT2_PRIOR
;
134 case OMAP_DMA_PORT_EMIFF
: /* FFFECC08 */
135 reg
= OMAP_TC_EMIFF_PRIOR
;
137 case OMAP_DMA_PORT_EMIFS
: /* FFFECC04 */
138 reg
= OMAP_TC_EMIFS_PRIOR
;
146 l
|= (priority
& 0xf) << 8;
150 void omap_set_dma_transfer_params(int lch
, int data_type
, int elem_count
,
151 int frame_count
, int sync_mode
,
152 int dma_trigger
, int src_or_dst_synch
)
154 OMAP_DMA_CSDP_REG(lch
) &= ~0x03;
155 OMAP_DMA_CSDP_REG(lch
) |= data_type
;
157 if (cpu_class_is_omap1()) {
158 OMAP_DMA_CCR_REG(lch
) &= ~(1 << 5);
159 if (sync_mode
== OMAP_DMA_SYNC_FRAME
)
160 OMAP_DMA_CCR_REG(lch
) |= 1 << 5;
162 OMAP1_DMA_CCR2_REG(lch
) &= ~(1 << 2);
163 if (sync_mode
== OMAP_DMA_SYNC_BLOCK
)
164 OMAP1_DMA_CCR2_REG(lch
) |= 1 << 2;
167 if (cpu_is_omap24xx() && dma_trigger
) {
168 u32 val
= OMAP_DMA_CCR_REG(lch
);
171 if (dma_trigger
> 63)
173 if (dma_trigger
> 31)
177 val
|= (dma_trigger
& 0x1f);
179 if (sync_mode
& OMAP_DMA_SYNC_FRAME
)
184 if (sync_mode
& OMAP_DMA_SYNC_BLOCK
)
189 if (src_or_dst_synch
)
190 val
|= 1 << 24; /* source synch */
192 val
&= ~(1 << 24); /* dest synch */
194 OMAP_DMA_CCR_REG(lch
) = val
;
197 OMAP_DMA_CEN_REG(lch
) = elem_count
;
198 OMAP_DMA_CFN_REG(lch
) = frame_count
;
201 void omap_set_dma_color_mode(int lch
, enum omap_dma_color_mode mode
, u32 color
)
205 BUG_ON(omap_dma_in_1510_mode());
207 if (cpu_is_omap24xx()) {
212 w
= OMAP1_DMA_CCR2_REG(lch
) & ~0x03;
214 case OMAP_DMA_CONSTANT_FILL
:
217 case OMAP_DMA_TRANSPARENT_COPY
:
220 case OMAP_DMA_COLOR_DIS
:
225 OMAP1_DMA_CCR2_REG(lch
) = w
;
227 w
= OMAP1_DMA_LCH_CTRL_REG(lch
) & ~0x0f;
228 /* Default is channel type 2D */
230 OMAP1_DMA_COLOR_L_REG(lch
) = (u16
)color
;
231 OMAP1_DMA_COLOR_U_REG(lch
) = (u16
)(color
>> 16);
232 w
|= 1; /* Channel type G */
234 OMAP1_DMA_LCH_CTRL_REG(lch
) = w
;
237 /* Note that src_port is only for omap1 */
238 void omap_set_dma_src_params(int lch
, int src_port
, int src_amode
,
239 unsigned long src_start
,
240 int src_ei
, int src_fi
)
242 if (cpu_class_is_omap1()) {
243 OMAP_DMA_CSDP_REG(lch
) &= ~(0x1f << 2);
244 OMAP_DMA_CSDP_REG(lch
) |= src_port
<< 2;
247 OMAP_DMA_CCR_REG(lch
) &= ~(0x03 << 12);
248 OMAP_DMA_CCR_REG(lch
) |= src_amode
<< 12;
250 if (cpu_class_is_omap1()) {
251 OMAP1_DMA_CSSA_U_REG(lch
) = src_start
>> 16;
252 OMAP1_DMA_CSSA_L_REG(lch
) = src_start
;
255 if (cpu_is_omap24xx())
256 OMAP2_DMA_CSSA_REG(lch
) = src_start
;
258 OMAP_DMA_CSEI_REG(lch
) = src_ei
;
259 OMAP_DMA_CSFI_REG(lch
) = src_fi
;
262 void omap_set_dma_params(int lch
, struct omap_dma_channel_params
* params
)
264 omap_set_dma_transfer_params(lch
, params
->data_type
,
265 params
->elem_count
, params
->frame_count
,
266 params
->sync_mode
, params
->trigger
,
267 params
->src_or_dst_synch
);
268 omap_set_dma_src_params(lch
, params
->src_port
,
269 params
->src_amode
, params
->src_start
,
270 params
->src_ei
, params
->src_fi
);
272 omap_set_dma_dest_params(lch
, params
->dst_port
,
273 params
->dst_amode
, params
->dst_start
,
274 params
->dst_ei
, params
->dst_fi
);
277 void omap_set_dma_src_index(int lch
, int eidx
, int fidx
)
279 if (cpu_is_omap24xx()) {
283 OMAP_DMA_CSEI_REG(lch
) = eidx
;
284 OMAP_DMA_CSFI_REG(lch
) = fidx
;
287 void omap_set_dma_src_data_pack(int lch
, int enable
)
289 OMAP_DMA_CSDP_REG(lch
) &= ~(1 << 6);
291 OMAP_DMA_CSDP_REG(lch
) |= (1 << 6);
294 void omap_set_dma_src_burst_mode(int lch
, enum omap_dma_burst_mode burst_mode
)
296 unsigned int burst
= 0;
297 OMAP_DMA_CSDP_REG(lch
) &= ~(0x03 << 7);
299 switch (burst_mode
) {
300 case OMAP_DMA_DATA_BURST_DIS
:
302 case OMAP_DMA_DATA_BURST_4
:
303 if (cpu_is_omap24xx())
308 case OMAP_DMA_DATA_BURST_8
:
309 if (cpu_is_omap24xx()) {
313 /* not supported by current hardware on OMAP1
317 case OMAP_DMA_DATA_BURST_16
:
318 if (cpu_is_omap24xx()) {
322 /* OMAP1 don't support burst 16
328 OMAP_DMA_CSDP_REG(lch
) |= (burst
<< 7);
331 /* Note that dest_port is only for OMAP1 */
332 void omap_set_dma_dest_params(int lch
, int dest_port
, int dest_amode
,
333 unsigned long dest_start
,
334 int dst_ei
, int dst_fi
)
336 if (cpu_class_is_omap1()) {
337 OMAP_DMA_CSDP_REG(lch
) &= ~(0x1f << 9);
338 OMAP_DMA_CSDP_REG(lch
) |= dest_port
<< 9;
341 OMAP_DMA_CCR_REG(lch
) &= ~(0x03 << 14);
342 OMAP_DMA_CCR_REG(lch
) |= dest_amode
<< 14;
344 if (cpu_class_is_omap1()) {
345 OMAP1_DMA_CDSA_U_REG(lch
) = dest_start
>> 16;
346 OMAP1_DMA_CDSA_L_REG(lch
) = dest_start
;
349 if (cpu_is_omap24xx())
350 OMAP2_DMA_CDSA_REG(lch
) = dest_start
;
352 OMAP_DMA_CDEI_REG(lch
) = dst_ei
;
353 OMAP_DMA_CDFI_REG(lch
) = dst_fi
;
356 void omap_set_dma_dest_index(int lch
, int eidx
, int fidx
)
358 if (cpu_is_omap24xx()) {
362 OMAP_DMA_CDEI_REG(lch
) = eidx
;
363 OMAP_DMA_CDFI_REG(lch
) = fidx
;
366 void omap_set_dma_dest_data_pack(int lch
, int enable
)
368 OMAP_DMA_CSDP_REG(lch
) &= ~(1 << 13);
370 OMAP_DMA_CSDP_REG(lch
) |= 1 << 13;
373 void omap_set_dma_dest_burst_mode(int lch
, enum omap_dma_burst_mode burst_mode
)
375 unsigned int burst
= 0;
376 OMAP_DMA_CSDP_REG(lch
) &= ~(0x03 << 14);
378 switch (burst_mode
) {
379 case OMAP_DMA_DATA_BURST_DIS
:
381 case OMAP_DMA_DATA_BURST_4
:
382 if (cpu_is_omap24xx())
387 case OMAP_DMA_DATA_BURST_8
:
388 if (cpu_is_omap24xx())
393 case OMAP_DMA_DATA_BURST_16
:
394 if (cpu_is_omap24xx()) {
398 /* OMAP1 don't support burst 16
402 printk(KERN_ERR
"Invalid DMA burst mode\n");
406 OMAP_DMA_CSDP_REG(lch
) |= (burst
<< 14);
409 static inline void omap_enable_channel_irq(int lch
)
414 if (cpu_class_is_omap1())
415 status
= OMAP_DMA_CSR_REG(lch
);
416 else if (cpu_is_omap24xx())
417 OMAP_DMA_CSR_REG(lch
) = OMAP2_DMA_CSR_CLEAR_MASK
;
419 /* Enable some nice interrupts. */
420 OMAP_DMA_CICR_REG(lch
) = dma_chan
[lch
].enabled_irqs
;
422 dma_chan
[lch
].flags
|= OMAP_DMA_ACTIVE
;
425 static void omap_disable_channel_irq(int lch
)
427 if (cpu_is_omap24xx())
428 OMAP_DMA_CICR_REG(lch
) = 0;
431 void omap_enable_dma_irq(int lch
, u16 bits
)
433 dma_chan
[lch
].enabled_irqs
|= bits
;
436 void omap_disable_dma_irq(int lch
, u16 bits
)
438 dma_chan
[lch
].enabled_irqs
&= ~bits
;
441 static inline void enable_lnk(int lch
)
443 if (cpu_class_is_omap1())
444 OMAP_DMA_CLNK_CTRL_REG(lch
) &= ~(1 << 14);
446 /* Set the ENABLE_LNK bits */
447 if (dma_chan
[lch
].next_lch
!= -1)
448 OMAP_DMA_CLNK_CTRL_REG(lch
) =
449 dma_chan
[lch
].next_lch
| (1 << 15);
452 static inline void disable_lnk(int lch
)
454 /* Disable interrupts */
455 if (cpu_class_is_omap1()) {
456 OMAP_DMA_CICR_REG(lch
) = 0;
457 /* Set the STOP_LNK bit */
458 OMAP_DMA_CLNK_CTRL_REG(lch
) |= 1 << 14;
461 if (cpu_is_omap24xx()) {
462 omap_disable_channel_irq(lch
);
463 /* Clear the ENABLE_LNK bit */
464 OMAP_DMA_CLNK_CTRL_REG(lch
) &= ~(1 << 15);
467 dma_chan
[lch
].flags
&= ~OMAP_DMA_ACTIVE
;
470 static inline void omap2_enable_irq_lch(int lch
)
474 if (!cpu_is_omap24xx())
477 val
= omap_readl(OMAP_DMA4_IRQENABLE_L0
);
479 omap_writel(val
, OMAP_DMA4_IRQENABLE_L0
);
482 int omap_request_dma(int dev_id
, const char *dev_name
,
483 void (* callback
)(int lch
, u16 ch_status
, void *data
),
484 void *data
, int *dma_ch_out
)
486 int ch
, free_ch
= -1;
488 struct omap_dma_lch
*chan
;
490 spin_lock_irqsave(&dma_chan_lock
, flags
);
491 for (ch
= 0; ch
< dma_chan_count
; ch
++) {
492 if (free_ch
== -1 && dma_chan
[ch
].dev_id
== -1) {
499 spin_unlock_irqrestore(&dma_chan_lock
, flags
);
502 chan
= dma_chan
+ free_ch
;
503 chan
->dev_id
= dev_id
;
505 if (cpu_class_is_omap1())
506 clear_lch_regs(free_ch
);
508 if (cpu_is_omap24xx())
509 omap_clear_dma(free_ch
);
511 spin_unlock_irqrestore(&dma_chan_lock
, flags
);
513 chan
->dev_name
= dev_name
;
514 chan
->callback
= callback
;
516 chan
->enabled_irqs
= OMAP_DMA_DROP_IRQ
| OMAP_DMA_BLOCK_IRQ
;
518 if (cpu_class_is_omap1())
519 chan
->enabled_irqs
|= OMAP1_DMA_TOUT_IRQ
;
520 else if (cpu_is_omap24xx())
521 chan
->enabled_irqs
|= OMAP2_DMA_MISALIGNED_ERR_IRQ
|
522 OMAP2_DMA_TRANS_ERR_IRQ
;
524 if (cpu_is_omap16xx()) {
525 /* If the sync device is set, configure it dynamically. */
527 set_gdma_dev(free_ch
+ 1, dev_id
);
528 dev_id
= free_ch
+ 1;
530 /* Disable the 1510 compatibility mode and set the sync device
532 OMAP_DMA_CCR_REG(free_ch
) = dev_id
| (1 << 10);
533 } else if (cpu_is_omap730() || cpu_is_omap15xx()) {
534 OMAP_DMA_CCR_REG(free_ch
) = dev_id
;
537 if (cpu_is_omap24xx()) {
538 omap2_enable_irq_lch(free_ch
);
540 omap_enable_channel_irq(free_ch
);
541 /* Clear the CSR register and IRQ status register */
542 OMAP_DMA_CSR_REG(free_ch
) = OMAP2_DMA_CSR_CLEAR_MASK
;
543 omap_writel(~0x0, OMAP_DMA4_IRQSTATUS_L0
);
546 *dma_ch_out
= free_ch
;
551 void omap_free_dma(int lch
)
555 spin_lock_irqsave(&dma_chan_lock
, flags
);
556 if (dma_chan
[lch
].dev_id
== -1) {
557 printk("omap_dma: trying to free nonallocated DMA channel %d\n",
559 spin_unlock_irqrestore(&dma_chan_lock
, flags
);
562 dma_chan
[lch
].dev_id
= -1;
563 dma_chan
[lch
].next_lch
= -1;
564 dma_chan
[lch
].callback
= NULL
;
565 spin_unlock_irqrestore(&dma_chan_lock
, flags
);
567 if (cpu_class_is_omap1()) {
568 /* Disable all DMA interrupts for the channel. */
569 OMAP_DMA_CICR_REG(lch
) = 0;
570 /* Make sure the DMA transfer is stopped. */
571 OMAP_DMA_CCR_REG(lch
) = 0;
574 if (cpu_is_omap24xx()) {
576 /* Disable interrupts */
577 val
= omap_readl(OMAP_DMA4_IRQENABLE_L0
);
579 omap_writel(val
, OMAP_DMA4_IRQENABLE_L0
);
581 /* Clear the CSR register and IRQ status register */
582 OMAP_DMA_CSR_REG(lch
) = OMAP2_DMA_CSR_CLEAR_MASK
;
584 val
= omap_readl(OMAP_DMA4_IRQSTATUS_L0
);
586 omap_writel(val
, OMAP_DMA4_IRQSTATUS_L0
);
588 /* Disable all DMA interrupts for the channel. */
589 OMAP_DMA_CICR_REG(lch
) = 0;
591 /* Make sure the DMA transfer is stopped. */
592 OMAP_DMA_CCR_REG(lch
) = 0;
598 * Clears any DMA state so the DMA engine is ready to restart with new buffers
599 * through omap_start_dma(). Any buffers in flight are discarded.
601 void omap_clear_dma(int lch
)
605 local_irq_save(flags
);
607 if (cpu_class_is_omap1()) {
609 OMAP_DMA_CCR_REG(lch
) &= ~OMAP_DMA_CCR_EN
;
611 /* Clear pending interrupts */
612 status
= OMAP_DMA_CSR_REG(lch
);
615 if (cpu_is_omap24xx()) {
617 u32 lch_base
= OMAP24XX_DMA_BASE
+ lch
* 0x60 + 0x80;
618 for (i
= 0; i
< 0x44; i
+= 4)
619 omap_writel(0, lch_base
+ i
);
622 local_irq_restore(flags
);
625 void omap_start_dma(int lch
)
627 if (!omap_dma_in_1510_mode() && dma_chan
[lch
].next_lch
!= -1) {
628 int next_lch
, cur_lch
;
629 char dma_chan_link_map
[OMAP_LOGICAL_DMA_CH_COUNT
];
631 dma_chan_link_map
[lch
] = 1;
632 /* Set the link register of the first channel */
635 memset(dma_chan_link_map
, 0, sizeof(dma_chan_link_map
));
636 cur_lch
= dma_chan
[lch
].next_lch
;
638 next_lch
= dma_chan
[cur_lch
].next_lch
;
640 /* The loop case: we've been here already */
641 if (dma_chan_link_map
[cur_lch
])
643 /* Mark the current channel */
644 dma_chan_link_map
[cur_lch
] = 1;
647 omap_enable_channel_irq(cur_lch
);
650 } while (next_lch
!= -1);
651 } else if (cpu_is_omap24xx()) {
652 /* Errata: Need to write lch even if not using chaining */
653 OMAP_DMA_CLNK_CTRL_REG(lch
) = lch
;
656 omap_enable_channel_irq(lch
);
658 /* Errata: On ES2.0 BUFFERING disable must be set.
659 * This will always fail on ES1.0 */
660 if (cpu_is_omap24xx()) {
661 OMAP_DMA_CCR_REG(lch
) |= OMAP_DMA_CCR_EN
;
664 OMAP_DMA_CCR_REG(lch
) |= OMAP_DMA_CCR_EN
;
666 dma_chan
[lch
].flags
|= OMAP_DMA_ACTIVE
;
669 void omap_stop_dma(int lch
)
671 if (!omap_dma_in_1510_mode() && dma_chan
[lch
].next_lch
!= -1) {
672 int next_lch
, cur_lch
= lch
;
673 char dma_chan_link_map
[OMAP_LOGICAL_DMA_CH_COUNT
];
675 memset(dma_chan_link_map
, 0, sizeof(dma_chan_link_map
));
677 /* The loop case: we've been here already */
678 if (dma_chan_link_map
[cur_lch
])
680 /* Mark the current channel */
681 dma_chan_link_map
[cur_lch
] = 1;
683 disable_lnk(cur_lch
);
685 next_lch
= dma_chan
[cur_lch
].next_lch
;
687 } while (next_lch
!= -1);
692 /* Disable all interrupts on the channel */
693 if (cpu_class_is_omap1())
694 OMAP_DMA_CICR_REG(lch
) = 0;
696 OMAP_DMA_CCR_REG(lch
) &= ~OMAP_DMA_CCR_EN
;
697 dma_chan
[lch
].flags
&= ~OMAP_DMA_ACTIVE
;
701 * Returns current physical source address for the given DMA channel.
702 * If the channel is running the caller must disable interrupts prior calling
703 * this function and process the returned value before re-enabling interrupt to
704 * prevent races with the interrupt handler. Note that in continuous mode there
705 * is a chance for CSSA_L register overflow inbetween the two reads resulting
706 * in incorrect return value.
708 dma_addr_t
omap_get_dma_src_pos(int lch
)
712 if (cpu_class_is_omap1())
713 offset
= (dma_addr_t
) (OMAP1_DMA_CSSA_L_REG(lch
) |
714 (OMAP1_DMA_CSSA_U_REG(lch
) << 16));
716 if (cpu_is_omap24xx())
717 offset
= OMAP_DMA_CSAC_REG(lch
);
723 * Returns current physical destination address for the given DMA channel.
724 * If the channel is running the caller must disable interrupts prior calling
725 * this function and process the returned value before re-enabling interrupt to
726 * prevent races with the interrupt handler. Note that in continuous mode there
727 * is a chance for CDSA_L register overflow inbetween the two reads resulting
728 * in incorrect return value.
730 dma_addr_t
omap_get_dma_dst_pos(int lch
)
734 if (cpu_class_is_omap1())
735 offset
= (dma_addr_t
) (OMAP1_DMA_CDSA_L_REG(lch
) |
736 (OMAP1_DMA_CDSA_U_REG(lch
) << 16));
738 if (cpu_is_omap24xx())
739 offset
= OMAP2_DMA_CDSA_REG(lch
);
745 * Returns current source transfer counting for the given DMA channel.
746 * Can be used to monitor the progress of a transfer inside a block.
747 * It must be called with disabled interrupts.
749 int omap_get_dma_src_addr_counter(int lch
)
751 return (dma_addr_t
) OMAP_DMA_CSAC_REG(lch
);
754 int omap_dma_running(void)
758 /* Check if LCD DMA is running */
759 if (cpu_is_omap16xx())
760 if (omap_readw(OMAP1610_DMA_LCD_CCR
) & OMAP_DMA_CCR_EN
)
763 for (lch
= 0; lch
< dma_chan_count
; lch
++)
764 if (OMAP_DMA_CCR_REG(lch
) & OMAP_DMA_CCR_EN
)
771 * lch_queue DMA will start right after lch_head one is finished.
772 * For this DMA link to start, you still need to start (see omap_start_dma)
773 * the first one. That will fire up the entire queue.
775 void omap_dma_link_lch (int lch_head
, int lch_queue
)
777 if (omap_dma_in_1510_mode()) {
778 printk(KERN_ERR
"DMA linking is not supported in 1510 mode\n");
783 if ((dma_chan
[lch_head
].dev_id
== -1) ||
784 (dma_chan
[lch_queue
].dev_id
== -1)) {
785 printk(KERN_ERR
"omap_dma: trying to link "
786 "non requested channels\n");
790 dma_chan
[lch_head
].next_lch
= lch_queue
;
794 * Once the DMA queue is stopped, we can destroy it.
796 void omap_dma_unlink_lch (int lch_head
, int lch_queue
)
798 if (omap_dma_in_1510_mode()) {
799 printk(KERN_ERR
"DMA linking is not supported in 1510 mode\n");
804 if (dma_chan
[lch_head
].next_lch
!= lch_queue
||
805 dma_chan
[lch_head
].next_lch
== -1) {
806 printk(KERN_ERR
"omap_dma: trying to unlink "
807 "non linked channels\n");
812 if ((dma_chan
[lch_head
].flags
& OMAP_DMA_ACTIVE
) ||
813 (dma_chan
[lch_head
].flags
& OMAP_DMA_ACTIVE
)) {
814 printk(KERN_ERR
"omap_dma: You need to stop the DMA channels "
815 "before unlinking\n");
819 dma_chan
[lch_head
].next_lch
= -1;
822 /*----------------------------------------------------------------------------*/
824 #ifdef CONFIG_ARCH_OMAP1
826 static int omap1_dma_handle_ch(int ch
)
830 if (enable_1510_mode
&& ch
>= 6) {
831 csr
= dma_chan
[ch
].saved_csr
;
832 dma_chan
[ch
].saved_csr
= 0;
834 csr
= OMAP_DMA_CSR_REG(ch
);
835 if (enable_1510_mode
&& ch
<= 2 && (csr
>> 7) != 0) {
836 dma_chan
[ch
+ 6].saved_csr
= csr
>> 7;
839 if ((csr
& 0x3f) == 0)
841 if (unlikely(dma_chan
[ch
].dev_id
== -1)) {
842 printk(KERN_WARNING
"Spurious interrupt from DMA channel "
843 "%d (CSR %04x)\n", ch
, csr
);
846 if (unlikely(csr
& OMAP1_DMA_TOUT_IRQ
))
847 printk(KERN_WARNING
"DMA timeout with device %d\n",
848 dma_chan
[ch
].dev_id
);
849 if (unlikely(csr
& OMAP_DMA_DROP_IRQ
))
850 printk(KERN_WARNING
"DMA synchronization event drop occurred "
851 "with device %d\n", dma_chan
[ch
].dev_id
);
852 if (likely(csr
& OMAP_DMA_BLOCK_IRQ
))
853 dma_chan
[ch
].flags
&= ~OMAP_DMA_ACTIVE
;
854 if (likely(dma_chan
[ch
].callback
!= NULL
))
855 dma_chan
[ch
].callback(ch
, csr
, dma_chan
[ch
].data
);
859 static irqreturn_t
omap1_dma_irq_handler(int irq
, void *dev_id
,
860 struct pt_regs
*regs
)
862 int ch
= ((int) dev_id
) - 1;
868 handled_now
+= omap1_dma_handle_ch(ch
);
869 if (enable_1510_mode
&& dma_chan
[ch
+ 6].saved_csr
)
870 handled_now
+= omap1_dma_handle_ch(ch
+ 6);
873 handled
+= handled_now
;
876 return handled
? IRQ_HANDLED
: IRQ_NONE
;
880 #define omap1_dma_irq_handler NULL
883 #ifdef CONFIG_ARCH_OMAP2
885 static int omap2_dma_handle_ch(int ch
)
887 u32 status
= OMAP_DMA_CSR_REG(ch
);
892 if (unlikely(dma_chan
[ch
].dev_id
== -1))
894 if (unlikely(status
& OMAP_DMA_DROP_IRQ
))
896 "DMA synchronization event drop occurred with device "
897 "%d\n", dma_chan
[ch
].dev_id
);
898 if (unlikely(status
& OMAP2_DMA_TRANS_ERR_IRQ
))
899 printk(KERN_INFO
"DMA transaction error with device %d\n",
900 dma_chan
[ch
].dev_id
);
901 if (unlikely(status
& OMAP2_DMA_SECURE_ERR_IRQ
))
902 printk(KERN_INFO
"DMA secure error with device %d\n",
903 dma_chan
[ch
].dev_id
);
904 if (unlikely(status
& OMAP2_DMA_MISALIGNED_ERR_IRQ
))
905 printk(KERN_INFO
"DMA misaligned error with device %d\n",
906 dma_chan
[ch
].dev_id
);
908 OMAP_DMA_CSR_REG(ch
) = OMAP2_DMA_CSR_CLEAR_MASK
;
910 val
= omap_readl(OMAP_DMA4_IRQSTATUS_L0
);
911 /* ch in this function is from 0-31 while in register it is 1-32 */
913 omap_writel(val
, OMAP_DMA4_IRQSTATUS_L0
);
915 if (likely(dma_chan
[ch
].callback
!= NULL
))
916 dma_chan
[ch
].callback(ch
, status
, dma_chan
[ch
].data
);
921 /* STATUS register count is from 1-32 while our is 0-31 */
922 static irqreturn_t
omap2_dma_irq_handler(int irq
, void *dev_id
,
923 struct pt_regs
*regs
)
928 val
= omap_readl(OMAP_DMA4_IRQSTATUS_L0
);
930 for (i
= 1; i
<= OMAP_LOGICAL_DMA_CH_COUNT
; i
++) {
931 int active
= val
& (1 << (i
- 1));
933 omap2_dma_handle_ch(i
- 1);
939 static struct irqaction omap24xx_dma_irq
= {
941 .handler
= omap2_dma_irq_handler
,
942 .flags
= IRQF_DISABLED
946 static struct irqaction omap24xx_dma_irq
;
949 /*----------------------------------------------------------------------------*/
951 static struct lcd_dma_info
{
954 void (* callback
)(u16 status
, void *data
);
958 unsigned long addr
, size
;
959 int rotate
, data_type
, xres
, yres
;
968 void omap_set_lcd_dma_b1(unsigned long addr
, u16 fb_xres
, u16 fb_yres
,
972 lcd_dma
.data_type
= data_type
;
973 lcd_dma
.xres
= fb_xres
;
974 lcd_dma
.yres
= fb_yres
;
977 void omap_set_lcd_dma_src_port(int port
)
979 lcd_dma
.src_port
= port
;
982 void omap_set_lcd_dma_ext_controller(int external
)
984 lcd_dma
.ext_ctrl
= external
;
987 void omap_set_lcd_dma_single_transfer(int single
)
989 lcd_dma
.single_transfer
= single
;
993 void omap_set_lcd_dma_b1_rotation(int rotate
)
995 if (omap_dma_in_1510_mode()) {
996 printk(KERN_ERR
"DMA rotation is not supported in 1510 mode\n");
1000 lcd_dma
.rotate
= rotate
;
1003 void omap_set_lcd_dma_b1_mirror(int mirror
)
1005 if (omap_dma_in_1510_mode()) {
1006 printk(KERN_ERR
"DMA mirror is not supported in 1510 mode\n");
1009 lcd_dma
.mirror
= mirror
;
1012 void omap_set_lcd_dma_b1_vxres(unsigned long vxres
)
1014 if (omap_dma_in_1510_mode()) {
1015 printk(KERN_ERR
"DMA virtual resulotion is not supported "
1019 lcd_dma
.vxres
= vxres
;
1022 void omap_set_lcd_dma_b1_scale(unsigned int xscale
, unsigned int yscale
)
1024 if (omap_dma_in_1510_mode()) {
1025 printk(KERN_ERR
"DMA scale is not supported in 1510 mode\n");
1028 lcd_dma
.xscale
= xscale
;
1029 lcd_dma
.yscale
= yscale
;
1032 static void set_b1_regs(void)
1034 unsigned long top
, bottom
;
1037 unsigned long en
, fn
;
1039 unsigned long vxres
;
1040 unsigned int xscale
, yscale
;
1042 switch (lcd_dma
.data_type
) {
1043 case OMAP_DMA_DATA_TYPE_S8
:
1046 case OMAP_DMA_DATA_TYPE_S16
:
1049 case OMAP_DMA_DATA_TYPE_S32
:
1057 vxres
= lcd_dma
.vxres
? lcd_dma
.vxres
: lcd_dma
.xres
;
1058 xscale
= lcd_dma
.xscale
? lcd_dma
.xscale
: 1;
1059 yscale
= lcd_dma
.yscale
? lcd_dma
.yscale
: 1;
1060 BUG_ON(vxres
< lcd_dma
.xres
);
1061 #define PIXADDR(x,y) (lcd_dma.addr + ((y) * vxres * yscale + (x) * xscale) * es)
1062 #define PIXSTEP(sx, sy, dx, dy) (PIXADDR(dx, dy) - PIXADDR(sx, sy) - es + 1)
1063 switch (lcd_dma
.rotate
) {
1065 if (!lcd_dma
.mirror
) {
1066 top
= PIXADDR(0, 0);
1067 bottom
= PIXADDR(lcd_dma
.xres
- 1, lcd_dma
.yres
- 1);
1068 /* 1510 DMA requires the bottom address to be 2 more
1069 * than the actual last memory access location. */
1070 if (omap_dma_in_1510_mode() &&
1071 lcd_dma
.data_type
== OMAP_DMA_DATA_TYPE_S32
)
1073 ei
= PIXSTEP(0, 0, 1, 0);
1074 fi
= PIXSTEP(lcd_dma
.xres
- 1, 0, 0, 1);
1076 top
= PIXADDR(lcd_dma
.xres
- 1, 0);
1077 bottom
= PIXADDR(0, lcd_dma
.yres
- 1);
1078 ei
= PIXSTEP(1, 0, 0, 0);
1079 fi
= PIXSTEP(0, 0, lcd_dma
.xres
- 1, 1);
1085 if (!lcd_dma
.mirror
) {
1086 top
= PIXADDR(0, lcd_dma
.yres
- 1);
1087 bottom
= PIXADDR(lcd_dma
.xres
- 1, 0);
1088 ei
= PIXSTEP(0, 1, 0, 0);
1089 fi
= PIXSTEP(0, 0, 1, lcd_dma
.yres
- 1);
1091 top
= PIXADDR(lcd_dma
.xres
- 1, lcd_dma
.yres
- 1);
1092 bottom
= PIXADDR(0, 0);
1093 ei
= PIXSTEP(0, 1, 0, 0);
1094 fi
= PIXSTEP(1, 0, 0, lcd_dma
.yres
- 1);
1100 if (!lcd_dma
.mirror
) {
1101 top
= PIXADDR(lcd_dma
.xres
- 1, lcd_dma
.yres
- 1);
1102 bottom
= PIXADDR(0, 0);
1103 ei
= PIXSTEP(1, 0, 0, 0);
1104 fi
= PIXSTEP(0, 1, lcd_dma
.xres
- 1, 0);
1106 top
= PIXADDR(0, lcd_dma
.yres
- 1);
1107 bottom
= PIXADDR(lcd_dma
.xres
- 1, 0);
1108 ei
= PIXSTEP(0, 0, 1, 0);
1109 fi
= PIXSTEP(lcd_dma
.xres
- 1, 1, 0, 0);
1115 if (!lcd_dma
.mirror
) {
1116 top
= PIXADDR(lcd_dma
.xres
- 1, 0);
1117 bottom
= PIXADDR(0, lcd_dma
.yres
- 1);
1118 ei
= PIXSTEP(0, 0, 0, 1);
1119 fi
= PIXSTEP(1, lcd_dma
.yres
- 1, 0, 0);
1121 top
= PIXADDR(0, 0);
1122 bottom
= PIXADDR(lcd_dma
.xres
- 1, lcd_dma
.yres
- 1);
1123 ei
= PIXSTEP(0, 0, 0, 1);
1124 fi
= PIXSTEP(0, lcd_dma
.yres
- 1, 1, 0);
1131 return; /* Supress warning about uninitialized vars */
1134 if (omap_dma_in_1510_mode()) {
1135 omap_writew(top
>> 16, OMAP1510_DMA_LCD_TOP_F1_U
);
1136 omap_writew(top
, OMAP1510_DMA_LCD_TOP_F1_L
);
1137 omap_writew(bottom
>> 16, OMAP1510_DMA_LCD_BOT_F1_U
);
1138 omap_writew(bottom
, OMAP1510_DMA_LCD_BOT_F1_L
);
1144 omap_writew(top
>> 16, OMAP1610_DMA_LCD_TOP_B1_U
);
1145 omap_writew(top
, OMAP1610_DMA_LCD_TOP_B1_L
);
1146 omap_writew(bottom
>> 16, OMAP1610_DMA_LCD_BOT_B1_U
);
1147 omap_writew(bottom
, OMAP1610_DMA_LCD_BOT_B1_L
);
1149 omap_writew(en
, OMAP1610_DMA_LCD_SRC_EN_B1
);
1150 omap_writew(fn
, OMAP1610_DMA_LCD_SRC_FN_B1
);
1152 w
= omap_readw(OMAP1610_DMA_LCD_CSDP
);
1154 w
|= lcd_dma
.data_type
;
1155 omap_writew(w
, OMAP1610_DMA_LCD_CSDP
);
1157 w
= omap_readw(OMAP1610_DMA_LCD_CTRL
);
1158 /* Always set the source port as SDRAM for now*/
1160 if (lcd_dma
.callback
!= NULL
)
1161 w
|= 1 << 1; /* Block interrupt enable */
1164 omap_writew(w
, OMAP1610_DMA_LCD_CTRL
);
1166 if (!(lcd_dma
.rotate
|| lcd_dma
.mirror
||
1167 lcd_dma
.vxres
|| lcd_dma
.xscale
|| lcd_dma
.yscale
))
1170 w
= omap_readw(OMAP1610_DMA_LCD_CCR
);
1171 /* Set the double-indexed addressing mode */
1173 omap_writew(w
, OMAP1610_DMA_LCD_CCR
);
1175 omap_writew(ei
, OMAP1610_DMA_LCD_SRC_EI_B1
);
1176 omap_writew(fi
>> 16, OMAP1610_DMA_LCD_SRC_FI_B1_U
);
1177 omap_writew(fi
, OMAP1610_DMA_LCD_SRC_FI_B1_L
);
1180 static irqreturn_t
lcd_dma_irq_handler(int irq
, void *dev_id
,
1181 struct pt_regs
*regs
)
1185 w
= omap_readw(OMAP1610_DMA_LCD_CTRL
);
1186 if (unlikely(!(w
& (1 << 3)))) {
1187 printk(KERN_WARNING
"Spurious LCD DMA IRQ\n");
1192 omap_writew(w
, OMAP1610_DMA_LCD_CTRL
);
1194 if (lcd_dma
.callback
!= NULL
)
1195 lcd_dma
.callback(w
, lcd_dma
.cb_data
);
1200 int omap_request_lcd_dma(void (* callback
)(u16 status
, void *data
),
1203 spin_lock_irq(&lcd_dma
.lock
);
1204 if (lcd_dma
.reserved
) {
1205 spin_unlock_irq(&lcd_dma
.lock
);
1206 printk(KERN_ERR
"LCD DMA channel already reserved\n");
1210 lcd_dma
.reserved
= 1;
1211 spin_unlock_irq(&lcd_dma
.lock
);
1212 lcd_dma
.callback
= callback
;
1213 lcd_dma
.cb_data
= data
;
1215 lcd_dma
.single_transfer
= 0;
1221 lcd_dma
.ext_ctrl
= 0;
1222 lcd_dma
.src_port
= 0;
1227 void omap_free_lcd_dma(void)
1229 spin_lock(&lcd_dma
.lock
);
1230 if (!lcd_dma
.reserved
) {
1231 spin_unlock(&lcd_dma
.lock
);
1232 printk(KERN_ERR
"LCD DMA is not reserved\n");
1236 if (!enable_1510_mode
)
1237 omap_writew(omap_readw(OMAP1610_DMA_LCD_CCR
) & ~1,
1238 OMAP1610_DMA_LCD_CCR
);
1239 lcd_dma
.reserved
= 0;
1240 spin_unlock(&lcd_dma
.lock
);
1243 void omap_enable_lcd_dma(void)
1247 /* Set the Enable bit only if an external controller is
1248 * connected. Otherwise the OMAP internal controller will
1249 * start the transfer when it gets enabled.
1251 if (enable_1510_mode
|| !lcd_dma
.ext_ctrl
)
1254 w
= omap_readw(OMAP1610_DMA_LCD_CTRL
);
1256 omap_writew(w
, OMAP1610_DMA_LCD_CTRL
);
1260 w
= omap_readw(OMAP1610_DMA_LCD_CCR
);
1262 omap_writew(w
, OMAP1610_DMA_LCD_CCR
);
1265 void omap_setup_lcd_dma(void)
1267 BUG_ON(lcd_dma
.active
);
1268 if (!enable_1510_mode
) {
1269 /* Set some reasonable defaults */
1270 omap_writew(0x5440, OMAP1610_DMA_LCD_CCR
);
1271 omap_writew(0x9102, OMAP1610_DMA_LCD_CSDP
);
1272 omap_writew(0x0004, OMAP1610_DMA_LCD_LCH_CTRL
);
1275 if (!enable_1510_mode
) {
1278 w
= omap_readw(OMAP1610_DMA_LCD_CCR
);
1279 /* If DMA was already active set the end_prog bit to have
1280 * the programmed register set loaded into the active
1283 w
|= 1 << 11; /* End_prog */
1284 if (!lcd_dma
.single_transfer
)
1285 w
|= (3 << 8); /* Auto_init, repeat */
1286 omap_writew(w
, OMAP1610_DMA_LCD_CCR
);
1290 void omap_stop_lcd_dma(void)
1295 if (enable_1510_mode
|| !lcd_dma
.ext_ctrl
)
1298 w
= omap_readw(OMAP1610_DMA_LCD_CCR
);
1300 omap_writew(w
, OMAP1610_DMA_LCD_CCR
);
1302 w
= omap_readw(OMAP1610_DMA_LCD_CTRL
);
1304 omap_writew(w
, OMAP1610_DMA_LCD_CTRL
);
1307 int omap_lcd_dma_ext_running(void)
1309 return lcd_dma
.ext_ctrl
&& lcd_dma
.active
;
1312 /*----------------------------------------------------------------------------*/
1314 static int __init
omap_init_dma(void)
1318 if (cpu_is_omap15xx()) {
1319 printk(KERN_INFO
"DMA support for OMAP15xx initialized\n");
1321 enable_1510_mode
= 1;
1322 } else if (cpu_is_omap16xx() || cpu_is_omap730()) {
1323 printk(KERN_INFO
"OMAP DMA hardware version %d\n",
1324 omap_readw(OMAP_DMA_HW_ID
));
1325 printk(KERN_INFO
"DMA capabilities: %08x:%08x:%04x:%04x:%04x\n",
1326 (omap_readw(OMAP_DMA_CAPS_0_U
) << 16) |
1327 omap_readw(OMAP_DMA_CAPS_0_L
),
1328 (omap_readw(OMAP_DMA_CAPS_1_U
) << 16) |
1329 omap_readw(OMAP_DMA_CAPS_1_L
),
1330 omap_readw(OMAP_DMA_CAPS_2
), omap_readw(OMAP_DMA_CAPS_3
),
1331 omap_readw(OMAP_DMA_CAPS_4
));
1332 if (!enable_1510_mode
) {
1335 /* Disable OMAP 3.0/3.1 compatibility mode. */
1336 w
= omap_readw(OMAP_DMA_GSCR
);
1338 omap_writew(w
, OMAP_DMA_GSCR
);
1339 dma_chan_count
= 16;
1342 if (cpu_is_omap16xx()) {
1345 /* this would prevent OMAP sleep */
1346 w
= omap_readw(OMAP1610_DMA_LCD_CTRL
);
1348 omap_writew(w
, OMAP1610_DMA_LCD_CTRL
);
1350 } else if (cpu_is_omap24xx()) {
1351 u8 revision
= omap_readb(OMAP_DMA4_REVISION
);
1352 printk(KERN_INFO
"OMAP DMA hardware revision %d.%d\n",
1353 revision
>> 4, revision
& 0xf);
1354 dma_chan_count
= OMAP_LOGICAL_DMA_CH_COUNT
;
1360 memset(&lcd_dma
, 0, sizeof(lcd_dma
));
1361 spin_lock_init(&lcd_dma
.lock
);
1362 spin_lock_init(&dma_chan_lock
);
1363 memset(&dma_chan
, 0, sizeof(dma_chan
));
1365 for (ch
= 0; ch
< dma_chan_count
; ch
++) {
1367 dma_chan
[ch
].dev_id
= -1;
1368 dma_chan
[ch
].next_lch
= -1;
1370 if (ch
>= 6 && enable_1510_mode
)
1373 if (cpu_class_is_omap1()) {
1374 /* request_irq() doesn't like dev_id (ie. ch) being
1375 * zero, so we have to kludge around this. */
1376 r
= request_irq(omap1_dma_irq
[ch
],
1377 omap1_dma_irq_handler
, 0, "DMA",
1382 printk(KERN_ERR
"unable to request IRQ %d "
1383 "for DMA (error %d)\n",
1384 omap1_dma_irq
[ch
], r
);
1385 for (i
= 0; i
< ch
; i
++)
1386 free_irq(omap1_dma_irq
[i
],
1393 if (cpu_is_omap24xx())
1394 setup_irq(INT_24XX_SDMA_IRQ0
, &omap24xx_dma_irq
);
1396 /* FIXME: Update LCD DMA to work on 24xx */
1397 if (cpu_class_is_omap1()) {
1398 r
= request_irq(INT_DMA_LCD
, lcd_dma_irq_handler
, 0,
1403 printk(KERN_ERR
"unable to request IRQ for LCD DMA "
1405 for (i
= 0; i
< dma_chan_count
; i
++)
1406 free_irq(omap1_dma_irq
[i
], (void *) (i
+ 1));
1414 arch_initcall(omap_init_dma
);
1416 EXPORT_SYMBOL(omap_get_dma_src_pos
);
1417 EXPORT_SYMBOL(omap_get_dma_dst_pos
);
1418 EXPORT_SYMBOL(omap_get_dma_src_addr_counter
);
1419 EXPORT_SYMBOL(omap_clear_dma
);
1420 EXPORT_SYMBOL(omap_set_dma_priority
);
1421 EXPORT_SYMBOL(omap_request_dma
);
1422 EXPORT_SYMBOL(omap_free_dma
);
1423 EXPORT_SYMBOL(omap_start_dma
);
1424 EXPORT_SYMBOL(omap_stop_dma
);
1425 EXPORT_SYMBOL(omap_set_dma_callback
);
1426 EXPORT_SYMBOL(omap_enable_dma_irq
);
1427 EXPORT_SYMBOL(omap_disable_dma_irq
);
1429 EXPORT_SYMBOL(omap_set_dma_transfer_params
);
1430 EXPORT_SYMBOL(omap_set_dma_color_mode
);
1431 EXPORT_SYMBOL(omap_set_dma_write_mode
);
1433 EXPORT_SYMBOL(omap_set_dma_src_params
);
1434 EXPORT_SYMBOL(omap_set_dma_src_index
);
1435 EXPORT_SYMBOL(omap_set_dma_src_data_pack
);
1436 EXPORT_SYMBOL(omap_set_dma_src_burst_mode
);
1438 EXPORT_SYMBOL(omap_set_dma_dest_params
);
1439 EXPORT_SYMBOL(omap_set_dma_dest_index
);
1440 EXPORT_SYMBOL(omap_set_dma_dest_data_pack
);
1441 EXPORT_SYMBOL(omap_set_dma_dest_burst_mode
);
1443 EXPORT_SYMBOL(omap_set_dma_params
);
1445 EXPORT_SYMBOL(omap_dma_link_lch
);
1446 EXPORT_SYMBOL(omap_dma_unlink_lch
);
1448 EXPORT_SYMBOL(omap_request_lcd_dma
);
1449 EXPORT_SYMBOL(omap_free_lcd_dma
);
1450 EXPORT_SYMBOL(omap_enable_lcd_dma
);
1451 EXPORT_SYMBOL(omap_setup_lcd_dma
);
1452 EXPORT_SYMBOL(omap_stop_lcd_dma
);
1453 EXPORT_SYMBOL(omap_lcd_dma_ext_running
);
1454 EXPORT_SYMBOL(omap_set_lcd_dma_b1
);
1455 EXPORT_SYMBOL(omap_set_lcd_dma_single_transfer
);
1456 EXPORT_SYMBOL(omap_set_lcd_dma_ext_controller
);
1457 EXPORT_SYMBOL(omap_set_lcd_dma_b1_rotation
);
1458 EXPORT_SYMBOL(omap_set_lcd_dma_b1_vxres
);
1459 EXPORT_SYMBOL(omap_set_lcd_dma_b1_scale
);
1460 EXPORT_SYMBOL(omap_set_lcd_dma_b1_mirror
);