include/asm-powerpc/cputable.h

   1 #ifndef __ASM_POWERPC_CPUTABLE_H
   2 #define __ASM_POWERPC_CPUTABLE_H
   3
   4 #include <asm/asm-compat.h>
   5
   6 #define PPC_FEATURE_32                  0x80000000
   7 #define PPC_FEATURE_64                  0x40000000
   8 #define PPC_FEATURE_601_INSTR           0x20000000
   9 #define PPC_FEATURE_HAS_ALTIVEC         0x10000000
  10 #define PPC_FEATURE_HAS_FPU             0x08000000
  11 #define PPC_FEATURE_HAS_MMU             0x04000000
  12 #define PPC_FEATURE_HAS_4xxMAC          0x02000000
  13 #define PPC_FEATURE_UNIFIED_CACHE       0x01000000
  14 #define PPC_FEATURE_HAS_SPE             0x00800000
  15 #define PPC_FEATURE_HAS_EFP_SINGLE      0x00400000
  16 #define PPC_FEATURE_HAS_EFP_DOUBLE      0x00200000
  17 #define PPC_FEATURE_NO_TB               0x00100000
  18 #define PPC_FEATURE_POWER4              0x00080000
  19 #define PPC_FEATURE_POWER5              0x00040000
  20 #define PPC_FEATURE_POWER5_PLUS         0x00020000
  21 #define PPC_FEATURE_CELL                0x00010000
  22 #define PPC_FEATURE_BOOKE               0x00008000
  23 #define PPC_FEATURE_SMT                 0x00004000
  24 #define PPC_FEATURE_ICACHE_SNOOP        0x00002000
  25 #define PPC_FEATURE_ARCH_2_05           0x00001000
  26 #define PPC_FEATURE_PA6T                0x00000800
  27 #define PPC_FEATURE_HAS_DFP             0x00000400
  28 #define PPC_FEATURE_POWER6_EXT          0x00000200
  29
  30 #define PPC_FEATURE_TRUE_LE             0x00000002
  31 #define PPC_FEATURE_PPC_LE              0x00000001
  32
  33 #ifdef __KERNEL__
  34 #ifndef __ASSEMBLY__
  35
  36 /* This structure can grow, it's real size is used by head.S code
  37  * via the mkdefs mechanism.
  38  */
  39 struct cpu_spec;
  40
  41 typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
  42 typedef void (*cpu_restore_t)(void);
  43
  44 enum powerpc_oprofile_type {
  45         PPC_OPROFILE_INVALID = 0,
  46         PPC_OPROFILE_RS64 = 1,
  47         PPC_OPROFILE_POWER4 = 2,
  48         PPC_OPROFILE_G4 = 3,
  49         PPC_OPROFILE_BOOKE = 4,
  50         PPC_OPROFILE_CELL = 5,
  51 };
  52
  53 struct cpu_spec {
  54         /* CPU is matched via (PVR & pvr_mask) == pvr_value */
  55         unsigned int    pvr_mask;
  56         unsigned int    pvr_value;
  57
  58         char            *cpu_name;
  59         unsigned long   cpu_features;           /* Kernel features */
  60         unsigned int    cpu_user_features;      /* Userland features */
  61
  62         /* cache line sizes */
  63         unsigned int    icache_bsize;
  64         unsigned int    dcache_bsize;
  65
  66         /* number of performance monitor counters */
  67         unsigned int    num_pmcs;
  68
  69         /* this is called to initialize various CPU bits like L1 cache,
  70          * BHT, SPD, etc... from head.S before branching to identify_machine
  71          */
  72         cpu_setup_t     cpu_setup;
  73         /* Used to restore cpu setup on secondary processors and at resume */
  74         cpu_restore_t   cpu_restore;
  75
  76         /* Used by oprofile userspace to select the right counters */
  77         char            *oprofile_cpu_type;
  78
  79         /* Processor specific oprofile operations */
  80         enum powerpc_oprofile_type oprofile_type;
  81
  82         /* Bit locations inside the mmcra change */
  83         unsigned long   oprofile_mmcra_sihv;
  84         unsigned long   oprofile_mmcra_sipr;
  85
  86         /* Bits to clear during an oprofile exception */
  87         unsigned long   oprofile_mmcra_clear;
  88
  89         /* Name of processor class, for the ELF AT_PLATFORM entry */
  90         char            *platform;
  91 };
  92
  93 extern struct cpu_spec          *cur_cpu_spec;
  94
  95 extern unsigned int __start___ftr_fixup, __stop___ftr_fixup;
  96
  97 extern struct cpu_spec *identify_cpu(unsigned long offset, unsigned int pvr);
  98 extern void do_feature_fixups(unsigned long value, void *fixup_start,
  99                               void *fixup_end);
 100
 101 #endif /* __ASSEMBLY__ */
 102
 103 /* CPU kernel features */
 104
 105 /* Retain the 32b definitions all use bottom half of word */
 106 #define CPU_FTR_SPLIT_ID_CACHE          ASM_CONST(0x0000000000000001)
 107 #define CPU_FTR_L2CR                    ASM_CONST(0x0000000000000002)
 108 #define CPU_FTR_SPEC7450                ASM_CONST(0x0000000000000004)
 109 #define CPU_FTR_ALTIVEC                 ASM_CONST(0x0000000000000008)
 110 #define CPU_FTR_TAU                     ASM_CONST(0x0000000000000010)
 111 #define CPU_FTR_CAN_DOZE                ASM_CONST(0x0000000000000020)
 112 #define CPU_FTR_USE_TB                  ASM_CONST(0x0000000000000040)
 113 #define CPU_FTR_604_PERF_MON            ASM_CONST(0x0000000000000080)
 114 #define CPU_FTR_601                     ASM_CONST(0x0000000000000100)
 115 #define CPU_FTR_HPTE_TABLE              ASM_CONST(0x0000000000000200)
 116 #define CPU_FTR_CAN_NAP                 ASM_CONST(0x0000000000000400)
 117 #define CPU_FTR_L3CR                    ASM_CONST(0x0000000000000800)
 118 #define CPU_FTR_L3_DISABLE_NAP          ASM_CONST(0x0000000000001000)
 119 #define CPU_FTR_NAP_DISABLE_L2_PR       ASM_CONST(0x0000000000002000)
 120 #define CPU_FTR_DUAL_PLL_750FX          ASM_CONST(0x0000000000004000)
 121 #define CPU_FTR_NO_DPM                  ASM_CONST(0x0000000000008000)
 122 #define CPU_FTR_HAS_HIGH_BATS           ASM_CONST(0x0000000000010000)
 123 #define CPU_FTR_NEED_COHERENT           ASM_CONST(0x0000000000020000)
 124 #define CPU_FTR_NO_BTIC                 ASM_CONST(0x0000000000040000)
 125 #define CPU_FTR_BIG_PHYS                ASM_CONST(0x0000000000080000)
 126 #define CPU_FTR_NODSISRALIGN            ASM_CONST(0x0000000000100000)
 127 #define CPU_FTR_PPC_LE                  ASM_CONST(0x0000000000200000)
 128 #define CPU_FTR_REAL_LE                 ASM_CONST(0x0000000000400000)
 129
 130 /*
 131  * Add the 64-bit processor unique features in the top half of the word;
 132  * on 32-bit, make the names available but defined to be 0.
 133  */
 134 #ifdef __powerpc64__
 135 #define LONG_ASM_CONST(x)               ASM_CONST(x)
 136 #else
 137 #define LONG_ASM_CONST(x)               0
 138 #endif
 139
 140 #define CPU_FTR_SLB                     LONG_ASM_CONST(0x0000000100000000)
 141 #define CPU_FTR_16M_PAGE                LONG_ASM_CONST(0x0000000200000000)
 142 #define CPU_FTR_TLBIEL                  LONG_ASM_CONST(0x0000000400000000)
 143 #define CPU_FTR_NOEXECUTE               LONG_ASM_CONST(0x0000000800000000)
 144 #define CPU_FTR_IABR                    LONG_ASM_CONST(0x0000002000000000)
 145 #define CPU_FTR_MMCRA                   LONG_ASM_CONST(0x0000004000000000)
 146 #define CPU_FTR_CTRL                    LONG_ASM_CONST(0x0000008000000000)
 147 #define CPU_FTR_SMT                     LONG_ASM_CONST(0x0000010000000000)
 148 #define CPU_FTR_COHERENT_ICACHE         LONG_ASM_CONST(0x0000020000000000)
 149 #define CPU_FTR_LOCKLESS_TLBIE          LONG_ASM_CONST(0x0000040000000000)
 150 #define CPU_FTR_CI_LARGE_PAGE           LONG_ASM_CONST(0x0000100000000000)
 151 #define CPU_FTR_PAUSE_ZERO              LONG_ASM_CONST(0x0000200000000000)
 152 #define CPU_FTR_PURR                    LONG_ASM_CONST(0x0000400000000000)
 153 #define CPU_FTR_CELL_TB_BUG             LONG_ASM_CONST(0x0000800000000000)
 154 #define CPU_FTR_SPURR                   LONG_ASM_CONST(0x0001000000000000)
 155
 156 #ifndef __ASSEMBLY__
 157
 158 #define CPU_FTR_PPCAS_ARCH_V2_BASE (CPU_FTR_SLB | \
 159                                         CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \
 160                                         CPU_FTR_NODSISRALIGN)
 161
 162 /* iSeries doesn't support large pages */
 163 #ifdef CONFIG_PPC_ISERIES
 164 #define CPU_FTR_PPCAS_ARCH_V2   (CPU_FTR_PPCAS_ARCH_V2_BASE)
 165 #else
 166 #define CPU_FTR_PPCAS_ARCH_V2   (CPU_FTR_PPCAS_ARCH_V2_BASE | CPU_FTR_16M_PAGE)
 167 #endif /* CONFIG_PPC_ISERIES */
 168
 169 /* We only set the altivec features if the kernel was compiled with altivec
 170  * support
 171  */
 172 #ifdef CONFIG_ALTIVEC
 173 #define CPU_FTR_ALTIVEC_COMP    CPU_FTR_ALTIVEC
 174 #define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
 175 #else
 176 #define CPU_FTR_ALTIVEC_COMP    0
 177 #define PPC_FEATURE_HAS_ALTIVEC_COMP    0
 178 #endif
 179
 180 /* We need to mark all pages as being coherent if we're SMP or we
 181  * have a 74[45]x and an MPC107 host bridge. Also 83xx requires
 182  * it for PCI "streaming/prefetch" to work properly.
 183  */
 184 #if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \
 185         || defined(CONFIG_PPC_83xx)
 186 #define CPU_FTR_COMMON                  CPU_FTR_NEED_COHERENT
 187 #else
 188 #define CPU_FTR_COMMON                  0
 189 #endif
 190
 191 /* The powersave features NAP & DOZE seems to confuse BDI when
 192    debugging. So if a BDI is used, disable theses
 193  */
 194 #ifndef CONFIG_BDI_SWITCH
 195 #define CPU_FTR_MAYBE_CAN_DOZE  CPU_FTR_CAN_DOZE
 196 #define CPU_FTR_MAYBE_CAN_NAP   CPU_FTR_CAN_NAP
 197 #else
 198 #define CPU_FTR_MAYBE_CAN_DOZE  0
 199 #define CPU_FTR_MAYBE_CAN_NAP   0
 200 #endif
 201
 202 #define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \
 203                      !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \
 204                      !defined(CONFIG_BOOKE))
 205
 206 #define CPU_FTRS_PPC601 (CPU_FTR_COMMON | CPU_FTR_601 | CPU_FTR_HPTE_TABLE)
 207 #define CPU_FTRS_603    (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
 208             CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
 209             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
 210 #define CPU_FTRS_604    (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
 211             CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE | \
 212             CPU_FTR_PPC_LE)
 213 #define CPU_FTRS_740_NOTAU      (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
 214             CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
 215             CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
 216 #define CPU_FTRS_740    (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
 217             CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
 218             CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
 219             CPU_FTR_PPC_LE)
 220 #define CPU_FTRS_750    (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
 221             CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
 222             CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
 223             CPU_FTR_PPC_LE)
 224 #define CPU_FTRS_750FX1 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
 225             CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
 226             CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
 227             CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM | CPU_FTR_PPC_LE)
 228 #define CPU_FTRS_750FX2 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
 229             CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
 230             CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
 231             CPU_FTR_NO_DPM | CPU_FTR_PPC_LE)
 232 #define CPU_FTRS_750FX  (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
 233             CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
 234             CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
 235             CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE)
 236 #define CPU_FTRS_750GX  (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \
 237             CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU | \
 238             CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
 239             CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE)
 240 #define CPU_FTRS_7400_NOTAU     (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
 241             CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
 242             CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \
 243             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
 244 #define CPU_FTRS_7400   (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
 245             CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
 246             CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \
 247             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
 248 #define CPU_FTRS_7450_20        (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
 249             CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
 250             CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
 251             CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
 252 #define CPU_FTRS_7450_21        (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
 253             CPU_FTR_USE_TB | \
 254             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
 255             CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
 256             CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
 257             CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
 258 #define CPU_FTRS_7450_23        (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
 259             CPU_FTR_USE_TB | \
 260             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
 261             CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
 262             CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
 263 #define CPU_FTRS_7455_1 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
 264             CPU_FTR_USE_TB | \
 265             CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \
 266             CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS | \
 267             CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
 268 #define CPU_FTRS_7455_20        (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
 269             CPU_FTR_USE_TB | \
 270             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
 271             CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
 272             CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
 273             CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE)
 274 #define CPU_FTRS_7455   (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
 275             CPU_FTR_USE_TB | \
 276             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
 277             CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
 278             CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
 279             CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
 280 #define CPU_FTRS_7447_10        (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
 281             CPU_FTR_USE_TB | \
 282             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
 283             CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
 284             CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
 285             CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE)
 286 #define CPU_FTRS_7447   (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
 287             CPU_FTR_USE_TB | \
 288             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
 289             CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
 290             CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
 291             CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
 292 #define CPU_FTRS_7447A  (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
 293             CPU_FTR_USE_TB | \
 294             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
 295             CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
 296             CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
 297             CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
 298 #define CPU_FTRS_82XX   (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
 299             CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB)
 300 #define CPU_FTRS_G2_LE  (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \
 301             CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS)
 302 #define CPU_FTRS_E300   (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \
 303             CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS | \
 304             CPU_FTR_COMMON)
 305 #define CPU_FTRS_CLASSIC32      (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
 306             CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE)
 307 #define CPU_FTRS_8XX    (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB)
 308 #define CPU_FTRS_40X    (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
 309             CPU_FTR_NODSISRALIGN)
 310 #define CPU_FTRS_44X    (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
 311             CPU_FTR_NODSISRALIGN)
 312 #define CPU_FTRS_E200   (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN)
 313 #define CPU_FTRS_E500   (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
 314             CPU_FTR_NODSISRALIGN)
 315 #define CPU_FTRS_E500_2 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
 316             CPU_FTR_BIG_PHYS | CPU_FTR_NODSISRALIGN)
 317 #define CPU_FTRS_GENERIC_32     (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
 318
 319 /* 64-bit CPUs */
 320 #define CPU_FTRS_POWER3 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
 321             CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | CPU_FTR_PPC_LE)
 322 #define CPU_FTRS_RS64   (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
 323             CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | \
 324             CPU_FTR_MMCRA | CPU_FTR_CTRL)
 325 #define CPU_FTRS_POWER4 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
 326             CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
 327             CPU_FTR_MMCRA)
 328 #define CPU_FTRS_PPC970 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
 329             CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
 330             CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA)
 331 #define CPU_FTRS_POWER5 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
 332             CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
 333             CPU_FTR_MMCRA | CPU_FTR_SMT | \
 334             CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
 335             CPU_FTR_PURR)
 336 #define CPU_FTRS_POWER6 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
 337             CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
 338             CPU_FTR_MMCRA | CPU_FTR_SMT | \
 339             CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
 340             CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE)
 341 #define CPU_FTRS_POWER6X (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
 342             CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
 343             CPU_FTR_MMCRA | CPU_FTR_SMT | \
 344             CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
 345             CPU_FTR_PURR | CPU_FTR_CI_LARGE_PAGE | \
 346             CPU_FTR_SPURR | CPU_FTR_REAL_LE)
 347 #define CPU_FTRS_CELL   (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
 348             CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
 349             CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
 350             CPU_FTR_PAUSE_ZERO | CPU_FTR_CI_LARGE_PAGE | CPU_FTR_CELL_TB_BUG)
 351 #define CPU_FTRS_PA6T (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
 352             CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \
 353             CPU_FTR_ALTIVEC_COMP | CPU_FTR_CI_LARGE_PAGE | \
 354             CPU_FTR_PURR | CPU_FTR_REAL_LE)
 355 #define CPU_FTRS_COMPATIBLE     (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
 356             CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2)
 357
 358 #ifdef __powerpc64__
 359 #define CPU_FTRS_POSSIBLE       \
 360             (CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 |        \
 361             CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_POWER6 |       \
 362             CPU_FTRS_CELL | CPU_FTRS_PA6T)
 363 #else
 364 enum {
 365         CPU_FTRS_POSSIBLE =
 366 #if CLASSIC_PPC
 367             CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU |
 368             CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 |
 369             CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX |
 370             CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 |
 371             CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 |
 372             CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 |
 373             CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX |
 374             CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_CLASSIC32 |
 375 #else
 376             CPU_FTRS_GENERIC_32 |
 377 #endif
 378 #ifdef CONFIG_8xx
 379             CPU_FTRS_8XX |
 380 #endif
 381 #ifdef CONFIG_40x
 382             CPU_FTRS_40X |
 383 #endif
 384 #ifdef CONFIG_44x
 385             CPU_FTRS_44X |
 386 #endif
 387 #ifdef CONFIG_E200
 388             CPU_FTRS_E200 |
 389 #endif
 390 #ifdef CONFIG_E500
 391             CPU_FTRS_E500 | CPU_FTRS_E500_2 |
 392 #endif
 393             0,
 394 };
 395 #endif /* __powerpc64__ */
 396
 397 #ifdef __powerpc64__
 398 #define CPU_FTRS_ALWAYS         \
 399             (CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 &        \
 400             CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_POWER6 &       \
 401             CPU_FTRS_CELL & CPU_FTRS_PA6T & CPU_FTRS_POSSIBLE)
 402 #else
 403 enum {
 404         CPU_FTRS_ALWAYS =
 405 #if CLASSIC_PPC
 406             CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
 407             CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
 408             CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
 409             CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 &
 410             CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
 411             CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
 412             CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
 413             CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_CLASSIC32 &
 414 #else
 415             CPU_FTRS_GENERIC_32 &
 416 #endif
 417 #ifdef CONFIG_8xx
 418             CPU_FTRS_8XX &
 419 #endif
 420 #ifdef CONFIG_40x
 421             CPU_FTRS_40X &
 422 #endif
 423 #ifdef CONFIG_44x
 424             CPU_FTRS_44X &
 425 #endif
 426 #ifdef CONFIG_E200
 427             CPU_FTRS_E200 &
 428 #endif
 429 #ifdef CONFIG_E500
 430             CPU_FTRS_E500 & CPU_FTRS_E500_2 &
 431 #endif
 432             CPU_FTRS_POSSIBLE,
 433 };
 434 #endif /* __powerpc64__ */
 435
 436 static inline int cpu_has_feature(unsigned long feature)
 437 {
 438         return (CPU_FTRS_ALWAYS & feature) ||
 439                (CPU_FTRS_POSSIBLE
 440                 & cur_cpu_spec->cpu_features
 441                 & feature);
 442 }
 443
 444 #endif /* !__ASSEMBLY__ */
 445
 446 #ifdef __ASSEMBLY__
 447
 448 #define BEGIN_FTR_SECTION_NESTED(label) label:
 449 #define BEGIN_FTR_SECTION               BEGIN_FTR_SECTION_NESTED(97)
 450 #define END_FTR_SECTION_NESTED(msk, val, label) \
 451         MAKE_FTR_SECTION_ENTRY(msk, val, label, __ftr_fixup)
 452 #define END_FTR_SECTION(msk, val)               \
 453         END_FTR_SECTION_NESTED(msk, val, 97)
 454
 455 #define END_FTR_SECTION_IFSET(msk)      END_FTR_SECTION((msk), (msk))
 456 #define END_FTR_SECTION_IFCLR(msk)      END_FTR_SECTION((msk), 0)
 457 #endif /* __ASSEMBLY__ */
 458
 459 #endif /* __KERNEL__ */
 460 #endif /* __ASM_POWERPC_CPUTABLE_H */