1 #include <linux/config.h>
2 #include <linux/init.h>
3 #include <linux/kernel.h>
5 #include <linux/string.h>
6 #include <linux/bitops.h>
8 #include <linux/thread_info.h>
9 #include <linux/module.h>
11 #include <asm/processor.h>
13 #include <asm/uaccess.h>
17 #ifdef CONFIG_X86_LOCAL_APIC
18 #include <asm/mpspec.h>
20 #include <mach_apic.h>
23 extern int trap_init_f00f_bug(void);
25 #ifdef CONFIG_X86_INTEL_USERCOPY
27 * Alignment at which movsl is preferred for bulk memory copies.
29 struct movsl_mask movsl_mask __read_mostly
;
32 void __cpuinit
early_intel_workaround(struct cpuinfo_x86
*c
)
34 if (c
->x86_vendor
!= X86_VENDOR_INTEL
)
36 /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
37 if (c
->x86
== 15 && c
->x86_cache_alignment
== 64)
38 c
->x86_cache_alignment
= 128;
42 * Early probe support logic for ppro memory erratum #50
44 * This is called before we do cpu ident work
47 int __cpuinit
ppro_with_ram_bug(void)
49 /* Uses data from early_cpu_detect now */
50 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
&&
51 boot_cpu_data
.x86
== 6 &&
52 boot_cpu_data
.x86_model
== 1 &&
53 boot_cpu_data
.x86_mask
< 8) {
54 printk(KERN_INFO
"Pentium Pro with Errata#50 detected. Taking evasive action.\n");
62 * P4 Xeon errata 037 workaround.
63 * Hardware prefetcher may cause stale data to be loaded into the cache.
65 static void __cpuinit
Intel_errata_workarounds(struct cpuinfo_x86
*c
)
69 if ((c
->x86
== 15) && (c
->x86_model
== 1) && (c
->x86_mask
== 1)) {
70 rdmsr (MSR_IA32_MISC_ENABLE
, lo
, hi
);
71 if ((lo
& (1<<9)) == 0) {
72 printk (KERN_INFO
"CPU: C0 stepping P4 Xeon detected.\n");
73 printk (KERN_INFO
"CPU: Disabling hardware prefetching (Errata 037)\n");
74 lo
|= (1<<9); /* Disable hw prefetching */
75 wrmsr (MSR_IA32_MISC_ENABLE
, lo
, hi
);
82 * find out the number of processor cores on the die
84 static int __cpuinit
num_cpu_cores(struct cpuinfo_x86
*c
)
86 unsigned int eax
, ebx
, ecx
, edx
;
88 if (c
->cpuid_level
< 4)
91 /* Intel has a non-standard dependency on %ecx for this CPUID level. */
92 cpuid_count(4, 0, &eax
, &ebx
, &ecx
, &edx
);
94 return ((eax
>> 26) + 1);
99 static void __cpuinit
init_intel(struct cpuinfo_x86
*c
)
104 #ifdef CONFIG_X86_F00F_BUG
106 * All current models of Pentium and Pentium with MMX technology CPUs
107 * have the F0 0F bug, which lets nonprivileged users lock up the system.
108 * Note that the workaround only should be initialized once...
112 static int f00f_workaround_enabled
= 0;
115 if ( !f00f_workaround_enabled
) {
116 trap_init_f00f_bug();
117 printk(KERN_NOTICE
"Intel Pentium with F0 0F bug - workaround enabled.\n");
118 f00f_workaround_enabled
= 1;
123 select_idle_routine(c
);
124 l2
= init_intel_cacheinfo(c
);
125 if (c
->cpuid_level
> 9 ) {
126 unsigned eax
= cpuid_eax(10);
127 /* Check for version and the number of counters */
128 if ((eax
& 0xff) && (((eax
>>8) & 0xff) > 1))
129 set_bit(X86_FEATURE_ARCH_PERFMON
, c
->x86_capability
);
132 /* SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until model 3 mask 3 */
133 if ((c
->x86
<<8 | c
->x86_model
<<4 | c
->x86_mask
) < 0x633)
134 clear_bit(X86_FEATURE_SEP
, c
->x86_capability
);
136 /* Names for the Pentium II/Celeron processors
137 detectable only by also checking the cache size.
138 Dixon is NOT a Celeron. */
140 switch (c
->x86_model
) {
142 if (c
->x86_mask
== 0) {
144 p
= "Celeron (Covington)";
146 p
= "Mobile Pentium II (Dixon)";
152 p
= "Celeron (Mendocino)";
153 else if (c
->x86_mask
== 0 || c
->x86_mask
== 5)
159 p
= "Celeron (Coppermine)";
165 strcpy(c
->x86_model_id
, p
);
167 c
->x86_max_cores
= num_cpu_cores(c
);
171 /* Work around errata */
172 Intel_errata_workarounds(c
);
174 #ifdef CONFIG_X86_INTEL_USERCOPY
176 * Set up the preferred alignment for movsl bulk memory moves
179 case 4: /* 486: untested */
181 case 5: /* Old Pentia: untested */
183 case 6: /* PII/PIII only like movsl with 8-byte alignment */
186 case 15: /* P4 is OK down to 8-byte alignment */
193 set_bit(X86_FEATURE_P4
, c
->x86_capability
);
195 set_bit(X86_FEATURE_P3
, c
->x86_capability
);
196 if ((c
->x86
== 0xf && c
->x86_model
>= 0x03) ||
197 (c
->x86
== 0x6 && c
->x86_model
>= 0x0e))
198 set_bit(X86_FEATURE_CONSTANT_TSC
, c
->x86_capability
);
202 static unsigned int intel_size_cache(struct cpuinfo_x86
* c
, unsigned int size
)
204 /* Intel PIII Tualatin. This comes in two flavours.
205 * One has 256kb of cache, the other 512. We have no way
206 * to determine which, so we use a boottime override
207 * for the 512kb model, and assume 256 otherwise.
209 if ((c
->x86
== 6) && (c
->x86_model
== 11) && (size
== 0))
214 static struct cpu_dev intel_cpu_dev __cpuinitdata
= {
216 .c_ident
= { "GenuineIntel" },
218 { .vendor
= X86_VENDOR_INTEL
, .family
= 4, .model_names
=
220 [0] = "486 DX-25/33",
231 { .vendor
= X86_VENDOR_INTEL
, .family
= 5, .model_names
=
233 [0] = "Pentium 60/66 A-step",
234 [1] = "Pentium 60/66",
235 [2] = "Pentium 75 - 200",
236 [3] = "OverDrive PODP5V83",
238 [7] = "Mobile Pentium 75 - 200",
239 [8] = "Mobile Pentium MMX"
242 { .vendor
= X86_VENDOR_INTEL
, .family
= 6, .model_names
=
244 [0] = "Pentium Pro A-step",
246 [3] = "Pentium II (Klamath)",
247 [4] = "Pentium II (Deschutes)",
248 [5] = "Pentium II (Deschutes)",
249 [6] = "Mobile Pentium II",
250 [7] = "Pentium III (Katmai)",
251 [8] = "Pentium III (Coppermine)",
252 [10] = "Pentium III (Cascades)",
253 [11] = "Pentium III (Tualatin)",
256 { .vendor
= X86_VENDOR_INTEL
, .family
= 15, .model_names
=
258 [0] = "Pentium 4 (Unknown)",
259 [1] = "Pentium 4 (Willamette)",
260 [2] = "Pentium 4 (Northwood)",
261 [4] = "Pentium 4 (Foster)",
262 [5] = "Pentium 4 (Foster)",
266 .c_init
= init_intel
,
267 .c_identify
= generic_identify
,
268 .c_size_cache
= intel_size_cache
,
271 __init
int intel_cpu_init(void)
273 cpu_devs
[X86_VENDOR_INTEL
] = &intel_cpu_dev
;
277 #ifndef CONFIG_X86_CMPXCHG
278 unsigned long cmpxchg_386_u8(volatile void *ptr
, u8 old
, u8
new)
283 /* Poor man's cmpxchg for 386. Unsuitable for SMP */
284 local_irq_save(flags
);
288 local_irq_restore(flags
);
291 EXPORT_SYMBOL(cmpxchg_386_u8
);
293 unsigned long cmpxchg_386_u16(volatile void *ptr
, u16 old
, u16
new)
298 /* Poor man's cmpxchg for 386. Unsuitable for SMP */
299 local_irq_save(flags
);
303 local_irq_restore(flags
);
306 EXPORT_SYMBOL(cmpxchg_386_u16
);
308 unsigned long cmpxchg_386_u32(volatile void *ptr
, u32 old
, u32
new)
313 /* Poor man's cmpxchg for 386. Unsuitable for SMP */
314 local_irq_save(flags
);
318 local_irq_restore(flags
);
321 EXPORT_SYMBOL(cmpxchg_386_u32
);
324 // arch_initcall(intel_cpu_init);