| blob | 73e18c5b15409e6014b29da6ffe46273c49cc22f |
1 taken from http://www.z80.info/z80-op.txt
3 ----------------------------------------------------------------
4 | |
5 | Zilog |
6 | |
7 | ZZZZZZZ 88888 000 |
8 | Z 8 8 0 0 |
9 | Z 8 8 0 0 0 |
10 | Z 88888 0 0 0 |
11 | Z 8 8 0 0 0 |
12 | Z 8 8 0 0 |
13 | ZZZZZZZ 88888 000 |
14 | |
15 | Z80 MICROPROCESSOR Instruction Set Summary |
16 | |
17 ----------------------------------------------------------------
18 ----------------------------------------------------------------
19 |Mnemonic |SZHPNC|Description |Notes |
20 |----------+------+---------------------+----------------------|
21 |ADC A,s |***V0*|Add with Carry |A=A+s+CY |
22 |ADC HL,ss |**?V0*|Add with Carry |HL=HL+ss+CY |
23 |ADD A,s |***V0*|Add |A=A+s |
24 |ADD HL,ss |--?-0*|Add |HL=HL+ss |
25 |ADD IX,pp |--?-0*|Add |IX=IX+pp |
26 |ADD IY,rr |--?-0*|Add |IY=IY+rr |
27 |AND s |***P00|Logical AND |A=A&s |
28 |BIT b,m |?*1?0-|Test Bit |m&{2^b} |
29 |CALL cc,nn|------|Conditional Call |If cc CALL |
30 |CALL nn |------|Unconditional Call |-[SP]=PC,PC=nn |
31 |CCF |--?-0*|Complement Carry Flag|CY=~CY |
32 |CP s |***V1*|Compare |A-s |
33 |CPD |****1-|Compare and Decrement|A-[HL],HL=HL-1,BC=BC-1|
34 |CPDR |****1-|Compare, Dec., Repeat|CPD till A=[HL]or BC=0|
35 |CPI |****1-|Compare and Increment|A-[HL],HL=HL+1,BC=BC-1|
36 |CPIR |****1-|Compare, Inc., Repeat|CPI till A=[HL]or BC=0|
37 |CPL |--1-1-|Complement |A=~A |
38 |DAA |***P-*|Decimal Adjust Acc. |A=BCD format |
39 |DEC s |***V1-|Decrement |s=s-1 |
40 |DEC xx |------|Decrement |xx=xx-1 |
41 |DEC ss |------|Decrement |ss=ss-1 |
42 |DI |------|Disable Interrupts | |
43 |DJNZ e |------|Dec., Jump Non-Zero |B=B-1 till B=0 |
44 |EI |------|Enable Interrupts | |
45 |EX [SP],HL|------|Exchange |[SP]<->HL |
46 |EX [SP],xx|------|Exchange |[SP]<->xx |
47 |EX AF,AF' |------|Exchange |AF<->AF' |
48 |EX DE,HL |------|Exchange |DE<->HL |
49 |EXX |------|Exchange |qq<->qq' (except AF)|
50 |HALT |------|Halt | |
51 |IM n |------|Interrupt Mode | (n=0,1,2)|
52 |IN A,[n] |------|Input |A=[n] |
53 |IN r,[C] |***P0-|Input |r=[C] |
54 |INC r |***V0-|Increment |r=r+1 |
55 |INC [HL] |***V0-|Increment |[HL]=[HL]+1 |
56 |INC xx |------|Increment |xx=xx+1 |
57 |INC [xx+d]|***V0-|Increment |[xx+d]=[xx+d]+1 |
58 |INC ss |------|Increment |ss=ss+1 |
59 |IND |?*??1-|Input and Decrement |[HL]=[C],HL=HL-1,B=B-1|
60 |INDR |?1??1-|Input, Dec., Repeat |IND till B=0 |
61 |INI |?*??1-|Input and Increment |[HL]=[C],HL=HL+1,B=B-1|
62 |INIR |?1??1-|Input, Inc., Repeat |INI till B=0 |
63 |JP [HL] |------|Unconditional Jump |PC=[HL] |
64 |JP [xx] |------|Unconditional Jump |PC=[xx] |
65 |JP nn |------|Unconditional Jump |PC=nn |
66 |JP cc,nn |------|Conditional Jump |If cc JP |
67 |JR e |------|Unconditional Jump |PC=PC+e |
68 |JR cc,e |------|Conditional Jump |If cc JR(cc=C,NC,NZ,Z)|
69 |LD dst,src|------|Load |dst=src |
70 |LD A,i |**0*0-|Load |A=i (i=I,R)|
71 |LDD |--0*0-|Load and Decrement |[DE]=[HL],HL=HL-1,# |
72 |LDDR |--000-|Load, Dec., Repeat |LDD till BC=0 |
73 |LDI |--0*0-|Load and Increment |[DE]=[HL],HL=HL+1,# |
74 |LDIR |--000-|Load, Inc., Repeat |LDI till BC=0 |
75 |NEG |***V1*|Negate |A=-A |
76 |NOP |------|No Operation | |
77 |OR s |***P00|Logical inclusive OR |A=Avs |
78 |OTDR |?1??1-|Output, Dec., Repeat |OUTD till B=0 |
79 |OTIR |?1??1-|Output, Inc., Repeat |OUTI till B=0 |
80 |OUT [C],r |------|Output |[C]=r |
81 |OUT [n],A |------|Output |[n]=A |
82 |OUTD |?*??1-|Output and Decrement |[C]=[HL],HL=HL-1,B=B-1|
83 |OUTI |?*??1-|Output and Increment |[C]=[HL],HL=HL+1,B=B-1|
84 |POP xx |------|Pop |xx=[SP]+ |
85 |POP qq |------|Pop |qq=[SP]+ |
86 |PUSH xx |------|Push |-[SP]=xx |
87 |PUSH qq |------|Push |-[SP]=qq |
88 |RES b,m |------|Reset bit |m=m&{~2^b} |
89 |RET |------|Return |PC=[SP]+ |
90 |RET cc |------|Conditional Return |If cc RET |
91 |RETI |------|Return from Interrupt|PC=[SP]+ |
92 |RETN |------|Return from NMI |PC=[SP]+ |
93 |RL m |**0P0*|Rotate Left |m={CY,m}<- |
94 |RLA |--0-0*|Rotate Left Acc. |A={CY,A}<- |
95 |RLC m |**0P0*|Rotate Left Circular |m=m<- |
96 |RLCA |--0-0*|Rotate Left Circular |A=A<- |
97 ----------------------------------------------------------------
98 ----------------------------------------------------------------
99 |Mnemonic |SZHPNC|Description |Notes |
100 |----------+------+---------------------+----------------------|
101 |RLD |**0P0-|Rotate Left 4 bits |{A,[HL]}={A,[HL]}<- ##|
102 |RR m |**0P0*|Rotate Right |m=->{CY,m} |
103 |RRA |--0-0*|Rotate Right Acc. |A=->{CY,A} |
104 |RRC m |**0P0*|Rotate Right Circular|m=->m |
105 |RRCA |--0-0*|Rotate Right Circular|A=->A |
106 |RRD |**0P0-|Rotate Right 4 bits |{A,[HL]}=->{A,[HL]} ##|
107 |RST p |------|Restart | (p=0H,8H,10H,...,38H)|
108 |SBC A,s |***V1*|Subtract with Carry |A=A-s-CY |
109 |SBC HL,ss |**?V1*|Subtract with Carry |HL=HL-ss-CY |
110 |SCF |--0-01|Set Carry Flag |CY=1 |
111 |SET b,m |------|Set bit |m=mv{2^b} |
112 |SLA m |**0P0*|Shift Left Arithmetic|m=m*2 |
113 |SRA m |**0P0*|Shift Right Arith. |m=m/2 |
114 |SRL m |**0P0*|Shift Right Logical |m=->{0,m,CY} |
115 |SUB s |***V1*|Subtract |A=A-s |
116 |XOR s |***P00|Logical Exclusive OR |A=Axs |
117 |----------+------+--------------------------------------------|
118 | F |-*01? |Flag unaffected/affected/reset/set/unknown |
119 | S |S |Sign flag (Bit 7) |
120 | Z | Z |Zero flag (Bit 6) |
121 | HC | H |Half Carry flag (Bit 4) |
122 | P/V | P |Parity/Overflow flag (Bit 2, V=overflow) |
123 | N | N |Add/Subtract flag (Bit 1) |
124 | CY | C|Carry flag (Bit 0) |
125 |-----------------+--------------------------------------------|
126 | n |Immediate addressing |
127 | nn |Immediate extended addressing |
128 | e |Relative addressing (PC=PC+2+offset) |
129 | [nn] |Extended addressing |
130 | [xx+d] |Indexed addressing |
131 | r |Register addressing |
132 | [rr] |Register indirect addressing |
133 | |Implied addressing |
134 | b |Bit addressing |
135 | p |Modified page zero addressing (see RST) |
136 |-----------------+--------------------------------------------|
137 |DEFB n(,...) |Define Byte(s) |
138 |DEFB 'str'(,...) |Define Byte ASCII string(s) |
139 |DEFS nn |Define Storage Block |
140 |DEFW nn(,...) |Define Word(s) |
141 |-----------------+--------------------------------------------|
142 | A B C D E |Registers (8-bit) |
143 | AF BC DE HL |Register pairs (16-bit) |
144 | F |Flag register (8-bit) |
145 | I |Interrupt page address register (8-bit) |
146 | IX IY |Index registers (16-bit) |
147 | PC |Program Counter register (16-bit) |
148 | R |Memory Refresh register |
149 | SP |Stack Pointer register (16-bit) |
150 |-----------------+--------------------------------------------|
151 | b |One bit (0 to 7) |
152 | cc |Condition (C,M,NC,NZ,P,PE,PO,Z) |
153 | d |One-byte expression (-128 to +127) |
154 | dst |Destination s, ss, [BC], [DE], [HL], [nn] |
155 | e |One-byte expression (-126 to +129) |
156 | m |Any register r, [HL] or [xx+d] |
157 | n |One-byte expression (0 to 255) |
158 | nn |Two-byte expression (0 to 65535) |
159 | pp |Register pair BC, DE, IX or SP |
160 | qq |Register pair AF, BC, DE or HL |
161 | qq' |Alternative register pair AF, BC, DE or HL |
162 | r |Register A, B, C, D, E, H or L |
163 | rr |Register pair BC, DE, IY or SP |
164 | s |Any register r, value n, [HL] or [xx+d] |
165 | src |Source s, ss, [BC], [DE], [HL], nn, [nn] |
166 | ss |Register pair BC, DE, HL or SP |
167 | xx |Index register IX or IY |
168 |-----------------+--------------------------------------------|
169 | + - * / ^ |Add/subtract/multiply/divide/exponent |
170 | & ~ v x |Logical AND/NOT/inclusive OR/exclusive OR |
171 | <- -> |Rotate left/right |
172 | [ ] |Indirect addressing |
173 | [ ]+ -[ ] |Indirect addressing auto-increment/decrement|
174 | { } |Combination of operands |
175 | # |Also BC=BC-1,DE=DE-1 |
176 | ## |Only lower 4 bits of accumulator A used |
177 ----------------------------------------------------------------