| blob | 8871fad2a33fc2b3ff0c92f2ec2fb33fb54de435 |
1 taken from http://www.z80.info/z80oplist.txt
3 Full Z80 Opcode List Including Undocumented Opcodes
4 ===================================================
5 File: DOCS.Comp.Z80.OpList - Update: 0.10
6 Author: J.G.Harston - Date: 09-09-1997
8 nn nn DD nn CB nn FD CB ff nn ED nn
9 --------------------------------------------------------------------------
10 00 NOP - RLC B rlc (iy+0)->b MOS_QUIT
11 01 LD BC,&0000 - RLC C rlc (iy+0)->c MOS_CLI
12 02 LD (BC),A - RLC D rlc (iy+0)->d MOS_BYTE
13 03 INC BC - RLC E rlc (iy+0)->e MOS_WORD
14 04 INC B - RLC H rlc (iy+0)->h MOS_WRCH
15 05 DEC B - RLC L rlc (iy+0)->l MOS_RDCH
16 06 LD B,&00 - RLC (HL) RLC (IY+0) MOS_FILE
17 07 RLCA - RLC A rlc (iy+0)->a MOS_ARGS
18 08 EX AF,AF' - RRC B rrc (iy+0)->b MOS_BGET
19 09 ADD HL,BC ADD IX,BC RRC C rrc (iy+0)->c MOS_BPUT
20 0A LD A,(BC) - RRC D rrc (iy+0)->d MOS_GBPB
21 0B DEC BC - RRC E rrc (iy+0)->e MOS_FIND
22 0C INC C - RRC H rrc (iy+0)->h MOS_FF0C
23 0D DEC C - RRC L rrc (iy+0)->l MOS_FF0D
24 0E LD C,&00 - RRC (HL) RRC (IY+0) MOS_FF0E
25 0F RRCA - RRC A rrc (iy+0)->a MOS_FF0F
26 10 DJNZ &4546 - RL B rl (iy+0)->b -
27 11 LD DE,&0000 - RL C rl (iy+0)->c -
28 12 LD (DE),A - RL D rl (iy+0)->d -
29 13 INC DE - RL E rl (iy+0)->e -
30 14 INC D - RL H rl (iy+0)->h -
31 15 DEC D - RL L rl (iy+0)->l -
32 16 LD D,&00 - RL (HL) RL (IY+0) -
33 17 RLA - RL A rl (iy+0)->a -
34 18 JR &4546 - RR B rr (iy+0)->b -
35 19 ADD HL,DE ADD IX,DE RR C rr (iy+0)->c -
36 1A LD A,(DE) - RR D rr (iy+0)->d -
37 1B DEC DE - RR E rr (iy+0)->e -
38 1C INC E - RR H rr (iy+0)->h -
39 1D DEC E - RR L rr (iy+0)->l -
40 1E LD E,&00 - RR (HL) RR (IY+0) -
41 1F RRA - RR A rr (iy+0)->a -
42 20 JR NZ,&4546 - SLA B sla (iy+0)->b -
43 21 LD HL,&0000 LD IX,&0000 SLA C sla (iy+0)->c -
44 22 LD (&0000),HL LD (&0000),IX SLA D sla (iy+0)->d -
45 23 INC HL INC IX SLA E sla (iy+0)->e -
46 24 INC H INC IXH SLA H sla (iy+0)->h -
47 25 DEC H DEC IXH SLA L sla (iy+0)->l -
48 26 LD H,&00 LD IXH,&00 SLA (HL) SLA (IY+0) -
49 27 DAA - SLA A sla (iy+0)->a -
50 28 JR Z,&4546 - SRA B sra (iy+0)->b -
51 29 ADD HL,HL ADD IX,IX SRA C sra (iy+0)->c -
52 2A LD HL,(&0000) LD IX,(&0000) SRA D sra (iy+0)->d -
53 2B DEC HL DEC IX SRA E sra (iy+0)->e -
54 2C INC L INC IXL SRA H sra (iy+0)->h -
55 2D DEC L DEC IXL SRA L sra (iy+0)->l -
56 2E LD L,&00 LD IXL,&00 SRA (HL) SRA (IY+0) -
57 2F CPL - SRA A sra (iy+0)->a -
58 30 JR NC,&4546 - SLS B sls (iy+0)->b -
59 31 LD SP,&0000 - SLS C sls (iy+0)->c -
60 32 LD (&0000),A - SLS D sls (iy+0)->d -
61 33 INC SP - SLS E sls (iy+0)->e -
62 34 INC (HL) INC (IX+0) SLS H sls (iy+0)->h -
63 35 DEC (HL) DEC (IX+0) SLS L sls (iy+0)->l -
64 36 LD (HL),&00 LD (IX+0),&00 SLS (HL) SLS (IY+0) -
65 37 SCF - SLS A sls (iy+0)->a -
66 38 JR C,&4546 - SRL B srl (iy+0)->b -
67 39 ADD HL,SP ADD IX,SP SRL C srl (iy+0)->c -
68 3A LD A,(&0000) - SRL D srl (iy+0)->d -
69 3B DEC SP - SRL E srl (iy+0)->e -
70 3C INC A - SRL H srl (iy+0)->h -
71 3D DEC A - SRL L srl (iy+0)->l -
72 3E LD A,&00 - SRL (HL) SRL (IY+0) -
73 3F CCF - SRL A srl (iy+0)->a -
74 40 LD B,B - BIT 0,B bit 0,(iy+0)->b IN B,(C)
75 41 LD B,C - BIT 0,C bit 0,(iy+0)->c OUT (C),B
76 42 LD B,D - BIT 0,D bit 0,(iy+0)->d SBC HL,BC
77 43 LD B,E - BIT 0,E bit 0,(iy+0)->e LD (&0000),BC
78 44 LD B,H LD B,IXH BIT 0,H bit 0,(iy+0)->h NEG
79 45 LD B,L LD B,IXL BIT 0,L bit 0,(iy+0)->l RETN
80 46 LD B,(HL) LD B,(IX+0) BIT 0,(HL) BIT 0,(IY+0) IM 0
81 47 LD B,A - BIT 0,A bit 0,(iy+0)->a LD I,A
82 48 LD C,B - BIT 1,B bit 1,(iy+0)->b IN C,(C)
83 49 LD C,C - BIT 1,C bit 1,(iy+0)->c OUT (C),C
84 4A LD C,D - BIT 1,D bit 1,(iy+0)->d ADC HL,BC
85 4B LD C,E - BIT 1,E bit 1,(iy+0)->e LD BC,(&0000)
86 4C LD C,H LD C,IXH BIT 1,H bit 1,(iy+0)->h [neg]
87 4D LD C,L LD C,IXL BIT 1,L bit 1,(iy+0)->l RETI
88 4E LD C,(HL) LD C,(IX+0) BIT 1,(HL) BIT 1,(IY+0) [im0]
89 4F LD C,A - BIT 1,A bit 1,(iy+0)->a LD R,A
90 50 LD D,B - BIT 2,B bit 2,(iy+0)->b IN D,(C)
91 51 LD D,C - BIT 2,C bit 2,(iy+0)->c OUT (C),D
92 52 LD D,D - BIT 2,D bit 2,(iy+0)->d SBC HL,DE
93 53 LD D,E - BIT 2,E bit 2,(iy+0)->e LD (&0000),DE
94 54 LD D,H LD D,IXH BIT 2,H bit 2,(iy+0)->h [neg]
95 55 LD D,L LD D,IXL BIT 2,L bit 2,(iy+0)->l [retn]
96 56 LD D,(HL) LD D,(IX+0) BIT 2,(HL) BIT 2,(IY+0) IM 1
97 57 LD D,A - BIT 2,A bit 2,(iy+0)->a LD A,I
98 58 LD E,B - BIT 3,B bit 3,(iy+0)->b IN E,(C)
99 59 LD E,C - BIT 3,C bit 3,(iy+0)->c OUT (C),E
100 5A LD E,D - BIT 3,D bit 3,(iy+0)->d ADC HL,DE
101 5B LD E,E - BIT 3,E bit 3,(iy+0)->e LD DE,(&0000)
102 5C LD E,H LD E,IXH BIT 3,H bit 3,(iy+0)->h [neg]
103 5D LD E,L LD E,IXL BIT 3,L bit 3,(iy+0)->l [reti]
104 5E LD E,(HL) LD E,(IX+0) BIT 3,(HL) BIT 3,(IY+0) IM 2
105 5F LD E,A - BIT 3,A bit 3,(iy+0)->a LD A,R
106 60 LD H,B LD IXH,B BIT 4,B bit 4,(iy+0)->b IN H,(C)
107 61 LD H,C LD IXH,C BIT 4,C bit 4,(iy+0)->c OUT (C),H
108 62 LD H,D LD IXH,D BIT 4,D bit 4,(iy+0)->d SBC HL,HL
109 63 LD H,E LD IXH,E BIT 4,E bit 4,(iy+0)->e LD (&0000),HL
110 64 LD H,H LD IXH,IXH BIT 4,H bit 4,(iy+0)->h [neg]
111 65 LD H,L LD IXH,IXL BIT 4,L bit 4,(iy+0)->l [retn]
112 66 LD H,(HL) LD H,(IX+0) BIT 4,(HL) BIT 4,(IY+0) [im0]
113 67 LD H,A LD IXH,A BIT 4,A bit 4,(iy+0)->a RRD
114 68 LD L,B LD IXL,B BIT 5,B bit 5,(iy+0)->b IN L,(C)
115 69 LD L,C LD IXL,C BIT 5,C bit 5,(iy+0)->c OUT (C),L
116 6A LD L,D LD IXL,D BIT 5,D bit 5,(iy+0)->d ADC HL,HL
117 6B LD L,E LD IXL,E BIT 5,E bit 5,(iy+0)->e LD HL,(&0000)
118 6C LD L,H LD IXL,IXH BIT 5,H bit 5,(iy+0)->h [neg]
119 6D LD L,L LD IXL,IXL BIT 5,L bit 5,(iy+0)->l [reti]
120 6E LD L,(HL) LD L,(IX+0) BIT 5,(HL) BIT 5,(IY+0) [im0]
121 6F LD L,A LD IXL,A BIT 5,A bit 5,(iy+0)->a RLD
122 70 LD (HL),B LD (IX+0),B BIT 6,B bit 6,(iy+0)->b IN F,(C)
123 71 LD (HL),C LD (IX+0),C BIT 6,C bit 6,(iy+0)->c OUT (C),F
124 72 LD (HL),D LD (IX+0),D BIT 6,D bit 6,(iy+0)->d SBC HL,SP
125 73 LD (HL),E LD (IX+0),E BIT 6,E bit 6,(iy+0)->e LD (&0000),SP
126 74 LD (HL),H LD (IX+0),H BIT 6,H bit 6,(iy+0)->h [neg]
127 75 LD (HL),L LD (IX+0),L BIT 6,L bit 6,(iy+0)->l [retn]
128 76 HALT - BIT 6,(HL) BIT 6,(IY+0) [im1]
129 77 LD (HL),A LD (IX+0),A BIT 6,A bit 6,(iy+0)->a [ld i,i?]
130 78 LD A,B - BIT 7,B bit 7,(iy+0)->b IN A,(C)
131 79 LD A,C - BIT 7,C bit 7,(iy+0)->c OUT (C),A
132 7A LD A,D - BIT 7,D bit 7,(iy+0)->d ADC HL,SP
133 7B LD A,E - BIT 7,E bit 7,(iy+0)->e LD SP,(&0000)
134 7C LD A,H LD A,IXH BIT 7,H bit 7,(iy+0)->h [neg]
135 7D LD A,L LD A,IXL BIT 7,L bit 7,(iy+0)->l [reti]
136 7E LD A,(HL) LD A,(IX+0) BIT 7,(HL) BIT 7,(IY+0) [im2]
137 7F LD A,A - BIT 7,A bit 7,(iy+0)->a [ld r,r?]
138 80 ADD A,B - RES 0,B res 0,(iy+0)->b -
139 81 ADD A,C - RES 0,C res 0,(iy+0)->c -
140 82 ADD A,D - RES 0,D res 0,(iy+0)->d -
141 83 ADD A,E - RES 0,E res 0,(iy+0)->e -
142 84 ADD A,H ADD A,IXH RES 0,H res 0,(iy+0)->h -
143 85 ADD A,L ADD A,IXL RES 0,L res 0,(iy+0)->l -
144 86 ADD A,(HL) ADD A,(IX+0) RES 0,(HL) RES 0,(IY+0) -
145 87 ADD A,A - RES 0,A res 0,(iy+0)->a -
146 88 ADC A,B - RES 1,B res 1,(iy+0)->b -
147 89 ADC A,C - RES 1,C res 1,(iy+0)->c -
148 8A ADC A,D - RES 1,D res 1,(iy+0)->d -
149 8B ADC A,E - RES 1,E res 1,(iy+0)->e -
150 8C ADC A,H ADC A,IXH RES 1,H res 1,(iy+0)->h -
151 8D ADC A,L ADC A,IXL RES 1,L res 1,(iy+0)->l -
152 8E ADC A,(HL) ADC A,(IX+0) RES 1,(HL) RES 1,(IY+0) -
153 8F ADC A,A - RES 1,A res 1,(iy+0)->a -
154 90 SUB A,B - RES 2,B res 2,(iy+0)->b -
155 91 SUB A,C - RES 2,C res 2,(iy+0)->c -
156 92 SUB A,D - RES 2,D res 2,(iy+0)->d -
157 93 SUB A,E - RES 2,E res 2,(iy+0)->e -
158 94 SUB A,H SUB A,IXH RES 2,H res 2,(iy+0)->h -
159 95 SUB A,L SUB A,IXL RES 2,L res 2,(iy+0)->l -
160 96 SUB A,(HL) SUB A,(IX+0) RES 2,(HL) RES 2,(IY+0) -
161 97 SUB A,A - RES 2,A res 2,(iy+0)->a -
162 98 SBC A,B - RES 3,B res 3,(iy+0)->b -
163 99 SBC A,C - RES 3,C res 3,(iy+0)->c -
164 9A SBC A,D - RES 3,D res 3,(iy+0)->d -
165 9B SBC A,E - RES 3,E res 3,(iy+0)->e -
166 9C SBC A,H SBC A,IXH RES 3,H res 3,(iy+0)->h -
167 9D SBC A,L SBC A,IXL RES 3,L res 3,(iy+0)->l -
168 9E SBC A,(HL) SBC A,(IX+0) RES 3,(HL) RES 3,(IY+0) -
169 9F SBC A,A - RES 3,A res 3,(iy+0)->a -
170 A0 AND B - RES 4,B res 4,(iy+0)->b LDI
171 A1 AND C - RES 4,C res 4,(iy+0)->c CPI
172 A2 AND D - RES 4,D res 4,(iy+0)->d INI
173 A3 AND E - RES 4,E res 4,(iy+0)->e OTI
174 A4 AND H AND IXH RES 4,H res 4,(iy+0)->h -
175 A5 AND L AND IXL RES 4,L res 4,(iy+0)->l -
176 A6 AND (HL) AND (IX+0) RES 4,(HL) RES 4,(IY+0) -
177 A7 AND A - RES 4,A res 4,(iy+0)->a -
178 A8 XOR B - RES 5,B res 5,(iy+0)->b LDD
179 A9 XOR C - RES 5,C res 5,(iy+0)->c CPD
180 AA XOR D - RES 5,D res 5,(iy+0)->d IND
181 AB XOR E - RES 5,E res 5,(iy+0)->e OTD
182 AC XOR H XOR IXH RES 5,H res 5,(iy+0)->h -
183 AD XOR L XOR IXL RES 5,L res 5,(iy+0)->l -
184 AE XOR (HL) XOR (IX+0) RES 5,(HL) RES 5,(IY+0) -
185 AF XOR A - RES 5,A res 5,(iy+0)->a -
186 B0 OR B - RES 6,B res 6,(iy+0)->b LDIR
187 B1 OR C - RES 6,C res 6,(iy+0)->c CPIR
188 B2 OR D - RES 6,D res 6,(iy+0)->d INIR
189 B3 OR E - RES 6,E res 6,(iy+0)->e OTIR
190 B4 OR H OR IXH RES 6,H res 6,(iy+0)->h -
191 B5 OR L OR IXL RES 6,L res 6,(iy+0)->l -
192 B6 OR (HL) OR (IX+0) RES 6,(HL) RES 6,(IY+0) -
193 B7 OR A - RES 6,A res 6,(iy+0)->a -
194 B8 CP B - RES 7,B res 7,(iy+0)->b LDDR
195 B9 CP C - RES 7,C res 7,(iy+0)->c CPDR
196 BA CP D - RES 7,D res 7,(iy+0)->d INDR
197 BB CP E - RES 7,E res 7,(iy+0)->e OTDR
198 BC CP H CP IXH RES 7,H res 7,(iy+0)->h -
199 BD CP L CP IXL RES 7,L res 7,(iy+0)->l -
200 BE CP (HL) CP (IX+0) RES 7,(HL) RES 7,(IY+0) -
201 BF CP A - RES 7,A res 7,(iy+0)->a -
202 C0 RET NZ - SET 0,B set 0,(iy+0)->b -
203 C1 POP BC - SET 0,C set 0,(iy+0)->c -
204 C2 JP NZ,&0000 - SET 0,D set 0,(iy+0)->d -
205 C3 JP &0000 - SET 0,E set 0,(iy+0)->e -
206 C4 CALL NZ,&0000 - SET 0,H set 0,(iy+0)->h -
207 C5 PUSH BC - SET 0,L set 0,(iy+0)->l -
208 C6 ADD A,&00 - SET 0,(HL) SET 0,(IY+0) -
209 C7 RST &00 - SET 0,A set 0,(iy+0)->a -
210 C8 RET Z - SET 1,B set 1,(iy+0)->b -
211 C9 RET - SET 1,C set 1,(iy+0)->c -
212 CA JP Z,&0000 - SET 1,D set 1,(iy+0)->d -
213 CB **** CB **** - SET 1,E set 1,(iy+0)->e -
214 CC CALL Z,&0000 - SET 1,H set 1,(iy+0)->h -
215 CD CALL &0000 - SET 1,L set 1,(iy+0)->l -
216 CE ADC A,&00 - SET 1,(HL) SET 1,(IY+0) -
217 CF RST &08 - SET 1,A set 1,(iy+0)->a -
218 D0 RET NC - SET 2,B set 2,(iy+0)->b -
219 D1 POP DE - SET 2,C set 2,(iy+0)->c -
220 D2 JP NC,&0000 - SET 2,D set 2,(iy+0)->d -
221 D3 OUT (&00),A - SET 2,E set 2,(iy+0)->e -
222 D4 CALL NC,&0000 - SET 2,H set 2,(iy+0)->h -
223 D5 PUSH DE - SET 2,L set 2,(iy+0)->l -
224 D6 SUB A,&00 - SET 2,(HL) SET 2,(IY+0) -
225 D7 RST &10 - SET 2,A set 2,(iy+0)->a -
226 D8 RET C - SET 3,B set 3,(iy+0)->b -
227 D9 EXX - SET 3,C set 3,(iy+0)->c -
228 DA JP C,&0000 - SET 3,D set 3,(iy+0)->d -
229 DB IN A,(&00) - SET 3,E set 3,(iy+0)->e -
230 DC CALL C,&0000 - SET 3,H set 3,(iy+0)->h -
231 DD **** DD **** - SET 3,L set 3,(iy+0)->l -
232 DE SBC A,&00 - SET 3,(HL) SET 3,(IY+0) -
233 DF RST &18 - SET 3,A set 3,(iy+0)->a -
234 E0 RET PO - SET 4,B set 4,(iy+0)->b -
235 E1 POP HL POP IX SET 4,C set 4,(iy+0)->c -
236 E2 JP PO,&0000 - SET 4,D set 4,(iy+0)->d -
237 E3 EX (SP),HL EX (SP),IX SET 4,E set 4,(iy+0)->e -
238 E4 CALL PO,&0000 - SET 4,H set 4,(iy+0)->h -
239 E5 PUSH HL PUSH IX SET 4,L set 4,(iy+0)->l -
240 E6 AND &00 - SET 4,(HL) SET 4,(IY+0) -
241 E7 RST &20 - SET 4,A set 4,(iy+0)->a -
242 E8 RET PE - SET 5,B set 5,(iy+0)->b -
243 E9 JP (HL) JP (IX) SET 5,C set 5,(iy+0)->c -
244 EA JP PE,&0000 - SET 5,D set 5,(iy+0)->d -
245 EB EX DE,HL - SET 5,E set 5,(iy+0)->e -
246 EC CALL PE,&0000 - SET 5,H set 5,(iy+0)->h -
247 ED **** ED **** - SET 5,L set 5,(iy+0)->l -
248 EE XOR &00 - SET 5,(HL) SET 5,(IY+0) -
249 EF RST &28 - SET 5,A set 5,(iy+0)->a -
250 F0 RET P - SET 6,B set 6,(iy+0)->b -
251 F1 POP AF - SET 6,C set 6,(iy+0)->c -
252 F2 JP P,&0000 - SET 6,D set 6,(iy+0)->d -
253 F3 DI - SET 6,E set 6,(iy+0)->e -
254 F4 CALL P,&0000 - SET 6,H set 6,(iy+0)->h -
255 F5 PUSH AF - SET 6,L set 6,(iy+0)->l -
256 F6 OR &00 - SET 6,(HL) SET 6,(IY+0) -
257 F7 RST &30 - SET 6,A set 6,(iy+0)->a -
258 F8 RET M - SET 7,B set 7,(iy+0)->b [z80]
259 F9 LD SP,HL - SET 7,C set 7,(iy+0)->c [z80]
260 FA JP M,&0000 - SET 7,D set 7,(iy+0)->d [z80]
261 FB EI - SET 7,E set 7,(iy+0)->e ED_LOAD
262 FC CALL M,&0000 - SET 7,H set 7,(iy+0)->h [z80]
263 FD **** FD **** - SET 7,L set 7,(iy+0)->l [z80]
264 FE CP &00 - SET 7,(HL) SET 7,(IY+0) [z80]
265 FF RST &38 - SET 7,A set 7,(iy+0)->a ED_DOS
267 Notes on index registers
268 ------------------------
269 Where DD and IX are mentioned, FD and IY may be substituted and vis versa.
271 Notes on Indexed Shift/Bit Operations
272 -------------------------------------
273 A shift or bit operation on an indexed byte in memory is done by prefixing
274 a CB opcode refering to (HL) with DD or FD to specify (IX+n) or (IY+n).
275 If the CB opcode does not refer to (HL), slightly differing things happen.
276 The majority of Z80 CPUs execute them as shown; the shift or bit operation
277 is done on and indexed byte in memory, and then if the opcode does not
278 specify (HL) originally, the resultant byte is copied into the specified
279 register. This is summarised with this example:
280 CB 0x RLC r FD CB nn 0x RLC (IY+nn)->r
281 for x=0..5, 7 for r=B,C,D,E,H,L,A
283 Some CPUs allow access to the high and low halves of the index register,
284 if x is 4 or 5, the operation does RLC IYH or RLC IYH.
285 CB 04 RLC H FD CB nn 04 RLC IYH
286 CB 05 RLC L FD CB nn 05 RLC IYL
288 Some CPUs treat all the subcodes as accessing the indexed byte and nothing
289 else:
290 CB 0x RLC r FD CB nn 0X RLC (IY+nn)
291 for all x=0..7
293 Notes on ED opcodes
294 -------------------
295 J.G.Harston's !Z80Tube Z80 CoPro emulator includes the extra opcodes ED00
296 to ED0F to interface with the host. G.A.Lunter's Z80 Spectrum emulator
297 includes the extra opcodes EDF8 to EDFF to interface to the host.