1 taken from http://www.z80.info/z80ins.txt
3 This file is from the book:
4 Microprocessor Technology ISBN 0835943925
7 Alvin Albrecht aralbrec@concentric.net
9 OCR , retyping, and checking done by:
10 Vaggelis Kapartzianis zx32@usa.net
12 Thanks to you guys for this great work :-)
20 IO - internal CPU Operation
21 MR - Memory Read ODL - Operand Data Read of Low Byte
22 MRH - Memory Read of High Byte PR - Port Read
23 MRL - Memory Read of Low Byte PW - Port Write
24 MW - Memory Write SRH - Stack Read of High Byte
25 MWH - Memory Write of High Byte SRL - Stack Read of Low Byte
26 MWL - Memory Write of Low Byte SWH - Stack Write of High Byte
27 OCF - Op Code Fetch SWL - Stack Write of Low byte
28 ODH - Operand Data Read of High Byte ( ) - Number of T-States in that Machine Cycle
30 Z80 INSTRUCTION BREAKDOWN BY MACHINE CODE
31 =========================================
33 INSTRUCTION BYTES M1 M2 M3 M4 M5
35 ====================================================================================================
40 LD r,(HL) 1 OCF(4) MR(3)
41 LD (HL),r OCF(4) MW(3)
43 LD r,(IX+d) 3 OCF(4)/OCF(4) OD(3) IO(5) MR(3)
44 LD (IX+d),r OCF(4)/OCF(4) OD(3) IO(5) MW(3)
46 LD (HL),n 2 OCF(4) OD(3) MW(3)
49 LD A,(DE) 1 OCF(4) MR(3)
51 LD (DE),A OCF(4) MW(3)
53 LD A,(nn) 3 OCF(4) ODL(3) ODH(3) MR(3)
54 LD (nn),A OCF(4) ODL(3) ODH(3) MW(3)
57 LD A,R 2 OCF(4)/OCF(5)
61 LD dd,nn 3 OCF(4) ODL(3) ODH(3)
63 LD IX,nn 4 OCF(4)/OCF(4) ODL(3) ODH(3)
65 LD HL,(nn) 3 OCF(4) ODL(3) ODH(3) MRL(3) MRH(3)
66 LD (nn),HL OCF(4) ODL(3) ODH(3) MWL(3) MWH(3)
68 LD dd,(nn) 4 OCF(4)/OCF(4) ODL(3) ODH(3) MRL(3) MRH(3)
69 LD (nn),dd OCF(4)/OCF(4) ODL(3) ODH(3) MWL(3) MWH(3)
70 LD IX,(nn) OCF(4)/OCF(4) ODL(3) ODH(3) MRL(3) MRH(3)
71 LD (nn),IX OCF(4)/OCF(4) ODL(3) ODH(3) MWL(3) MWH(3)
75 LD SP,IX 2 OCF(4)/OCF(6)
77 PUSH qq 1 OCF(5) SWH(3) SWL(3)
80 PUSH IX 2 OCF(4)/OCF(5) SWH(3) SWL(3)
83 POP qq 1 OCF(4) SRL(3) SRH(3)
86 POP IX 2 OCF(4)/OCF(4) SRL(3) SRH(3)
95 EX (SP),HL 1 OCF(4) SRL(3) SRH(4) SWH(3) SWL(5)
98 EX (SP),IX 2 OCF(4)/OCF(4) SRL(3) SRH(4) SWH(3) SWL(5)
102 LDI 2 OCF(4)/OCF(4) MR(3) MW(5)
107 LDIR 2 OCF(4)/OCF(4) MR(3) MW(5) IO(5)*
118 ALU A,n 2 OCF(4) OD(3)
120 ALU A,(HL) 1 OCF(4) MR(3)
122 ALU A,(IX+d) 3 OCF(4)/OCF(4) OD(3) IO(5) MR(3)
128 INC (HL) 1 OCF(4) MR(4) MW(3)
131 INC (IX+D) 2 OCF(4)/OCF(4) OD(3) IO(5) MR(4) MW(3)
147 ADD HL,ss 1 OCF(4) IO(4) IO(3)
149 ADC HL,ss 2 OCF(4)/OCF(4) IO(4) IO(3)
156 DEC IX 2 OCF(4)/OCF(6)
164 RLC r 2 OCF(4)/OCF(4)
172 RLC (HL) 2 OCF(4)/OCF(4) MR(4) MW(3)
180 RLC (IX+d) 4 OCF(4)/OCF(4) OD(3) IO(5) MR(4) MW(3)
188 RLD 2 OCF(4)/OCF(4) MR(3) IO(4) MW(3)
191 BIT b,r 2 OCF(4)/OCF(4)
195 BIT b,(HL) 2 OCF(4)/OCF(4) MR(4)
197 SET b,(HL) 2 OCF(4)/OCF(4) MR(4) MW(3)
200 BIT b,(IX+d) 4 OCF(4)/OCF(4) OD(3) IO(5) MR(4)
202 SET b,(IX+d) 4 OCF(4)/OCF(4) OD(3) IO(5) MR(4) MW(3)
205 JP nn 3 OCF(4) ODL(3) ODH(3)
208 JR e 2 OCF(4) OD(3) IO(5)
210 JR C,e 2 OCF(4) OD(3) IO(5)*
211 JR NC,e *If condition is met
217 JP (IX) 2 OCF(4)/OCF(4)
219 DJNZ,e 2 OCF(5) OD(3) IO(5)*
222 CALL nn 3 OCF(4) ODL(3) ODH(4) SWH(3) SWL(3)
223 CALL cc,nn SP-1 ---> SP-1 --->
226 CALL cc,nn 3 OCF(4) ODL(3) ODH(3)
229 RET 1 OCF(4) SRL(3) SRH(3)
232 RET cc 1 OCF(5) SRL(3)* SRH(3)*
236 RETI 2 OCF(4)/OCF(4) SRL(3) SRH(3)
237 RETN SP+1 ---> SP+1 --->
239 RST p 1 OCF(5) SWH(3) SWL(3)
242 IN A,(n) 2 OCF(4) OD(3) PR(4)
244 IN r,(c) 2 OCF(4)/OCF(4) PR(4)
246 INI 2 OCF(4)/OCF(5) PR(4) MW(3)
249 INIR 2 OCF(4)/OCF(5) PR(4) MW(3) IO(5)
252 OUT (n),A 2 OCF(4) OD(3) PW(4)
254 OUT (C),r 2 OCF(4)/OCF(4) PW(4)
256 OUTI 2 OCF(4)/OCF(5) MR(3) PW(4)
259 OTIR 2 OCF(4)/OCF(5) MR(3) PW(4) IO(5)
266 NMI _ OCF(5)* SWH(3) SWL(3) *Op Code Ignored
269 MODE 0 - INTA(6) ODL(3) ODH(4) SWH(3) SWL(3)
270 (CALL INSERTED) SP-1 ---> SP-1 --->
272 - INTA(6) SWH(3) SWL(3)
276 MODE 1 INTA(7) SWH(3) SWL(3)
281 MODE 2 - INTA(7) SWH(3) SWL(3) MRL(3) MRH(3)