usr/src/uts/common/sys/sata/adapters/nv_sata/nv_sgpio.h

   1 /*
   2  * CDDL HEADER START
   3  *
   4  * The contents of this file are subject to the terms of the
   5  * Common Development and Distribution License (the "License").
   6  * You may not use this file except in compliance with the License.
   7  *
   8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
   9  * or http://www.opensolaris.org/os/licensing.
  10  * See the License for the specific language governing permissions
  11  * and limitations under the License.
  12  *
  13  * When distributing Covered Code, include this CDDL HEADER in each
  14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
  15  * If applicable, add the following below this CDDL HEADER, with the
  16  * fields enclosed by brackets "[]" replaced with your own identifying
  17  * information: Portions Copyright [yyyy] [name of copyright owner]
  18  *
  19  * CDDL HEADER END
  20  */
  21
  22 /*
  23  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
  24  * Use is subject to license terms.
  25  */
  26
  27 #ifndef _NV_SGPIO_H
  28 #define _NV_SGPIO_H
  29
  30
  31 #ifdef  __cplusplus
  32 extern "C" {
  33 #endif
  34
  35 /*
  36  * SGPIO Command Timeout (2000ms, in nsecs)
  37  */
  38 #define NV_SGP_CMD_TIMEOUT      2000000000
  39
  40 /*
  41  * SGPIO Configuration Space Offsets
  42  */
  43 #define SGPIO_CSRP      0x58
  44 #define SGPIO_CBP       0x5c
  45
  46
  47 /*
  48  * SGPIO Command/Status Register
  49  */
  50
  51 /* Command field - write-only */
  52 #define SGPIO_CSR_CMD_MASK      0x000000e0
  53 #define SGPIO_CSR_CMD_SHFT      5
  54 #define SGPIO_CSR_CMD_SET(y)    (((y) << SGPIO_CSR_CMD_SHFT) & \
  55                                     SGPIO_CSR_CMD_MASK)
  56
  57 /* Command field values */
  58 #define SGPIO_CMD_RESET         0x0
  59 #define SGPIO_CMD_READ_PARAMS   0x1
  60 #define SGPIO_CMD_READ_DATA     0x2
  61 #define SGPIO_CMD_WRITE_DATA    0x3
  62
  63 /* Command Status field - read-only */
  64 #define SGPIO_CSR_CSTAT_MASK    0x00000018
  65 #define SGPIO_CSR_CSTAT_SHFT    3
  66 #define SGPIO_CSR_CSTAT(x)      (((x) & SGPIO_CSR_CSTAT_MASK) >> \
  67                                     SGPIO_CSR_CSTAT_SHFT)
  68
  69 /* Command Status field values */
  70 #define SGPIO_CMD_OK            0x0
  71 #define SGPIO_CMD_ACTIVE        0x1
  72 #define SGPIO_CMD_ERROR         0x2
  73
  74 /* Sequence field - read-only */
  75 #define SGPIO_CSR_SEQ_MASK      0x00000004
  76 #define SGPIO_CSR_SEQ_SHFT      2
  77 #define SGPIO_CSR_SEQ(x)        (((x) & SGPIO_CSR_SEQ_MASK) >> \
  78                                     SGPIO_CSR_SEQ_SHFT)
  79
  80 /* SGPIO Status field - read-only */
  81 #define SGPIO_CSR_SSTAT_MASK    0x00000003
  82 #define SGPIO_CSR_SSTAT_SHFT    0
  83 #define SGPIO_CSR_SSTAT(x)      (((x) & SGPIO_CSR_SSTAT_MASK) >> \
  84                                     SGPIO_CSR_SSTAT_SHFT)
  85
  86 /* SGPIO Status field values */
  87 #define SGPIO_STATE_RESET       0x0
  88 #define SGPIO_STATE_OPERATIONAL 0x1
  89 #define SGPIO_STATE_ERROR       0x2
  90
  91
  92 /*
  93  * SGPIO Control Block
  94  * This is not the entire control block.  It stops at the last register
  95  * that could possibly be used.
  96  */
  97 typedef struct nv_sgp_cb {
  98 #if defined(__amd64)
  99         uint64_t        sgpio_sr;       /* Scratch Register 0-1 */
 100 #else
 101         uint32_t        sgpio_sr;       /* Scratch Register 0-1 */
 102         uint32_t        sgpio_sr1;      /* Scratch Register 0-1 */
 103 #endif
 104         uint32_t        sgpio_nvcr;     /* NVIDIA Configuration Register */
 105         uint32_t        sgpio_cr0;      /* Configuration Register 0 */
 106         uint32_t        sgpio_cr1;      /* Configuration Register 1 */
 107         uint32_t        rsrd;
 108         uint32_t        sgpio_gptxcr;   /* General Purpose Transmit */
 109                                         /* Configuration Register */
 110         uint32_t        sgpio_gprxcr;   /* General Purpose Receive */
 111                                         /* Configuration Register */
 112         uint32_t        sgpio0_tr;      /* SGPIO 0 Transmit Register */
 113         uint32_t        sgpio1_tr;      /* SGPIO 1 Transmit Register */
 114 } nv_sgp_cb_t;
 115
 116
 117 /*
 118  * NVIDIA Configuration Register (SGPIO_NVCR)
 119  * Contains read-only configuration fields that are unique to NVIDIA's
 120  * implementation of SGPIO and therefore not defined in SFF8485.
 121  */
 122
 123 /* Initiator Count */
 124 #define SGP_NVCR_INIT_CNT_MASK  0x0000000f
 125 #define SGP_NVCR_INIT_CNT_SHFT  0
 126 #define SGP_NVCR_INIT_CNT(x)    (((x) & SGP_NVCR_INIT_CNT_MASK) >> \
 127                                     SGP_NVCR_INIT_CNT_SHFT)
 128
 129 /* fixed value */
 130 #define SGPIO_NVCR_INIT_CNT_VAL 0x2
 131
 132 /* Command Block Size */
 133 #define SGP_NVCR_CB_SIZE_MASK   0x0000ff00
 134 #define SGP_NVCR_CB_SIZE_SHFT   8
 135 #define SGP_NVCR_CB_SIZE(x)     (((x) & SGP_NVCR_CB_SIZE_MASK) >> \
 136                                     SGP_NVCR_CB_SIZE_SHFT)
 137
 138 /* Command Block Version */
 139 #define SGP_NVCR_CB_VERS_MASK   0x00ff0000
 140 #define SGP_NVCR_CB_VERS_SHFT   16
 141 #define SGP_NVCR_CB_VERS(x)     (((x) & SGP_NVCR_CB_VERS_MASK) >> \
 142                                     SGP_NVCR_CB_VERS_SHFT)
 143
 144 /* current version value */
 145 #define SGP_NVCR_CB_VERSION     0
 146
 147
 148 /*
 149  * SGPIO Configuration Register 0 (SGPIO_CR0)
 150  */
 151
 152 /* Version */
 153 #define SGP_CR0_VERS_MASK       0x00000f00
 154 #define SGP_CR0_VERS_SHFT       8
 155 #define SGP_CR0_VERS(x)         (((x) & SGP_CR0_VERS_MASK) >> \
 156                                     SGP_CR0_VERS_SHFT)
 157
 158 /* fixed value */
 159 #define SGP_CR0_VERSION         0
 160
 161 /* Enable - write-only */
 162 #define SGP_CR0_ENABLE_MASK     0x00800000
 163
 164 /* CFG Register Count */
 165 #define SGP_CR0_CFG_RC_MASK     0x00700000
 166 #define SGP_CR0_CFG_RC_SHFT     20
 167 #define SGP_CR0_CFG_RC(x)       (((x) & SGP_CR0_CFG_RC_MASK) >> \
 168                                     SGP_CR0_CFG_RC_SHFT)
 169
 170 /* fixed value */
 171 #define SGPIO_CR_GP_REG_COUNT   0x1
 172
 173 /* GP Register Count */
 174 #define SGP_CR0_GP_RC_MASK      0x000f0000
 175 #define SGP_CR0_GP_RC_SHFT      16
 176 #define SGP_CR0_GP_RC(x)        (((x) & SGP_CR0_GP_RC_MASK) >> \
 177                                     SGP_CR0_GP_RC_SHFT)
 178
 179 /* fixed value */
 180 #define SGPIO_CR_CFG_REG_COUNT  0x2
 181
 182 /* Supported Drive Count */
 183 #define SGP_CR0_DRV_CNT_MASK    0xff000000
 184 #define SGP_CR0_DRV_CNT_SHFT    24
 185 #define SGP_CR0_DRV_CNT(x)      (((x) & SGP_CR0_DRV_CNT_MASK) >> \
 186                                     SGP_CR0_DRV_CNT_SHFT)
 187
 188 /* fixed value */
 189 #define SGPIO_DRV_CNT_VALUE     4
 190
 191 /*
 192  * SGPIO Configuration Register 1 (SGPIO_CR1)
 193  */
 194
 195 #ifdef SGPIO_BLINK
 196 /*
 197  * NVIDIA documents these Blink Generator Rate values.  However,
 198  * setting up the LEDs to use these Blink Generators does not result
 199  * in blinking LEDs.
 200  */
 201
 202 /* Blink Generator Rate B */
 203 #define SGPIO_CR1_BGR_B_MASK    0x0000f000
 204 #define SGPIO_CR1_BGR_B_SHFT    12
 205 #define SGPIO_CR1_BGR_B_SET(y)  ((y) << SGPIO_CR1_BGR_B_SHFT) & \
 206                                     SGPIO_CR1_BGR_B_MASK)
 207
 208 /* Blink Generator Rate A */
 209 #define SGPIO_CR1_BGR_A_MASK    0x00000f00
 210 #define SGPIO_CR1_BGR_A_SHFT    8
 211 #define SGPIO_CR1_BGR_A_SET(y)  ((y) << SGPIO_CR1_BGR_A_SHFT) & \
 212                                     SGPIO_CR1_BGR_A_MASK)
 213
 214 /* Blink Generator Rate values */
 215 #define SGPIO_BLK_1_8           0x0     /* 1/8 seconds */
 216 #define SGPIO_BLK_2_8           0x1     /* 2/8 seconds */
 217 #define SGPIO_BLK_3_8           0x2     /* 3/8 seconds */
 218 #define SGPIO_BLK_4_8           0x3     /* 4/8 seconds */
 219 #define SGPIO_BLK_5_8           0x4     /* 5/8 seconds */
 220 #define SGPIO_BLK_6_8           0x5     /* 6/8 seconds */
 221 #define SGPIO_BLK_7_8           0x6     /* 7/8 seconds */
 222 #define SGPIO_BLK_8_8           0x7     /* 8/8 seconds */
 223 #define SGPIO_BLK_9_8           0x8     /* 9/8 seconds */
 224 #define SGPIO_BLK_10_8          0x9     /* 10/8 seconds */
 225 #define SGPIO_BLK_11_8          0xa     /* 11/8 seconds */
 226 #define SGPIO_BLK_12_8          0xb     /* 12/8 seconds */
 227 #define SGPIO_BLK_13_8          0xc     /* 13/8 seconds */
 228 #define SGPIO_BLK_14_8          0xd     /* 14/8 seconds */
 229 #define SGPIO_BLK_15_8          0xe     /* 15/8 seconds */
 230 #define SGPIO_BLK_16_8          0xf     /* 16/8 seconds */
 231 #endif  /* SGPIO_BLINK */
 232
 233 /*
 234  * SGPIO 0 Transmit Register (SGPIO_0_TR)
 235  */
 236
 237 /* Drive x Activity/Locate/Error */
 238 #define SGPIO0_TR_DRV_SET(y, a) (((y) & 0xff) << ((3 - (a)) * 8))
 239 #define SGPIO0_TR_DRV_CLR(a)    ~(0xff << ((3 - (a)) * 8))
 240 #define SGPIO0_TR_DRV(x, a)     (((x) >> ((3 - (a)) * 8)) & 0xff)
 241 #define TR_ACTIVE_MASK_ALL      0xe0e0e0e0
 242 #define TR_LOCATE_MASK_ALL      0x18181818
 243 #define TR_ERROR_MASK_ALL       0x07070707
 244
 245 /* Drive x Activity */
 246 #define TR_ACTIVE_MASK          0xe0
 247 #define TR_ACTIVE_SHFT          5
 248 #define TR_ACTIVE_SET(y)        (((y) << TR_ACTIVE_SHFT) & TR_ACTIVE_MASK)
 249 #define TR_ACTIVE(x)            (((x) & TR_ACTIVE_MASK) >> TR_ACTIVE_SHFT)
 250
 251 /* Drive x Activity values */
 252 #define TR_ACTIVE_DISABLE       0x0     /* Disable activity indicator */
 253 #define TR_ACTIVE_ENABLE        0x1     /* Enable activity indicator */
 254 #ifdef SGPIO_BLINK
 255 #define TR_ACTIVE_BLINK_A_ON    0x2     /* Select blink generator A, 50% */
 256                                         /* duty cycle, on for the first */
 257                                         /* half-cycle, off for the second */
 258                                         /* half. */
 259 #define TR_ACTIVE_BLINK_A_OFF   0x3     /* Select blink generator A, 50% */
 260                                         /* duty cycle, off for the first */
 261                                         /* half-cycle, on for the second */
 262                                         /* half. */
 263 #define TR_ACTIVE_BLINK_B_ON    0x6     /* Select blink generator B, 50% */
 264                                         /* duty cycle, on for the first */
 265                                         /* half-cycle, off for the second */
 266                                         /* half. */
 267 #define TR_ACTIVE_BLINK_B_OFF   0x7     /* Select blink generator B, 50% */
 268                                         /* duty cycle, off for the first */
 269                                         /* half-cycle, on for the second */
 270                                         /* half. */
 271 #endif  /* SGPIO_BLINK */
 272
 273 /* Drive x Locate */
 274 #define TR_LOCATE_MASK          0x18
 275 #define TR_LOCATE_SHFT          3
 276 #define TR_LOCATE_SET(y)        (((y) << TR_LOCATE_SHFT) & TR_LOCATE_MASK)
 277 #define TR_LOCATE(x)            (((x) & TR_LOCATE_MASK) >> TR_LOCATE_SHFT)
 278
 279 /* Drive x Locate values */
 280 #define TR_LOCATE_DISABLE       0x0     /* Disable locate indicator */
 281 #define TR_LOCATE_ENABLE        0x1     /* Enable locate indicator */
 282 #ifdef SGPIO_BLINK
 283 #define TR_LOCATE_BLINK_ON      0x2     /* Select blink generator A, 50% */
 284                                         /* duty cycle, on for the first */
 285                                         /* half-cycle, off for the second */
 286                                         /* half. */
 287 #define TR_LOCATE_BLINK_OFF     0x3     /* Select blink generator A, 50% */
 288                                         /* duty cycle, off for the first */
 289                                         /* half-cycle, on for the second */
 290                                         /* half. */
 291 #endif  /* SGPIO_BLINK */
 292
 293 /* Drive x Error */
 294 #define TR_ERROR_MASK           0x07
 295 #define TR_ERROR_SHFT           0
 296 #define TR_ERROR_SET(y)         (((y) << TR_ERROR_SHFT) & TR_ERROR_MASK)
 297 #define TR_ERROR(x)             (((x) & TR_ERROR_MASK) >> TR_ERROR_SHFT)
 298
 299 /* Drive x Error values */
 300 #define TR_ERROR_DISABLE        0x0     /* Disable error indicator */
 301 #define TR_ERROR_ENABLE         0x1     /* Enable error indicator */
 302 #ifdef SGPIO_BLINK
 303 #define TR_ERROR_BLINK_A_ON     0x2     /* Select blink generator A, 50% */
 304                                         /* duty cycle, on for the first */
 305                                         /* half-cycle, off for the second */
 306                                         /* half for error indicator. */
 307 #define TR_ERROR_BLINK_A_OFF    0x3     /* Select blink generator A, 50% */
 308                                         /* duty cycle, off for the first */
 309                                         /* half-cycle, on for the second */
 310                                         /* half for error indicator. */
 311 #define TR_ERROR_BLINK_B_ON     0x6     /* Select blink generator B, 50% */
 312                                         /* duty cycle, on for the first */
 313                                         /* half-cycle, off for the second */
 314                                         /* half for error indicator. */
 315 #define TR_ERROR_BLINK_B_OFF    0x7     /* Select blink generator B, 50% */
 316                                         /* duty cycle, off for the first */
 317                                         /* half-cycle, on for the second */
 318                                         /* half for error indicator. */
 319 #endif  /* SGPIO_BLINK */
 320
 321 /*
 322  * SGPIO 1 Transmit Register (SGPIO_1_TR)
 323  */
 324
 325 /* Drive x Activity/Locate/Error */
 326 #define SGPIO1_TR_DRV_SET(y, a) (((y) & 0xff) << ((7 - (a)) * 8))
 327 #define SGPIO1_TR_DRV_CLR(a)    ~(0xff << ((7 - (a)) * 8))
 328 #define SGPIO1_TR_DRV(x, a)     (((x) >> ((7 - (a)) * 8)) & 0xff)
 329
 330 #ifdef  __cplusplus
 331 }
 332 #endif
 333
 334 #endif /* _NV_SGPIO_H */