usr/src/uts/common/sys/sata/adapters/ahci/ahcireg.h

   1 /*
   2  * CDDL HEADER START
   3  *
   4  * The contents of this file are subject to the terms of the
   5  * Common Development and Distribution License (the "License").
   6  * You may not use this file except in compliance with the License.
   7  *
   8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
   9  * or http://www.opensolaris.org/os/licensing.
  10  * See the License for the specific language governing permissions
  11  * and limitations under the License.
  12  *
  13  * When distributing Covered Code, include this CDDL HEADER in each
  14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
  15  * If applicable, add the following below this CDDL HEADER, with the
  16  * fields enclosed by brackets "[]" replaced with your own identifying
  17  * information: Portions Copyright [yyyy] [name of copyright owner]
  18  *
  19  * CDDL HEADER END
  20  */
  21
  22 /*
  23  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
  24  * Use is subject to license terms.
  25  */
  26 /*
  27  * Copyright 2013 Nexenta Systems, Inc.  All rights reserved.
  28  */
  29
  30 #ifndef _AHCIREG_H
  31 #define _AHCIREG_H
  32
  33 #ifdef  __cplusplus
  34 extern "C" {
  35 #endif
  36
  37 #define AHCI_MAX_PORTS          32
  38 #define AHCI_PORT_MAX_CMD_SLOTS 32
  39
  40 #define VIA_VENID               0x1106
  41
  42 /*
  43  * In AHCI spec, command table contains a list of 0 (no data transfer)
  44  * to up to 65,535 scatter/gather entries for the data transfer.
  45  */
  46 #define AHCI_MAX_PRDT_NUMBER    65535
  47 #define AHCI_MIN_PRDT_NUMBER    1
  48
  49 /*
  50  * The default value of s/g entrie is 257, at least 1MB (4KB/pg * 256) + 1
  51  * if misaligned, and it's tuable by setting ahci_dma_prdt_number in
  52  * /etc/system file.
  53  */
  54 #define AHCI_PRDT_NUMBER        257
  55
  56 /* PCI header offset for AHCI Base Address */
  57 #define AHCI_PCI_RNUM           0x24
  58
  59 /* various global HBA capability bits */
  60 #define AHCI_HBA_CAP_NP         (0x1f << 0) /* number of ports */
  61 #define AHCI_HBA_CAP_SXS        (0x1 << 5) /* external SATA */
  62 #define AHCI_HBA_CAP_EMS        (0x1 << 6) /* enclosure management */
  63 #define AHCI_HBA_CAP_CCCS       (0x1 << 7) /* command completed coalescing */
  64 #define AHCI_HBA_CAP_NCS        (0x1f << 8) /* number of command slots */
  65 #define AHCI_HBA_CAP_PSC        (0x1 << 13) /* partial state capable */
  66 #define AHCI_HBA_CAP_SSC        (0x1 << 14) /* slumber state capable */
  67 #define AHCI_HBA_CAP_PMD        (0x1 << 15) /* PIO multiple DRQ block */
  68 #define AHCI_HBA_CAP_FBSS       (0x1 << 16) /* FIS-based switching */
  69 #define AHCI_HBA_CAP_SPM        (0x1 << 17) /* port multiplier */
  70 #define AHCI_HBA_CAP_SAM        (0x1 << 18) /* AHCI mode only */
  71 #define AHCI_HBA_CAP_SNZO       (0x1 << 19) /* non-zero DMA offsets */
  72 #define AHCI_HBA_CAP_ISS        (0xf << 20) /* interface speed support */
  73 #define AHCI_HBA_CAP_SCLO       (0x1 << 24) /* command list override */
  74 #define AHCI_HBA_CAP_SAL        (0x1 << 25) /* activity LED */
  75 #define AHCI_HBA_CAP_SALP       (0x1 << 26) /* aggressive link power mgmt */
  76 #define AHCI_HBA_CAP_SSS        (0x1 << 27) /* staggered  spin-up */
  77 #define AHCI_HBA_CAP_SMPS       (0x1 << 28) /* mechanical presence switch */
  78 #define AHCI_HBA_CAP_SSNTF      (0x1 << 29) /* Snotification register */
  79 #define AHCI_HBA_CAP_SNCQ       (0x1 << 30) /* Native Command Queuing */
  80 #define AHCI_HBA_CAP_S64A       ((uint32_t)0x1 << 31) /* 64-bit addressing */
  81 #define AHCI_HBA_CAP_NCS_SHIFT  8  /* Number of command slots */
  82 #define AHCI_HBA_CAP_ISS_SHIFT  20 /* Interface speed support */
  83
  84 /* various global HBA control bits */
  85 #define AHCI_HBA_GHC_HR         (0x1 << 0) /* HBA Reset */
  86 #define AHCI_HBA_GHC_IE         (0x1 << 1) /* Interrupt Enable */
  87 #define AHCI_HBA_GHC_MRSM       (0x1 << 2) /* MSI Revert to Single Message */
  88 #define AHCI_HBA_GHC_AE         ((uint32_t)0x1 << 31) /* AHCI Enable */
  89
  90 /* various global HBA Command Completion Coalescing (CCC) control bits */
  91 #define AHCI_HBA_CCC_CTL_EN             0x00000001  /* Enable */
  92 #define AHCI_HBA_CCC_CTL_INT_MASK       (0x1f << 3) /* Interrupt */
  93 #define AHCI_HBA_CCC_CTL_CC_MASK        0x0000ff00  /* Command Completions */
  94 #define AHCI_HBA_CCC_CTL_TV_MASK        0xffff0000  /* Timeout Value */
  95 #define AHCI_HBA_CCC_CTL_INT_SHIFT      3
  96 #define AHCI_HBA_CCC_CTL_CC_SHIFT       8
  97 #define AHCI_HBA_CCC_CTL_TV_SHIFT       16
  98
  99 /* global HBA Enclosure Management Location (EM_LOC) */
 100 #define AHCI_HBA_EM_LOC_SZ_MASK         0x0000ffff /* Buffer Size */
 101 #define AHCI_HBA_EM_LOC_OFST_MASK       0xffff0000 /* Offset */
 102 #define AHCI_HBA_EM_LOC_OFST_SHIFT      16
 103
 104 /* global HBA Enclosure Management Control (EM_CTL) bits */
 105 #define AHCI_HBA_EM_CTL_STS_MR          (0x1 << 0) /* Message Received */
 106 #define AHCI_HBA_EM_CTL_CTL_TM          (0x1 << 8) /* Transmit Message */
 107 #define AHCI_HBA_EM_CTL_CTL_RST         (0x1 << 9) /* Reset */
 108 #define AHCI_HBA_EM_CTL_SUPP_LED        (0x1 << 16) /* LED Message Types */
 109 #define AHCI_HBA_EM_CTL_SUPP_SAFTE      (0x1 << 17) /* SAF-TE EM Messages */
 110 #define AHCI_HBA_EM_CTL_SUPP_SES2       (0x1 << 18) /* SES-2 EM Messages */
 111 #define AHCI_HBA_EM_CTL_SUPP_SGPIO      (0x1 << 19) /* SGPIO EM Messages */
 112 #define AHCI_HBA_EM_CTL_ATTR_SMB        (0x1 << 24) /* Single Message Buffer */
 113 #define AHCI_HBA_EM_CTL_ATTR_XMT        (0x1 << 25) /* Transmit Only */
 114 #define AHCI_HBA_EM_CTL_ATTR_ALHD       (0x1 << 26) /* Activity LED HW Driven */
 115 #define AHCI_HBA_EM_CTL_ATTR_PM         (0x1 << 27) /* PM Support */
 116
 117
 118 /* global HBA registers definitions */
 119 #define AHCI_GLOBAL_OFFSET(ahci_ctlp)   (ahci_ctlp->ahcictl_ahci_addr)
 120         /* HBA Capabilities */
 121 #define AHCI_GLOBAL_CAP(ahci_ctlp)      (AHCI_GLOBAL_OFFSET(ahci_ctlp) + 0x00)
 122         /* Global HBA Control */
 123 #define AHCI_GLOBAL_GHC(ahci_ctlp)      (AHCI_GLOBAL_OFFSET(ahci_ctlp) + 0x04)
 124         /* Interrupt Status Register */
 125 #define AHCI_GLOBAL_IS(ahci_ctlp)       (AHCI_GLOBAL_OFFSET(ahci_ctlp) + 0x08)
 126         /* Ports Implemented */
 127 #define AHCI_GLOBAL_PI(ahci_ctlp)       (AHCI_GLOBAL_OFFSET(ahci_ctlp) + 0x0c)
 128         /* AHCI Version */
 129 #define AHCI_GLOBAL_VS(ahci_ctlp)       (AHCI_GLOBAL_OFFSET(ahci_ctlp) + 0x10)
 130         /* Command Completion Coalescing Control */
 131 #define AHCI_GLOBAL_CCC_CTL(ahci_ctlp)  (AHCI_GLOBAL_OFFSET(ahci_ctlp) + 0x14)
 132         /* Command Completion Coalescing Ports */
 133 #define AHCI_GLOBAL_CCC_PORTS(ahci_ctlp)        \
 134                                         (AHCI_GLOBAL_OFFSET(ahci_ctlp) + 0x18)
 135         /* Enclosure Management Location */
 136 #define AHCI_GLOBAL_EM_LOC(ahci_ctlp)   (AHCI_GLOBAL_OFFSET(ahci_ctlp) + 0x1c)
 137         /* Enclosure Management Control */
 138 #define AHCI_GLOBAL_EM_CTL(ahci_ctlp)   (AHCI_GLOBAL_OFFSET(ahci_ctlp) + 0x20)
 139         /* HBA Capabilities Extended (AHCI spec 1.2) */
 140 #define AHCI_GLOBAL_CAP2(ahci_ctlp)     (AHCI_GLOBAL_OFFSET(ahci_ctlp) + 0x24)
 141         /* BIOS/OS Handoff Control and Status (AHCI spec 1.2) */
 142 #define AHCI_GLOBAL_BOHC(ahci_ctlp)     (AHCI_GLOBAL_OFFSET(ahci_ctlp) + 0x28)
 143
 144 #define AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)  \
 145         ((0x1 << port) & ahci_ctlp->ahcictl_ports_implemented)
 146
 147 /* various port interrupt bits */
 148         /* Device to Host Register FIS Interrupt */
 149 #define AHCI_INTR_STATUS_DHRS (0x1 << 0)
 150         /* PIO Setup FIS Interrupt */
 151 #define AHCI_INTR_STATUS_PSS                    (0x1 << 1)
 152         /* DMA Setup FIS Interrupt */
 153 #define AHCI_INTR_STATUS_DSS                    (0x1 << 2)
 154         /* Set Device Bits Interrupt */
 155 #define AHCI_INTR_STATUS_SDBS                   (0x1 << 3)
 156         /* Unknown FIS Interrupt */
 157 #define AHCI_INTR_STATUS_UFS                    (0x1 << 4)
 158         /* Descriptor Processed */
 159 #define AHCI_INTR_STATUS_DPS                    (0x1 << 5)
 160         /* Port Connect Change Status */
 161 #define AHCI_INTR_STATUS_PCS                    (0x1 << 6)
 162         /* Device Mechanical Presence Status */
 163 #define AHCI_INTR_STATUS_DMPS                   (0x1 << 7)
 164         /* PhyRdy Change Status */
 165 #define AHCI_INTR_STATUS_PRCS                   (0x1 << 22)
 166         /* Incorrect Port Multiplier Status */
 167 #define AHCI_INTR_STATUS_IPMS                   (0x1 << 23)
 168         /* Overflow Status */
 169 #define AHCI_INTR_STATUS_OFS                    (0x1 << 24)
 170         /* Interface Non-fatal Error Status */
 171 #define AHCI_INTR_STATUS_INFS                   (0x1 << 26)
 172         /* Interface Fatal Error Status */
 173 #define AHCI_INTR_STATUS_IFS                    (0x1 << 27)
 174         /* Host Bus Data Error Status */
 175 #define AHCI_INTR_STATUS_HBDS                   (0x1 << 28)
 176         /* Host Bus Fatal Error Status */
 177 #define AHCI_INTR_STATUS_HBFS                   (0x1 << 29)
 178         /* Task File Error Status */
 179 #define AHCI_INTR_STATUS_TFES                   (0x1 << 30)
 180         /* Cold Port Detect Status */
 181 #define AHCI_INTR_STATUS_CPDS                   ((uint32_t)0x1 << 31)
 182 #define AHCI_PORT_INTR_MASK                     0xfec000ff
 183
 184 /* port command and status bits */
 185 #define AHCI_CMD_STATUS_ST      (0x1 << 0) /* Start */
 186 #define AHCI_CMD_STATUS_SUD     (0x1 << 1) /* Spin-up device */
 187 #define AHCI_CMD_STATUS_POD     (0x1 << 2) /* Power on device */
 188 #define AHCI_CMD_STATUS_CLO     (0x1 << 3) /* Command list override */
 189 #define AHCI_CMD_STATUS_FRE     (0x1 << 4) /* FIS receive enable */
 190 #define AHCI_CMD_STATUS_CCS     (0x1f << 8) /* Current command slot */
 191                         /* Mechanical presence switch state */
 192 #define AHCI_CMD_STATUS_MPSS    (0x1 << 13)
 193 #define AHCI_CMD_STATUS_FR      (0x1 << 14) /* FIS receiving running */
 194 #define AHCI_CMD_STATUS_CR      (0x1 << 15) /* Command list running */
 195 #define AHCI_CMD_STATUS_CPS     (0x1 << 16) /* Cold presence state */
 196 #define AHCI_CMD_STATUS_PMA     (0x1 << 17) /* Port multiplier attached */
 197 #define AHCI_CMD_STATUS_HPCP    (0x1 << 18) /* Hot plug capable port */
 198                         /* Mechanical presence switch attached to port */
 199 #define AHCI_CMD_STATUS_MPSP    (0x1 << 19)
 200 #define AHCI_CMD_STATUS_CPD     (0x1 << 20) /* Cold presence detection */
 201 #define AHCI_CMD_STATUS_ESP     (0x1 << 21) /* External SATA port */
 202 #define AHCI_CMD_STATUS_ATAPI   (0x1 << 24) /* Device is ATAPI */
 203 #define AHCI_CMD_STATUS_DLAE    (0x1 << 25) /* Drive LED on ATAPI enable */
 204                         /* Aggressive link power magament enable */
 205 #define AHCI_CMD_STATUS_ALPE    (0x1 << 26)
 206 #define AHCI_CMD_STATUS_ASP     (0x1 << 27) /* Aggressive slumber/partial */
 207                         /* Interface communication control */
 208 #define AHCI_CMD_STATUS_ICC     (0xf << 28)
 209 #define AHCI_CMD_STATUS_CCS_SHIFT       8
 210 #define AHCI_CMD_STATUS_ICC_SHIFT       28
 211
 212 /* port task file data bits */
 213 #define AHCI_TFD_STS_MASK       0x000000ff
 214 #define AHCI_TFD_ERR_MASK       0x0000ff00
 215 #define AHCI_TFD_STS_BSY        (0x1 << 7)
 216 #define AHCI_TFD_STS_DRQ        (0x1 << 3)
 217 #define AHCI_TFD_STS_ERR        (0x1 << 0)
 218 #define AHCI_TFD_ERR_SHIFT      8
 219 #define AHCI_TFD_ERR_SGS        (0x1 << 0) /* DDR1: Send_good_status */
 220
 221 /* FIS-Based Switching Control Register */
 222 #define AHCI_FBS_SWE_MASK       (0xf << 16)     /* Device With Error */
 223 #define AHCI_FBS_ADO_MASK       (0xf << 12)     /* Active Device Optimization */
 224 #define AHCI_FBS_DEV_MASK       (0xf << 8)      /* Device To Issue */
 225 #define AHCI_FBS_SDE            (0x1 << 2)      /* Single Device Error */
 226 #define AHCI_FBS_DEC            (0x1 << 1)      /* Device Error Clear */
 227 #define AHCI_FBS_EN             (0x1 << 0)      /* Enable */
 228
 229 /* Sxxx Registers */
 230 #define AHCI_SERROR_CLEAR_ALL                   0xffffffff
 231 #define AHCI_SNOTIF_CLEAR_ALL                   0xffffffff
 232
 233 /* per port registers offset */
 234 #define AHCI_PORT_OFFSET(ahci_ctlp, port)                       \
 235                 (ahci_ctlp->ahcictl_ahci_addr + (0x100 + (port * 0x80)))
 236         /* Command List Base Address */
 237 #define AHCI_PORT_PxCLB(ahci_ctlp, port)                        \
 238                         (AHCI_PORT_OFFSET(ahci_ctlp, port) + 0x00)
 239         /* Command List Base Address Upper 32-Bits */
 240 #define AHCI_PORT_PxCLBU(ahci_ctlp, port)                       \
 241                         (AHCI_PORT_OFFSET(ahci_ctlp, port) + 0x04)
 242         /* FIS Base Address */
 243 #define AHCI_PORT_PxFB(ahci_ctlp, port)                         \
 244                         (AHCI_PORT_OFFSET(ahci_ctlp, port) + 0x08)
 245         /* FIS Base Address Upper 32-Bits */
 246 #define AHCI_PORT_PxFBU(ahci_ctlp, port)                        \
 247                         (AHCI_PORT_OFFSET(ahci_ctlp, port) + 0x0c)
 248         /* Interrupt Status */
 249 #define AHCI_PORT_PxIS(ahci_ctlp, port)                         \
 250                         (AHCI_PORT_OFFSET(ahci_ctlp, port) + 0x10)
 251         /* Interrupt Enable */
 252 #define AHCI_PORT_PxIE(ahci_ctlp, port)                         \
 253                         (AHCI_PORT_OFFSET(ahci_ctlp, port) + 0x14)
 254         /* Command and Status */
 255 #define AHCI_PORT_PxCMD(ahci_ctlp, port)                        \
 256                         (AHCI_PORT_OFFSET(ahci_ctlp, port) + 0x18)
 257         /* Task File Data */
 258 #define AHCI_PORT_PxTFD(ahci_ctlp, port)                        \
 259                         (AHCI_PORT_OFFSET(ahci_ctlp, port) + 0x20)
 260         /* Signature */
 261 #define AHCI_PORT_PxSIG(ahci_ctlp, port)                        \
 262                         (AHCI_PORT_OFFSET(ahci_ctlp, port) + 0x24)
 263         /* Serial ATA Status (SCR0:SStatus) */
 264 #define AHCI_PORT_PxSSTS(ahci_ctlp, port)                       \
 265                         (AHCI_PORT_OFFSET(ahci_ctlp, port) + 0x28)
 266         /* Serial ATA Control (SCR2:SControl) */
 267 #define AHCI_PORT_PxSCTL(ahci_ctlp, port)                       \
 268                         (AHCI_PORT_OFFSET(ahci_ctlp, port) + 0x2c)
 269         /* Serial ATA Error (SCR1:SError) */
 270 #define AHCI_PORT_PxSERR(ahci_ctlp, port)                       \
 271                         (AHCI_PORT_OFFSET(ahci_ctlp, port) + 0x30)
 272         /* Serial ATA Active (SCR3:SActive) */
 273 #define AHCI_PORT_PxSACT(ahci_ctlp, port)                       \
 274                         (AHCI_PORT_OFFSET(ahci_ctlp, port) + 0x34)
 275         /* Command Issue */
 276 #define AHCI_PORT_PxCI(ahci_ctlp, port)                         \
 277                         (AHCI_PORT_OFFSET(ahci_ctlp, port) + 0x38)
 278         /* SNotification */
 279 #define AHCI_PORT_PxSNTF(ahci_ctlp, port)                       \
 280                         (AHCI_PORT_OFFSET(ahci_ctlp, port) + 0x3c)
 281         /* FIS-Based Switching Control */
 282 #define AHCI_PORT_PxFBS(ahci_ctlp, port)                        \
 283                         (AHCI_PORT_OFFSET(ahci_ctlp, port) + 0x40)
 284
 285 #define AHCI_SLOT_MASK(ahci_ctlp)                               \
 286         ((ahci_ctlp->ahcictl_num_cmd_slots == AHCI_PORT_MAX_CMD_SLOTS) ? \
 287         0xffffffff : ((0x1 << ahci_ctlp->ahcictl_num_cmd_slots) - 1))
 288 #define AHCI_NCQ_SLOT_MASK(ahci_portp)                          \
 289         ((ahci_portp->ahciport_max_ncq_tags == AHCI_PORT_MAX_CMD_SLOTS) ? \
 290         0xffffffff : ((0x1 << ahci_portp->ahciport_max_ncq_tags) - 1))
 291 #define AHCI_PMPORT_MASK(ahci_portp)                            \
 292         ((0x1 << ahci_portp->ahciport_pmult_info->ahcipmi_num_dev_ports) - 1)
 293
 294 /* Device signatures */
 295 #define AHCI_SIGNATURE_PORT_MULTIPLIER  0x96690101
 296 #define AHCI_SIGNATURE_ATAPI            0xeb140101
 297 #define AHCI_SIGNATURE_DISK             0x00000101
 298
 299 #define AHCI_H2D_REGISTER_FIS_TYPE      0x27
 300 #define AHCI_H2D_REGISTER_FIS_LENGTH    5
 301
 302 #define AHCI_CMDHEAD_ATAPI      0x1 /* set to 1 for ATAPI command */
 303 #define AHCI_CMDHEAD_DATA_WRITE 0x1 /* From system memory to device */
 304 #define AHCI_CMDHEAD_DATA_READ  0x0 /* From device to system memory */
 305 #define AHCI_CMDHEAD_PREFETCHABLE       0x1 /* if set, HBA prefetch PRDs */
 306
 307 /* Register - Host to Device FIS (from SATA spec) */
 308 typedef struct ahci_fis_h2d_register {
 309         /* offset 0x00 */
 310         uint32_t        ahcifhr_type_pmp_rsvd_cmddevctl_cmd_features;
 311
 312 #define SET_FIS_TYPE(fis, type)                                 \
 313         (fis->ahcifhr_type_pmp_rsvd_cmddevctl_cmd_features |= (type & 0xff))
 314
 315 #define SET_FIS_PMP(fis, pmp)                                   \
 316         (fis->ahcifhr_type_pmp_rsvd_cmddevctl_cmd_features |=   \
 317                 ((pmp & 0xf) << 8))
 318
 319 #define SET_FIS_CDMDEVCTL(fis, cmddevctl)                       \
 320         (fis->ahcifhr_type_pmp_rsvd_cmddevctl_cmd_features |=   \
 321                 ((cmddevctl & 0x1) << 15))
 322
 323 #define GET_FIS_COMMAND(fis)                                    \
 324         ((fis->ahcifhr_type_pmp_rsvd_cmddevctl_cmd_features >> 16) & 0xff)
 325
 326 #define SET_FIS_COMMAND(fis, command)                           \
 327         (fis->ahcifhr_type_pmp_rsvd_cmddevctl_cmd_features |=   \
 328                 ((command & 0xff) << 16))
 329
 330 #define GET_FIS_FEATURES(fis)                                   \
 331         ((fis->ahcifhr_type_pmp_rsvd_cmddevctl_cmd_features >> 24) & 0xff)
 332
 333 #define SET_FIS_FEATURES(fis, features)                         \
 334         (fis->ahcifhr_type_pmp_rsvd_cmddevctl_cmd_features |=   \
 335                 ((features & 0xff) << 24))
 336
 337         /* offset 0x04 */
 338         uint32_t        ahcifhr_sector_cyllow_cylhi_devhead;
 339
 340 #define GET_FIS_SECTOR(fis)                                     \
 341         (fis->ahcifhr_sector_cyllow_cylhi_devhead & 0xff)
 342
 343 #define SET_FIS_SECTOR(fis, sector)                             \
 344         (fis->ahcifhr_sector_cyllow_cylhi_devhead |= ((sector & 0xff)))
 345
 346 #define GET_FIS_CYL_LOW(fis)                                    \
 347         ((fis->ahcifhr_sector_cyllow_cylhi_devhead >> 8) & 0xff)
 348
 349 #define SET_FIS_CYL_LOW(fis, cyl_low)                           \
 350         (fis->ahcifhr_sector_cyllow_cylhi_devhead |= ((cyl_low & 0xff) << 8))
 351
 352 #define GET_FIS_CYL_HI(fis)                                     \
 353         ((fis->ahcifhr_sector_cyllow_cylhi_devhead >> 16) & 0xff)
 354
 355 #define SET_FIS_CYL_HI(fis, cyl_hi)                             \
 356         (fis->ahcifhr_sector_cyllow_cylhi_devhead |= ((cyl_hi & 0xff) << 16))
 357
 358 #define GET_FIS_DEV_HEAD(fis)                                   \
 359         ((fis->ahcifhr_sector_cyllow_cylhi_devhead >> 24) & 0xff)
 360
 361 #define SET_FIS_DEV_HEAD(fis, dev_head)                         \
 362         (fis->ahcifhr_sector_cyllow_cylhi_devhead |= ((dev_head & 0xff) << 24))
 363
 364         /* offset 0x08 */
 365         uint32_t        ahcifhr_sectexp_cyllowexp_cylhiexp_featuresexp;
 366
 367 #define GET_FIS_SECTOR_EXP(fis)                                 \
 368         (fis->ahcifhr_sectexp_cyllowexp_cylhiexp_featuresexp  & 0xff)
 369
 370 #define SET_FIS_SECTOR_EXP(fis, sectorexp)                      \
 371         (fis->ahcifhr_sectexp_cyllowexp_cylhiexp_featuresexp |= \
 372                 ((sectorexp & 0xff)))
 373
 374 #define GET_FIS_CYL_LOW_EXP(fis)                                \
 375         ((fis->ahcifhr_sectexp_cyllowexp_cylhiexp_featuresexp >> 8) & 0xff)
 376
 377 #define SET_FIS_CYL_LOW_EXP(fis, cyllowexp)                     \
 378         (fis->ahcifhr_sectexp_cyllowexp_cylhiexp_featuresexp |= \
 379                 ((cyllowexp & 0xff) << 8))
 380
 381 #define GET_FIS_CYL_HI_EXP(fis)                                 \
 382         ((fis->ahcifhr_sectexp_cyllowexp_cylhiexp_featuresexp >> 16) & 0xff)
 383
 384 #define SET_FIS_CYL_HI_EXP(fis, cylhiexp)                       \
 385         (fis->ahcifhr_sectexp_cyllowexp_cylhiexp_featuresexp |= \
 386                 ((cylhiexp & 0xff) << 16))
 387
 388 #define SET_FIS_FEATURES_EXP(fis, features_exp)                 \
 389         (fis->ahcifhr_sectexp_cyllowexp_cylhiexp_featuresexp |= \
 390                 ((features_exp & 0xff) << 24))
 391
 392         /* offset 0x0c */
 393         uint32_t        ahcifhr_sectcount_sectcountexp_rsvd_devctl;
 394
 395 #define GET_FIS_SECTOR_COUNT(fis)                               \
 396         (fis->ahcifhr_sectcount_sectcountexp_rsvd_devctl & 0xff)
 397
 398 #define SET_FIS_SECTOR_COUNT(fis, sector_count)                 \
 399         (fis->ahcifhr_sectcount_sectcountexp_rsvd_devctl |=     \
 400                 ((sector_count & 0xff)))
 401
 402 #define GET_FIS_SECTOR_COUNT_EXP(fis)                           \
 403         ((fis->ahcifhr_sectcount_sectcountexp_rsvd_devctl >> 8) & 0xff)
 404
 405 #define SET_FIS_SECTOR_COUNT_EXP(fis, sector_count_exp)         \
 406         (fis->ahcifhr_sectcount_sectcountexp_rsvd_devctl |=     \
 407                 ((sector_count_exp & 0xff) << 8))
 408
 409 #define SET_FIS_DEVCTL(fis, devctl)                             \
 410         (fis->ahcifhr_sectcount_sectcountexp_rsvd_devctl |=     \
 411                 ((devctl & 0xff) << 24))
 412
 413         /* offset 0x10 */
 414         uint32_t        ahcifhr_rsvd3[1]; /* should be zero */
 415 } ahci_fis_h2d_register_t;
 416
 417 /* Register - Device to Host FIS (from SATA spec) */
 418 typedef struct ahci_fis_d2h_register {
 419         /* offset 0x00 */
 420         uint32_t        ahcifdr_type_intr_rsvd_status_error;
 421
 422 #define GET_RFIS_STATUS(fis)                                    \
 423         ((fis->ahcifdr_type_intr_rsvd_status_error >> 16) & 0xff)
 424
 425 #define GET_RFIS_ERROR(fis)                                     \
 426         ((fis->ahcifdr_type_intr_rsvd_status_error >> 24) & 0xff)
 427
 428         /* offset 0x04 */
 429         uint32_t        ahcifdr_sector_cyllow_cylhi_devhead;
 430
 431 #define GET_RFIS_CYL_LOW(fis)                                   \
 432         (fis->ahcifdr_sector_cyllow_cylhi_devhead & 0xff)
 433
 434 #define GET_RFIS_CYL_MID(fis)                                   \
 435         ((fis->ahcifdr_sector_cyllow_cylhi_devhead >> 8) & 0xff)
 436
 437 #define GET_RFIS_CYL_HI(fis)                                    \
 438         ((fis->ahcifdr_sector_cyllow_cylhi_devhead >> 16) & 0xff)
 439
 440 #define GET_RFIS_DEV_HEAD(fis)                                  \
 441         ((fis->ahcifdr_sector_cyllow_cylhi_devhead >> 24) & 0xff)
 442
 443         /* offset 0x08 */
 444         uint32_t        ahcifdr_sectexp_cyllowexp_cylhiexp_rsvd;
 445
 446 #define GET_RFIS_CYL_LOW_EXP(fis)                                       \
 447         (fis->ahcifdr_sectexp_cyllowexp_cylhiexp_rsvd  & 0xff)
 448
 449 #define GET_RFIS_CYL_MID_EXP(fis)                               \
 450         ((fis->ahcifdr_sectexp_cyllowexp_cylhiexp_rsvd >> 8) & 0xff)
 451
 452 #define GET_RFIS_CYL_HI_EXP(fis)                                        \
 453         ((fis->ahcifdr_sectexp_cyllowexp_cylhiexp_rsvd >> 16) & 0xff)
 454
 455         /* offset 0x0c */
 456         uint32_t        ahcifdr_sectcount_sectcountexp_rsvd;
 457
 458 #define GET_RFIS_SECTOR_COUNT(fis)                              \
 459         (fis->ahcifdr_sectcount_sectcountexp_rsvd & 0xff)
 460
 461 #define GET_RFIS_SECTOR_COUNT_EXP(fis)                          \
 462         ((fis->ahcifdr_sectcount_sectcountexp_rsvd >> 8) & 0xff)
 463
 464         /* offset 0x10 */
 465         uint32_t        ahcifdr_rsvd;
 466 } ahci_fis_d2h_register_t;
 467
 468 /* Set Device Bits - Device to Host FIS (from SATA spec) */
 469 typedef struct ahci_fis_set_device_bits {
 470         /* offset 0x00 */
 471         uint32_t        ahcifsdb_type_rsvd_intr_status_error;
 472
 473 #define GET_N_BIT_OF_SET_DEV_BITS(fis)                          \
 474         ((fis->ahcifsdb_type_rsvd_intr_status_error >> 15) & 0x1)
 475
 476         /* offset 0x04 */
 477         uint32_t        ahcifsdb_rsvd;
 478 } ahci_fis_set_device_bits_t;
 479
 480 /* DMA Setup - Device to Host or Host to Device (from SATA spec) */
 481 typedef struct ahci_fis_dma_setup {
 482         /* offset 0x00 */
 483         uint32_t        ahcifds_type_rsvd_direction_intr_rsvd;
 484
 485         /* offset 0x04 */
 486         uint32_t        ahcifds_dma_buffer_identifier_low;
 487
 488         /* offset 0x08 */
 489         uint32_t        ahcifds_dma_buffer_identifier_high;
 490
 491         /* offset 0x0c */
 492         uint32_t        ahcifds_rsvd1;
 493
 494         /* offset 0x10 */
 495         uint32_t        ahcifds_dma_buffer_offset;
 496
 497         /* offset 0x14 */
 498         uint32_t        ahcifds_dma_transfer_count;
 499
 500         /* offset 0x18 */
 501         uint32_t        ahcifds_rsvd2;
 502 } ahci_fis_dma_setup_t;
 503
 504 /* PIO Setup - Device to Host FIS (from SATA spec) */
 505 typedef struct ahci_fis_pio_setup {
 506         /* offset 0x00 */
 507         uint32_t        ahcifps_type_rsvd_direction_intr_status_error;
 508
 509         /* offset 0x04 */
 510         uint32_t        ahcifps_sector_cyllow_cylhi_devhead;
 511
 512         /* offset 0x08 */
 513         uint32_t        ahcifps_sectexp_cyllowexp_cylhiexp_rsvd;
 514
 515         /* offset 0x0c */
 516         uint32_t        ahcifps_sectcount_sectcountexp_rsvd_e_status;
 517
 518         /* offset 0x10 */
 519         uint32_t        ahcifps_transfer_count_rsvd;
 520 } ahci_fis_pio_setup_t;
 521
 522 /* BIST Active - Host to Device or Device to Host (from SATA spec) */
 523 typedef struct ahci_fis_bist_active {
 524         /* offset 0x00 */
 525         uint32_t        ahcifba_type_rsvd_pattern_rsvd;
 526
 527         /* offset 0x04 */
 528         uint32_t        ahcifba_data1;
 529
 530         /* offset 0x08 */
 531         uint32_t        ahcifba_data2;
 532 } ahci_fis_bist_active_t;
 533
 534 /* Up to 64 bytes */
 535 typedef struct ahci_fis_unknown {
 536         uint32_t        ahcifu_first_dword;
 537         uint32_t        ahcifu_dword[15];
 538 } ahci_fis_unknown_t;
 539
 540 /*
 541  * This is a software constructed FIS. For data transfer,
 542  * this is the H2D Register FIS format as specified in
 543  * the Serial ATA 1.0a specification. Valid Command FIS
 544  * length are 2 to 16 Dwords.
 545  */
 546 typedef struct ahci_fis_command {
 547         union {
 548                 ahci_fis_h2d_register_t ahcifc_h2d_register;
 549                 ahci_fis_bist_active_t  ahcifc_bist_active;
 550         } ahcifc_fis;
 551         uint32_t        ahcifc_rsvd3[11]; /* should be zero */
 552 } ahci_fis_command_t;
 553
 554 /* Received FISes structure - size 100h */
 555 typedef struct ahci_rcvd_fis {
 556         /* offset 0x00 - DMA Setup FIS */
 557         ahci_fis_dma_setup_t            ahcirf_dma_setup_fis;
 558         uint32_t                        ahcirf_fis_rsvd1;
 559
 560         /* offset 0x20 - PIO Setup FIS */
 561         ahci_fis_pio_setup_t            ahcirf_pio_setup_fis;
 562         uint32_t                        ahcirf_fis_rsvd2[3];
 563
 564         /* offset 0x40 - D2H Register FIS */
 565         ahci_fis_d2h_register_t         ahcirf_d2h_register_fis;
 566         uint32_t                        ahcirf_fis_rsvd3;
 567
 568         /* offset 0x58 - Set Device Bits FIS */
 569         ahci_fis_set_device_bits_t      ahcirf_set_device_bits_fis;
 570
 571         /* offset 0x60 - Unknown FIS */
 572         ahci_fis_unknown_t              ahcirf_unknown_fis;
 573
 574         /* offset 0xa0h - Reserved */
 575         uint32_t                        ahcirf_fis_rsvd4[24];
 576 } ahci_rcvd_fis_t;
 577
 578 /* physical region description table (PRDT) item structure */
 579 typedef struct ahci_prdt_item {
 580         /* DW 0 - Data Base Address */
 581         uint32_t        ahcipi_data_base_addr;
 582
 583         /* DW 1 - Data Base Address Upper */
 584         uint32_t        ahcipi_data_base_addr_upper;
 585
 586         /* DW 2 - Reserved */
 587         uint32_t        ahcipi_rsvd;
 588
 589         /* DW 3 - Description Information */
 590         uint32_t        ahcipi_descr_info;
 591
 592 #define GET_PRDT_ITEM_INTR_ON_COMPLETION(prdt_item)     \
 593                 ((prdt_item.ahcipi_descr_info >> 31) & 0x01)
 594
 595 #define GET_PRDT_ITEM_DATA_BYTE_COUNT(prdt_item)        \
 596                 (prdt_item.ahcipi_descr_info & 0x3fffff)
 597
 598 } ahci_prdt_item_t;
 599
 600 /* command table structure */
 601 typedef struct ahci_cmd_table {
 602         /* offset 0x00 - Command FIS */
 603         ahci_fis_command_t      ahcict_command_fis;
 604
 605         /* offset 0x40 - ATAPI Command */
 606         uint8_t                 ahcict_atapi_cmd[SATA_ATAPI_MAX_CDB_LEN];
 607
 608         /* offset 0x50 - Reserved */
 609         uint32_t                ahcict_rsvd[12];
 610
 611         /* offset 0x80 - Physical Region Description Table */
 612         ahci_prdt_item_t        ahcict_prdt[AHCI_PRDT_NUMBER];
 613 } ahci_cmd_table_t;
 614
 615 /* command head structure - size 20h */
 616 typedef struct ahci_cmd_header {
 617         /* DW 0 - Description Information */
 618         uint32_t        ahcich_descr_info;
 619
 620 #define BZERO_DESCR_INFO(cmd_header)                            \
 621         (cmd_header->ahcich_descr_info = 0)
 622
 623 #define GET_PRD_TABLE_LENGTH(cmd_header)                        \
 624                 ((cmd_header->ahcich_descr_info >> 16) & 0xffff)
 625
 626 #define SET_PRD_TABLE_LENGTH(cmd_header, length)                \
 627         (cmd_header->ahcich_descr_info |= ((length & 0xffff) << 16))
 628
 629 #define GET_PORT_MULTI_PORT(cmd_header)                         \
 630                 ((cmd_header->ahcich_descr_info >> 12) & 0x0f)
 631
 632 #define SET_PORT_MULTI_PORT(cmd_header, flags)                  \
 633         (cmd_header->ahcich_descr_info |= ((flags & 0x0f) << 12))
 634
 635 #define GET_CLEAR_BUSY_UPON_R_OK(cmd_header)                    \
 636                 ((cmd_header->ahcich_descr_info >> 10) & 0x01)
 637
 638 #define SET_CLEAR_BUSY_UPON_R_OK(cmd_header, flags)             \
 639         (cmd_header->ahcich_descr_info |= ((flags & 0x01) << 10))
 640
 641 #define GET_BIST(cmd_header)                                    \
 642                 ((cmd_header->ahcich_descr_info >> 9) & 0x01)
 643
 644 #define GET_RESET(cmd_header)                                   \
 645                 ((cmd_header->ahcich_descr_info >> 8) & 0x01)
 646
 647 #define SET_RESET(cmd_header, features_exp)                     \
 648         (cmd_header->ahcich_descr_info |= ((features_exp & 0x01) << 8))
 649
 650 #define GET_PREFETCHABLE(cmd_header)                            \
 651                 ((cmd_header->ahcich_descr_info >> 7) & 0x01)
 652
 653 #define SET_PREFETCHABLE(cmd_header, flags)                     \
 654         (cmd_header->ahcich_descr_info |= ((flags & 0x01) << 7))
 655
 656 #define GET_WRITE(cmd_header)                                   \
 657                 ((cmd_header->ahcich_descr_info >> 6) & 0x01)
 658
 659 #define SET_WRITE(cmd_header, flags)                            \
 660         (cmd_header->ahcich_descr_info |= ((flags & 0x01) << 6))
 661
 662 #define GET_ATAPI(cmd_header)                                   \
 663                 ((cmd_header->ahcich_descr_info >> 5) & 0x01)
 664
 665 #define SET_ATAPI(cmd_header, flags)                            \
 666         (cmd_header->ahcich_descr_info |= ((flags & 0x01) << 5))
 667
 668 #define GET_COMMAND_FIS_LENGTH(cmd_header)                      \
 669                 (cmd_header->ahcich_descr_info && 0x1f)
 670
 671 #define SET_COMMAND_FIS_LENGTH(cmd_header, length)              \
 672         (cmd_header->ahcich_descr_info |= (length & 0x1f))
 673
 674         /* DW 1 - Physical Region Descriptor Byte Count */
 675         uint32_t        ahcich_prd_byte_count;
 676
 677 #define BZERO_PRD_BYTE_COUNT(cmd_header)                        \
 678         (cmd_header->ahcich_prd_byte_count = 0)
 679
 680         /* DW 2 - Command Table Base Address */
 681         uint32_t        ahcich_cmd_tab_base_addr;
 682
 683 #define SET_COMMAND_TABLE_BASE_ADDR(cmd_header, base_address)   \
 684         (cmd_header->ahcich_cmd_tab_base_addr = base_address)
 685
 686         /* DW 3 - Command Table Base Address Upper */
 687         uint32_t        ahcich_cmd_tab_base_addr_upper;
 688
 689 #define SET_COMMAND_TABLE_BASE_ADDR_UPPER(cmd_header, base_address) \
 690         (cmd_header->ahcich_cmd_tab_base_addr_upper = base_address)
 691
 692         /* DW 4-7 - Reserved */
 693         uint32_t        ahcich_rsvd[4];
 694 } ahci_cmd_header_t;
 695
 696
 697 #ifdef  __cplusplus
 698 }
 699 #endif
 700
 701 #endif /* _AHCIREG_H */