usr/src/uts/common/sys/asy.h

   1 /*
   2  * CDDL HEADER START
   3  *
   4  * The contents of this file are subject to the terms of the
   5  * Common Development and Distribution License (the "License").
   6  * You may not use this file except in compliance with the License.
   7  *
   8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
   9  * or http://www.opensolaris.org/os/licensing.
  10  * See the License for the specific language governing permissions
  11  * and limitations under the License.
  12  *
  13  * When distributing Covered Code, include this CDDL HEADER in each
  14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
  15  * If applicable, add the following below this CDDL HEADER, with the
  16  * fields enclosed by brackets "[]" replaced with your own identifying
  17  * information: Portions Copyright [yyyy] [name of copyright owner]
  18  *
  19  * CDDL HEADER END
  20  */
  21 /*      Copyright (c) 1990, 1991 UNIX System Laboratories, Inc. */
  22 /*      Copyright (c) 1984, 1986, 1987, 1988, 1989, 1990 AT&T   */
  23 /*        All Rights Reserved   */
  24
  25 /*
  26  * Copyright (c) 1992, 2010, Oracle and/or its affiliates. All rights reserved.
  27  */
  28
  29 #ifndef _SYS_ASY_H
  30 #define _SYS_ASY_H
  31
  32 #ifdef __cplusplus
  33 extern "C" {
  34 #endif
  35
  36 #include <sys/tty.h>
  37 #include <sys/ksynch.h>
  38 #include <sys/dditypes.h>
  39
  40 /*
  41  * internal bus type naming
  42  */
  43 #define ASY_BUS_PCI     (0)
  44 #define ASY_BUS_ISA     (1)
  45 #define ASY_BUS_UNKNOWN (-1)
  46
  47 #define ASY_MINOR_LEN   (40)
  48
  49 #define COM1_IOADDR     0x3f8
  50 #define COM2_IOADDR     0x2f8
  51 #define COM3_IOADDR     0x3e8
  52 #define COM4_IOADDR     0x2e8
  53
  54 /*
  55  * Definitions for INS8250 / 16550  chips
  56  */
  57
  58 /* defined as offsets from the data register */
  59 #define DAT             0       /* receive/transmit data */
  60 #define ICR             1       /* interrupt control register */
  61 #define ISR             2       /* interrupt status register */
  62 #define LCR             3       /* line control register */
  63 #define MCR             4       /* modem control register */
  64 #define LSR             5       /* line status register */
  65 #define MSR             6       /* modem status register */
  66 #define SCR             7       /* scratch register */
  67 #define DLL             0       /* divisor latch (lsb) */
  68 #define DLH             1       /* divisor latch (msb) */
  69 #define FIFOR           ISR     /* FIFO register for 16550 */
  70 #define EFR             ISR     /* Enhanced feature register for 16650 */
  71
  72 /*
  73  * INTEL 8210-A/B & 16450/16550 Registers Structure.
  74  */
  75
  76 /* Line Control Register */
  77 #define WLS0            0x01    /* word length select bit 0 */
  78 #define WLS1            0x02    /* word length select bit 2 */
  79 #define STB             0x04    /* number of stop bits */
  80 #define PEN             0x08    /* parity enable */
  81 #define EPS             0x10    /* even parity select */
  82 #define SETBREAK        0x40    /* break key */
  83 #define DLAB            0x80    /* divisor latch access bit */
  84 #define RXLEN           0x03    /* # of data bits per received/xmitted char */
  85 #define STOP1           0x00
  86 #define STOP2           0x04
  87 #define PAREN           0x08
  88 #define PAREVN          0x10
  89 #define PARMARK         0x20
  90 #define SNDBRK          0x40
  91 #define EFRACCESS       0xBF    /* magic value for 16650 EFR access */
  92
  93 #define BITS5           0x00    /* 5 bits per char */
  94 #define BITS6           0x01    /* 6 bits per char */
  95 #define BITS7           0x02    /* 7 bits per char */
  96 #define BITS8           0x03    /* 8 bits per char */
  97
  98 /* Line Status Register */
  99 #define RCA             0x01    /* data ready */
 100 #define OVRRUN          0x02    /* overrun error */
 101 #define PARERR          0x04    /* parity error */
 102 #define FRMERR          0x08    /* framing error */
 103 #define BRKDET          0x10    /* a break has arrived */
 104 #define XHRE            0x20    /* tx hold reg is now empty */
 105 #define XSRE            0x40    /* tx shift reg is now empty */
 106 #define RFBE            0x80    /* rx FIFO Buffer error */
 107
 108 /* Interrupt Id Regisger */
 109 #define MSTATUS         0x00    /* modem status changed */
 110 #define NOINTERRUPT     0x01    /* no interrupt pending */
 111 #define TxRDY           0x02    /* Transmitter Holding Register Empty */
 112 #define RxRDY           0x04    /* Receiver Data Available */
 113 #define FFTMOUT         0x0c    /* FIFO timeout - 16550AF */
 114 #define RSTATUS         0x06    /* Receiver Line Status */
 115
 116 /* Interrupt Enable Register */
 117 #define RIEN            0x01    /* Received Data Ready */
 118 #define TIEN            0x02    /* Tx Hold Register Empty */
 119 #define SIEN            0x04    /* Receiver Line Status */
 120 #define MIEN            0x08    /* Modem Status */
 121
 122 /* Modem Control Register */
 123 #define DTR             0x01    /* Data Terminal Ready */
 124 #define RTS             0x02    /* Request To Send */
 125 #define OUT1            0x04    /* Aux output - not used */
 126 #define OUT2            0x08    /* turns intr to 386 on/off */
 127 #define ASY_LOOP        0x10    /* loopback for diagnostics */
 128
 129 /* Modem Status Register */
 130 #define DCTS            0x01    /* Delta Clear To Send */
 131 #define DDSR            0x02    /* Delta Data Set Ready */
 132 #define DRI             0x04    /* Trail Edge Ring Indicator */
 133 #define DDCD            0x08    /* Delta Data Carrier Detect */
 134 #define CTS             0x10    /* Clear To Send */
 135 #define DSR             0x20    /* Data Set Ready */
 136 #define RI              0x40    /* Ring Indicator */
 137 #define DCD             0x80    /* Data Carrier Detect */
 138
 139 #define DELTAS(x)       ((x)&(DCTS|DDSR|DRI|DDCD))
 140 #define STATES(x)       ((x)&(CTS|DSR|RI|DCD))
 141
 142 /* flags for FCR (FIFO Control register) */
 143 #define FIFO_OFF        0x00    /* fifo disabled */
 144 #define FIFO_ON         0x01    /* fifo enabled */
 145 #define FIFORXFLSH      0x02    /* flush receiver FIFO */
 146 #define FIFOTXFLSH      0x04    /* flush transmitter FIFO */
 147 #define FIFODMA         0x08    /* DMA mode 1 */
 148 #define FIFOEXTRA1      0x10    /* Longer fifos on some 16650's */
 149 #define FIFOEXTRA2      0x20    /* Longer fifos on some 16650's and 16750 */
 150 #define FIFO_TRIG_1     0x00    /* 1 byte trigger level */
 151 #define FIFO_TRIG_4     0x40    /* 4 byte trigger level */
 152 #define FIFO_TRIG_8     0x80    /* 8 byte trigger level */
 153 #define FIFO_TRIG_14    0xC0    /* 14 byte trigger level */
 154
 155 /* Serial in/out requests */
 156
 157 #define OVERRUN         040000
 158 #define FRERROR         020000
 159 #define PERROR          010000
 160 #define S_ERRORS        (PERROR|OVERRUN|FRERROR)
 161
 162 /* EFR - Enhanced feature register for 16650 */
 163 #define ENHENABLE       0x10
 164
 165 /* SCR - scratch register */
 166 #define SCRTEST         0x5a    /* arbritrary value for testing SCR register */
 167
 168 /*
 169  * Ring buffer and async line management definitions.
 170  */
 171 #define RINGBITS        16              /* # of bits in ring ptrs */
 172 #define RINGSIZE        (1<<RINGBITS)   /* size of ring */
 173 #define RINGMASK        (RINGSIZE-1)
 174 #define RINGFRAC        12              /* fraction of ring to force flush */
 175
 176 #define RING_INIT(ap)  ((ap)->async_rput = (ap)->async_rget = 0)
 177 #define RING_CNT(ap)   (((ap)->async_rput >= (ap)->async_rget) ? \
 178         ((ap)->async_rput - (ap)->async_rget):\
 179         ((0x10000 - (ap)->async_rget) + (ap)->async_rput))
 180 #define RING_FRAC(ap)  ((int)RING_CNT(ap) >= (int)(RINGSIZE/RINGFRAC))
 181 #define RING_POK(ap, n) ((int)RING_CNT(ap) < (int)(RINGSIZE-(n)))
 182 #define RING_PUT(ap, c) \
 183         ((ap)->async_ring[(ap)->async_rput++ & RINGMASK] =  (uchar_t)(c))
 184 #define RING_UNPUT(ap) ((ap)->async_rput--)
 185 #define RING_GOK(ap, n) ((int)RING_CNT(ap) >= (int)(n))
 186 #define RING_GET(ap)   ((ap)->async_ring[(ap)->async_rget++ & RINGMASK])
 187 #define RING_EAT(ap, n) ((ap)->async_rget += (n))
 188 #define RING_MARK(ap, c, s) \
 189         ((ap)->async_ring[(ap)->async_rput++ & RINGMASK] = ((uchar_t)(c)|(s)))
 190 #define RING_UNMARK(ap) \
 191         ((ap)->async_ring[((ap)->async_rget) & RINGMASK] &= ~S_ERRORS)
 192 #define RING_ERR(ap, c) \
 193         ((ap)->async_ring[((ap)->async_rget) & RINGMASK] & (c))
 194
 195 /*
 196  * Asy tracing macros.  These are a bit similar to some macros in sys/vtrace.h .
 197  *
 198  * XXX - Needs review:  would it be better to use the macros in sys/vtrace.h ?
 199  */
 200 #ifdef DEBUG
 201 #define DEBUGWARN0(fac, format) \
 202         if (debug & (fac)) \
 203                 cmn_err(CE_WARN, format)
 204 #define DEBUGNOTE0(fac, format) \
 205         if (debug & (fac)) \
 206                 cmn_err(CE_NOTE, format)
 207 #define DEBUGNOTE1(fac, format, arg1) \
 208         if (debug & (fac)) \
 209                 cmn_err(CE_NOTE, format, arg1)
 210 #define DEBUGNOTE2(fac, format, arg1, arg2) \
 211         if (debug & (fac)) \
 212                 cmn_err(CE_NOTE, format, arg1, arg2)
 213 #define DEBUGNOTE3(fac, format, arg1, arg2, arg3) \
 214         if (debug & (fac)) \
 215                 cmn_err(CE_NOTE, format, arg1, arg2, arg3)
 216 #define DEBUGCONT0(fac, format) \
 217         if (debug & (fac)) \
 218                 cmn_err(CE_CONT, format)
 219 #define DEBUGCONT1(fac, format, arg1) \
 220         if (debug & (fac)) \
 221                 cmn_err(CE_CONT, format, arg1)
 222 #define DEBUGCONT2(fac, format, arg1, arg2) \
 223         if (debug & (fac)) \
 224                 cmn_err(CE_CONT, format, arg1, arg2)
 225 #define DEBUGCONT3(fac, format, arg1, arg2, arg3) \
 226         if (debug & (fac)) \
 227                 cmn_err(CE_CONT, format, arg1, arg2, arg3)
 228 #define DEBUGCONT4(fac, format, arg1, arg2, arg3, arg4) \
 229         if (debug & (fac)) \
 230                 cmn_err(CE_CONT, format, arg1, arg2, arg3, arg4)
 231 #define DEBUGCONT10(fac, format, \
 232         arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8, arg9, arg10) \
 233         if (debug & (fac)) \
 234                 cmn_err(CE_CONT, format, \
 235                 arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8, arg9, arg10)
 236 #else
 237 #define DEBUGWARN0(fac, format)
 238 #define DEBUGNOTE0(fac, format)
 239 #define DEBUGNOTE1(fac, format, arg1)
 240 #define DEBUGNOTE2(fac, format, arg1, arg2)
 241 #define DEBUGNOTE3(fac, format, arg1, arg2, arg3)
 242 #define DEBUGCONT0(fac, format)
 243 #define DEBUGCONT1(fac, format, arg1)
 244 #define DEBUGCONT2(fac, format, arg1, arg2)
 245 #define DEBUGCONT3(fac, format, arg1, arg2, arg3)
 246 #define DEBUGCONT4(fac, format, arg1, arg2, arg3, arg4)
 247 #define DEBUGCONT10(fac, format, \
 248         arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8, arg9, arg10)
 249 #endif
 250
 251 /*
 252  * Hardware channel common data. One structure per port.
 253  * Each of the fields in this structure is required to be protected by a
 254  * mutex lock at the highest priority at which it can be altered.
 255  * The asy_flags, and asy_next fields can be altered by interrupt
 256  * handling code that must be protected by the mutex whose handle is
 257  * stored in asy_excl_hi.  All others can be protected by the asy_excl
 258  * mutex, which is lower priority and adaptive.
 259  */
 260
 261 struct asycom {
 262         int             asy_flags;      /* random flags  */
 263                                         /* protected by asy_excl_hi lock */
 264         uint_t          asy_hwtype;     /* HW type: ASY16550A, etc. */
 265         uint_t          asy_use_fifo;   /* HW FIFO use it or not ?? */
 266         uint_t          asy_fifo_buf;   /* With FIFO = 16, otherwise = 1 */
 267         uint_t          asy_flags2;     /* flags which don't change, no lock */
 268         uint8_t         *asy_ioaddr;    /* i/o address of ASY port */
 269         struct asyncline *asy_priv;     /* protocol private data -- asyncline */
 270         dev_info_t      *asy_dip;       /* dev_info */
 271         int             asy_unit;       /* which port */
 272         ddi_iblock_cookie_t asy_iblock;
 273         kmutex_t        asy_excl;       /* asy adaptive mutex */
 274         kmutex_t        asy_excl_hi;    /* asy spinlock mutex */
 275         kmutex_t        asy_soft_lock;  /* soft lock for guarding softpend. */
 276         int             asysoftpend;    /* Flag indicating soft int pending. */
 277         ddi_softintr_t  asy_softintr_id;
 278         ddi_iblock_cookie_t asy_soft_iblock;
 279
 280         /*
 281          * The asy_soft_sr mutex should only be taken by the soft interrupt
 282          * handler and the driver DDI_SUSPEND/DDI_RESUME code.  It
 283          * shouldn't be taken by any code that may get called indirectly
 284          * by the soft interrupt handler (e.g. as a result of a put or
 285          * putnext call).
 286          */
 287         kmutex_t        asy_soft_sr;    /* soft int suspend/resume mutex */
 288         uchar_t         asy_msr;        /* saved modem status */
 289         uchar_t         asy_mcr;        /* soft carrier bits */
 290         uchar_t         asy_lcr;        /* console lcr bits */
 291         uchar_t         asy_bidx;       /* console baud rate index */
 292         tcflag_t        asy_cflag;      /* console mode bits */
 293         struct cons_polledio    polledio;       /* polled I/O functions */
 294         ddi_acc_handle_t        asy_iohandle;   /* Data access handle */
 295         tcflag_t        asy_ocflag;     /* old console mode bits */
 296         uchar_t         asy_com_port;   /* COM port number, or zero */
 297         uchar_t         asy_fifor;      /* FIFOR register setting */
 298 #ifdef DEBUG
 299         int             asy_msint_cnt;  /* number of times in async_msint */
 300 #endif
 301 };
 302
 303 /*
 304  * Asychronous protocol private data structure for ASY.
 305  * Each of the fields in the structure is required to be protected by
 306  * the lower priority lock except the fields that are set only at
 307  * base level but cleared (with out lock) at interrupt level.
 308  */
 309
 310 struct asyncline {
 311         int             async_flags;    /* random flags */
 312         kcondvar_t      async_flags_cv; /* condition variable for flags */
 313         kcondvar_t      async_ops_cv;   /* condition variable for async_ops */
 314         dev_t           async_dev;      /* device major/minor numbers */
 315         mblk_t          *async_xmitblk; /* transmit: active msg block */
 316         struct asycom   *async_common;  /* device common data */
 317         tty_common_t    async_ttycommon; /* tty driver common data */
 318         bufcall_id_t    async_wbufcid;  /* id for pending write-side bufcall */
 319         size_t          async_wbufcds;  /* Buffer size requested in bufcall */
 320         timeout_id_t    async_polltid;  /* softint poll timeout id */
 321         timeout_id_t    async_dtrtid;   /* delaying DTR turn on */
 322         timeout_id_t    async_utbrktid; /* hold minimum untimed break time id */
 323
 324         /*
 325          * The following fields are protected by the asy_excl_hi lock.
 326          * Some, such as async_flowc, are set only at the base level and
 327          * cleared (without the lock) only by the interrupt level.
 328          */
 329         uchar_t         *async_optr;    /* output pointer */
 330         int             async_ocnt;     /* output count */
 331         uint_t          async_rput;     /* producing pointer for input */
 332         uint_t          async_rget;     /* consuming pointer for input */
 333
 334         /*
 335          * Each character stuffed into the ring has two bytes associated
 336          * with it.  The first byte is used to indicate special conditions
 337          * and the second byte is the actual data.  The ring buffer
 338          * needs to be defined as ushort_t to accomodate this.
 339          */
 340         ushort_t        async_ring[RINGSIZE];
 341
 342         short           async_break;    /* break count */
 343         int             async_inflow_source; /* input flow control type */
 344
 345         union {
 346                 struct {
 347                         uchar_t _hw;    /* overrun (hw) */
 348                         uchar_t _sw;    /* overrun (sw) */
 349                 } _a;
 350                 ushort_t uover_overrun;
 351         } async_uover;
 352 #define async_overrun           async_uover._a.uover_overrun
 353 #define async_hw_overrun        async_uover._a._hw
 354 #define async_sw_overrun        async_uover._a._sw
 355         short           async_ext;      /* modem status change count */
 356         short           async_work;     /* work to do flag */
 357         timeout_id_t    async_timer;    /* close drain progress timer */
 358
 359         mblk_t          *async_suspqf;  /* front of suspend queue */
 360         mblk_t          *async_suspqb;  /* back of suspend queue */
 361         int             async_ops;      /* active operations counter */
 362 };
 363
 364 /* definitions for async_flags field */
 365 #define ASYNC_EXCL_OPEN  0x10000000     /* exclusive open */
 366 #define ASYNC_WOPEN      0x00000001     /* waiting for open to complete */
 367 #define ASYNC_ISOPEN     0x00000002     /* open is complete */
 368 #define ASYNC_OUT        0x00000004     /* line being used for dialout */
 369 #define ASYNC_CARR_ON    0x00000008     /* carrier on last time we looked */
 370 #define ASYNC_STOPPED    0x00000010     /* output is stopped */
 371 #define ASYNC_DELAY      0x00000020     /* waiting for delay to finish */
 372 #define ASYNC_BREAK      0x00000040     /* waiting for break to finish */
 373 #define ASYNC_BUSY       0x00000080     /* waiting for transmission to finish */
 374 #define ASYNC_DRAINING   0x00000100     /* waiting for output to drain */
 375 #define ASYNC_SERVICEIMM 0x00000200     /* queue soft interrupt as soon as */
 376 #define ASYNC_HW_IN_FLOW 0x00000400     /* input flow control in effect */
 377 #define ASYNC_HW_OUT_FLW 0x00000800     /* output flow control in effect */
 378 #define ASYNC_PROGRESS   0x00001000     /* made progress on output effort */
 379 #define ASYNC_CLOSING    0x00002000     /* processing close on stream */
 380 #define ASYNC_OUT_SUSPEND 0x00004000    /* waiting for TIOCSBRK to finish */
 381 #define ASYNC_HOLD_UTBRK 0x00008000     /* waiting for untimed break hold */
 382                                         /* the minimum time */
 383 #define ASYNC_DTR_DELAY  0x00010000     /* delaying DTR turn on */
 384 #define ASYNC_SW_IN_FLOW 0x00020000     /* sw input flow control in effect */
 385 #define ASYNC_SW_OUT_FLW 0x00040000     /* sw output flow control in effect */
 386 #define ASYNC_SW_IN_NEEDED 0x00080000   /* sw input flow control char is */
 387                                         /* needed to be sent */
 388 #define ASYNC_OUT_FLW_RESUME 0x00100000 /* output need to be resumed */
 389                                         /* because of transition of flow */
 390                                         /* control from stop to start */
 391 #define ASYNC_DDI_SUSPENDED  0x00200000 /* suspended by DDI */
 392 #define ASYNC_RESUME_BUFCALL 0x00400000 /* call bufcall when resumed by DDI */
 393
 394 /* asy_hwtype definitions */
 395 #define ASY8250A        0x2             /* 8250A or 16450 */
 396 #define ASY16550        0x3             /* broken FIFO which must not be used */
 397 #define ASY16550A       0x4             /* usable FIFO */
 398 #define ASY16650        0x5
 399 #define ASY16750        0x6
 400
 401 /* definitions for asy_flags field */
 402 #define ASY_NEEDSOFT    0x00000001
 403 #define ASY_DOINGSOFT   0x00000002
 404 #define ASY_PPS         0x00000004
 405 #define ASY_PPS_EDGE    0x00000008
 406 #define ASY_DOINGSOFT_RETRY     0x00000010
 407 #define ASY_RTS_DTR_OFF 0x00000020
 408 #define ASY_IGNORE_CD   0x00000040
 409 #define ASY_CONSOLE     0x00000080
 410 #define ASY_DDI_SUSPENDED       0x00000100 /* suspended by DDI */
 411
 412 /* definitions for asy_flags2 field */
 413 #define ASY2_NO_LOOPBACK 0x00000001     /* Device doesn't support loopback */
 414
 415 /* definitions for async_inflow_source field in struct asyncline */
 416 #define IN_FLOW_NULL    0x00000000
 417 #define IN_FLOW_RINGBUFF        0x00000001
 418 #define IN_FLOW_STREAMS 0x00000002
 419 #define IN_FLOW_USER    0x00000004
 420
 421 /*
 422  * OUTLINE defines the high-order flag bit in the minor device number that
 423  * controls use of a tty line for dialin and dialout simultaneously.
 424  */
 425 #ifdef _LP64
 426 #define OUTLINE         (1 << (NBITSMINOR32 - 1))
 427 #else
 428 #define OUTLINE         (1 << (NBITSMINOR - 1))
 429 #endif
 430 #define UNIT(x)         (getminor(x) & ~OUTLINE)
 431
 432 /*
 433  * ASYSETSOFT macro to pend a soft interrupt if one isn't already pending.
 434  */
 435
 436 #define ASYSETSOFT(asy) {                       \
 437         if (mutex_tryenter(&asy->asy_soft_lock)) {      \
 438                 asy->asy_flags |= ASY_NEEDSOFT;         \
 439                 if (!asy->asysoftpend) {                \
 440                         asy->asysoftpend = 1;           \
 441                         mutex_exit(&asy->asy_soft_lock);        \
 442                         ddi_trigger_softintr(asy->asy_softintr_id);     \
 443                 }                                       \
 444                 else                                    \
 445                         mutex_exit(&asy->asy_soft_lock);        \
 446         }                                                       \
 447 }
 448
 449 #ifdef __cplusplus
 450 }
 451 #endif
 452
 453 #endif  /* _SYS_ASY_H */