include/sys/i8272A.h

   1 /*
   2  * CDDL HEADER START
   3  *
   4  * The contents of this file are subject to the terms of the
   5  * Common Development and Distribution License, Version 1.0 only
   6  * (the "License").  You may not use this file except in compliance
   7  * with the License.
   8  *
   9  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
  10  * or http://www.opensolaris.org/os/licensing.
  11  * See the License for the specific language governing permissions
  12  * and limitations under the License.
  13  *
  14  * When distributing Covered Code, include this CDDL HEADER in each
  15  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
  16  * If applicable, add the following below this CDDL HEADER, with the
  17  * fields enclosed by brackets "[]" replaced with your own identifying
  18  * information: Portions Copyright [yyyy] [name of copyright owner]
  19  *
  20  * CDDL HEADER END
  21  */
  22 /*
  23  * Copyright (c) 1995 by Sun Microsystems, Inc.
  24  * All rights reserved.
  25  */
  26
  27 #ifndef _SYS_I8272A_H
  28 #define _SYS_I8272A_H
  29
  30 #pragma ident   "%Z%%M% %I%     %E% SMI"
  31
  32 #ifdef  __cplusplus
  33 extern "C" {
  34 #endif
  35
  36 /*
  37  * i/o port numbers
  38  */
  39 #define FCR_BASE        0x3f0   /* default i/o base address */
  40
  41 #define FCR_SRA         0x000   /* only 82077AA (not AT mode) or SMC */
  42 #define FCR_SRB         0x001   /* only 82077AA (not AT mode) or SMC */
  43 #define FCR_DOR         0x002
  44 #define FCR_MSR         0x004
  45 #define FCR_DSR         0x004   /* only enhanced controllers */
  46 #define FCR_DATA        0x005
  47 #define FCR_DIR         0x007
  48 #define FCR_CCR         0x007   /* 82077AA term; == DSR on PC/AT */
  49
  50 /*  SRA : values for Configuration Select Register for SMC FDC37C66xGT */
  51 #define FSA_ENA5        0x55    /*  enable config mode, issue twice */
  52 #define FSA_ENA6        0x44    /*  enable config mode, issue twice */
  53 #define FSA_DISB        0xAA    /*  disable config mode */
  54 #define FSA_CR5         0x05    /*  select config register 5 */
  55
  56 /*  SRB : Configuration Data Register for SMC FDC37C66xGT */
  57 #define FSB_DSDEF       0xE7    /*  bit mask for density select in reg 5 */
  58 #define FSB_DSLO        0x10    /*  density select = LOW (300 rpm) */
  59 #define FSB_DSHI        0x18    /*  density select = HIGH (360 rpm) */
  60
  61 /*  DOR : Digital Output Register */
  62 #define FD_DMTREN       0xF0
  63 #define FD_D3MTR        0x80
  64 #define FD_D2MTR        0x40
  65 #define FD_DBMTR        0x20
  66 #define FD_DAMTR        0x10
  67 #define FD_ENABLE       0x08    /* DMA gate */
  68 #define FD_RSETZ        0x04
  69 #define FD_DRSEL        0x03
  70 #define FD_DBSEL        0x01
  71 #define FD_DASEL        0x00
  72
  73 #define ENAB_MCA_INT    0x00
  74
  75
  76 /* MSR - Main Status Register */
  77 #define MS_RQM          0x80    /* request for master - chip needs attention */
  78 #define MS_DIO          0x40    /* data in/out, 1 = remove bytes from fifo */
  79 #define MS_NDM          0x20    /* non-dma mode - 1 during execution phase */
  80 #define MS_CB           0x10    /* controller busy, command in progress */
  81 #define MS_D3B          0x08    /* drive 3 busy */
  82 #define MS_D2B          0x04    /* drive 2 busy */
  83 #define MS_DBB          0x02    /* drive B busy */
  84 #define MS_DAB          0x01    /* drive A busy */
  85
  86 #define FDC_RQM_RETRY   300
  87
  88
  89 /*  DIR : Digital Input Register */
  90 #define FDI_DKCHG       0x80    /* this is inverted in Model 30 mode */
  91 #define FDI_DMAGAT      0x08    /* Model 30: DMA gate */
  92 #define FDI_NOPREC      0x04    /* Model 30 only */
  93 #define FDI_DRATE       0x03    /* Model 30: selected datarate mask */
  94
  95
  96 /*  DSR : Datarate Select Register on 82072 and 82077AA */
  97 #define FSR_SWR         0x80    /* software reset */
  98 #define FSR_PD          0x40    /* power down */
  99 #define FSR_PRECP       0x1C    /* precomp mask */
 100 #define FSR_DRATE       0x3     /* datarate select mask */
 101
 102
 103 /*  CCR : Configuration Control Register, aka Datarate Select Register */
 104 #define FCC_NOPREC      0x4     /* Model 30 only */
 105 #define FCC_DRATE       0x3     /* datarate select mask */
 106
 107
 108 /*
 109  * Floppy controller command opcodes
 110  */
 111 #define FO_MODE         0x01    /* National PC8477 types only */
 112 #define FO_RDTRK        0x02
 113 #define FO_SPEC         0x03
 114 #define FO_SDRV         0x04    /* read status register 3 */
 115 #define FO_WRDAT        0x05
 116 #define FO_RDDAT        0x06
 117 #define FO_RECAL        0x07
 118 #define FO_SINT         0x08
 119 #define FO_WRDEL        0x09
 120 #define FO_RDID         0x0A
 121 #define FO_RDDEL        0x0C
 122 #define FO_FRMT         0x0D
 123 #define FO_SEEK         0x0F
 124 #define FO_VRSN         0x10    /* get version */
 125 #define FO_PERP         0x12    /* perpendicular mode */
 126 #define FO_CNFG         0x13    /* configure */
 127 #define FO_NSC          0x18    /* identify National chip */
 128
 129                                 /* option bits */
 130 #define FO_MT           0x80    /* multi-track operation */
 131 #define FO_MFM          0x40    /* double & high density disks */
 132 #define FO_FM           0x00    /* single density disks */
 133 #define FO_SK           0x20    /* skip deleted adr mark */
 134
 135
 136 #define S0_ICMASK       0xC0    /* status register 0 */
 137 #define S0_XRDY         0xC0
 138 #define S0_IVCMD        0x80
 139 #define S0_ABTERM       0x40
 140 #define S0_SEKEND       0x20
 141 #define S0_ECHK         0x10
 142 #define S0_NOTRDY       0x08
 143
 144 #define S1_EOCYL        0x80    /* status register 1 */
 145 #define S1_CRCER        0x20
 146 #define S1_OVRUN        0x10
 147 #define S1_NODATA       0x04
 148 #define S1_MADMK        0x01
 149
 150 #define S3_FAULT        0x80    /* status register 3 */
 151 #define S3_WPROT        0x40
 152 #define S3_DRRDY        0x20
 153 #define S3_TRK0         0x10
 154 #define S3_2SIDE        0x08
 155 #define S3_HEAD         0x04
 156 #define S3_UNIT         0x03
 157
 158
 159 /*
 160  * controller chip values
 161  */
 162 #define i8272A          0x8272
 163 #define uPD72064        0x72064         /* NEC */
 164 /* enhanced floppy controllers */
 165 #define i82077          0x82077
 166 #define PC87322         0x87322         /* National Semiconducter */
 167 #define FDC37C665       0x37c665        /* SMC */
 168 #define FDC37C666       0x37c666        /* SMC */
 169
 170 #ifdef  __cplusplus
 171 }
 172 #endif
 173
 174 #endif  /* !_SYS_I8272A_H */