usr/src/uts/common/io/pic.c

   1 /*
   2  * CDDL HEADER START
   3  *
   4  * The contents of this file are subject to the terms of the
   5  * Common Development and Distribution License, Version 1.0 only
   6  * (the "License").  You may not use this file except in compliance
   7  * with the License.
   8  *
   9  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
  10  * or http://www.opensolaris.org/os/licensing.
  11  * See the License for the specific language governing permissions
  12  * and limitations under the License.
  13  *
  14  * When distributing Covered Code, include this CDDL HEADER in each
  15  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
  16  * If applicable, add the following below this CDDL HEADER, with the
  17  * fields enclosed by brackets "[]" replaced with your own identifying
  18  * information: Portions Copyright [yyyy] [name of copyright owner]
  19  *
  20  * CDDL HEADER END
  21  */
  22 /*
  23  * Copyright 1999 Sun Microsystems, Inc.  All rights reserved.
  24  * Use is subject to license terms.
  25  */
  26
  27 /*      Copyright (c) 1990, 1991 UNIX System Laboratories, Inc. */
  28 /*      Copyright (c) 1984, 1986, 1987, 1988, 1989, 1990 AT&T   */
  29 /*        All Rights Reserved   */
  30
  31 #pragma ident   "%Z%%M% %I%     %E% SMI"
  32
  33 #include <sys/types.h>
  34 #include <sys/pic.h>
  35 #include <sys/sunddi.h>
  36
  37 void
  38 picsetup()
  39 {
  40         /* initialize master first                              */
  41         /* ICW1: Edge-triggered, Cascaded, need ICW4    */
  42         (void) outb(MCMD_PORT, PIC_ICW1BASE|PIC_NEEDICW4);
  43
  44         /* ICW2: start master vectors at PIC_VECTBASE           */
  45         (void) outb(MIMR_PORT, PIC_VECTBASE);
  46
  47         /* ICW3: define which lines are connected to slaves     */
  48         (void) outb(MIMR_PORT, 1 << MASTERLINE);
  49
  50         /* ICW4: buffered master (?), norm eoi, mcs 86          */
  51         (void) outb(MIMR_PORT, PIC_86MODE);
  52
  53         /* OCW1: Start the master with all interrupts off       */
  54         (void) outb(MIMR_PORT, 0xFF);
  55
  56         /* OCW3: set master into "read isr mode"                */
  57         (void) outb(MCMD_PORT, PIC_READISR);
  58
  59         /* initialize the slave                                 */
  60         /* ICW1: Edge-triggered, Cascaded, need ICW4    */
  61         (void) outb(SCMD_PORT, PIC_ICW1BASE|PIC_NEEDICW4);
  62
  63         /* ICW2: set base of vectors                            */
  64         outb(SIMR_PORT, PIC_VECTBASE +  8);
  65
  66         /* ICW3: specify ID for this slave                      */
  67         outb(SIMR_PORT, MASTERLINE);
  68
  69         /* ICW4: buffered slave (?), norm eoi, mcs 86           */
  70         outb(SIMR_PORT, PIC_86MODE);
  71
  72         /* OCW1: set interrupt mask                             */
  73         outb(SIMR_PORT, 0xff);
  74
  75         /* OCW3: set pic into "read isr mode"                   */
  76         outb(SCMD_PORT, PIC_READISR);
  77 }