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Merge commit '4ec4134be29a3b00791f6d70074168a6a3ff4fb3'
[unleashed.git] / kernel / comstar / port / qlt / qlt.h
bloba9e6019062263036706e5315ec0a2df383cb3126
1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright 2009 QLogic Corporation. All rights reserved.
24 * Use is subject to license terms.
25 */
26
27 /*
28 * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved.
29 */
30
31 #ifndef _QLT_H
32 #define _QLT_H
33
34 #include <sys/stmf_defines.h>
35 #include "qlt_regs.h"
36
37 #ifdef __cplusplus
38 extern "C" {
39 #endif
40
41 /*
42 * Qlogic logging
43 */
44 extern int enable_extended_logging;
45
46 /*
47 * Caution: 1) LOG will be available in debug/non-debug mode
48 * 2) Anything which can potentially flood the log should be under
49 * extended logging, and use QLT_EXT_LOG.
50 * 3) Don't use QLT_EXT_LOG in performance-critical code path, such
51 * as normal SCSI I/O code path. It could hurt system performance.
52 * 4) Use kmdb to change enable_extened_logging in the fly to adjust
53 * tracing
54 */
55 #define QLT_EXT_LOG(log_ident, ...) \
56 if (enable_extended_logging) { \
57 stmf_trace(log_ident, __VA_ARGS__); \
58 }
59
60 #define QLT_LOG(log_ident, ...) \
61 stmf_trace(log_ident, __VA_ARGS__)
62
63 /*
64 * Error codes. FSC stands for Failure sub code.
65 */
66 #define QLT_FAILURE FCT_FCA_FAILURE
67 #define QLT_SUCCESS FCT_SUCCESS
68 #define QLT_FSC(x) ((uint64_t)(x) << 40)
69 #define QLT_DMA_STUCK (QLT_FAILURE | QLT_FSC(1))
70 #define QLT_MAILBOX_STUCK (QLT_FAILURE | QLT_FSC(2))
71 #define QLT_ROM_STUCK (QLT_FAILURE | QLT_FSC(3))
72 #define QLT_UNEXPECTED_RESPONSE (QLT_FAILURE | QLT_FSC(4))
73 #define QLT_MBOX_FAILED (QLT_FAILURE | QLT_FSC(5))
74 #define QLT_MBOX_NOT_INITIALIZED (QLT_FAILURE | QLT_FSC(6))
75 #define QLT_MBOX_BUSY (QLT_FAILURE | QLT_FSC(7))
76 #define QLT_MBOX_ABORTED (QLT_FAILURE | QLT_FSC(8))
77 #define QLT_MBOX_TIMEOUT (QLT_FAILURE | QLT_FSC(9))
78 #define QLT_RESP_TIMEOUT (QLT_FAILURE | QLT_FSC(10))
79 #define QLT_FLASH_TIMEOUT (QLT_FAILURE | QLT_FSC(11))
80 #define QLT_FLASH_ACCESS_ERROR (QLT_FAILURE | QLT_FSC(12))
81 #define QLT_BAD_NVRAM_DATA (QLT_FAILURE | QLT_FSC(13))
82 #define QLT_FIRMWARE_ERROR_CODE (QLT_FAILURE | QLT_FSC(14))
83
84 #define QLT_FIRMWARE_ERROR(s, c1, c2) (QLT_FIRMWARE_ERROR_CODE | \
85 (((uint64_t)s) << 32) | (((uint64_t)c1) << 24) | ((uint64_t)c2))
86
87 extern uint32_t fw2400_code01[];
88 extern uint32_t fw2400_length01;
89 extern uint32_t fw2400_addr01;
90 extern uint32_t fw2400_code02[];
91 extern uint32_t fw2400_length02;
92 extern uint32_t fw2400_addr02;
93
94 extern uint32_t fw2500_code01[];
95 extern uint32_t fw2500_length01;
96 extern uint32_t fw2500_addr01;
97 extern uint32_t fw2500_code02[];
98 extern uint32_t fw2500_length02;
99 extern uint32_t fw2500_addr02;
100
101 extern uint32_t fw8100_code01[];
102 extern uint32_t fw8100_length01;
103 extern uint32_t fw8100_addr01;
104 extern uint32_t fw8100_code02[];
105 extern uint32_t fw8100_length02;
106 extern uint32_t fw8100_addr02;
107
108 typedef enum {
109 MBOX_STATE_UNKNOWN = 0,
110 MBOX_STATE_READY,
111 MBOX_STATE_CMD_RUNNING,
112 MBOX_STATE_CMD_DONE
113 } mbox_state_t;
114
115 /*
116 * ISP mailbox commands
117 */
118 #define MBC_LOAD_RAM 0x01 /* Load RAM. */
119 #define MBC_EXECUTE_FIRMWARE 0x02 /* Execute firmware. */
120 #define MBC_DUMP_RAM 0x03 /* Dump RAM. */
121 #define MBC_WRITE_RAM_WORD 0x04 /* Write RAM word. */
122 #define MBC_READ_RAM_WORD 0x05 /* Read RAM word. */
123 #define MBC_MAILBOX_REGISTER_TEST 0x06 /* Wrap incoming mailboxes */
124 #define MBC_VERIFY_CHECKSUM 0x07 /* Verify checksum. */
125 #define MBC_ABOUT_FIRMWARE 0x08 /* About Firmware. */
126 #define MBC_DUMP_RISC_RAM 0x0a /* Dump RISC RAM command. */
127 #define MBC_LOAD_RAM_EXTENDED 0x0b /* Load RAM extended. */
128 #define MBC_DUMP_RAM_EXTENDED 0x0c /* Dump RAM extended. */
129 #define MBC_WRITE_RAM_EXTENDED 0x0d /* Write RAM word. */
130 #define MBC_READ_RAM_EXTENDED 0x0f /* Read RAM extended. */
131 #define MBC_SERDES_TRANSMIT_PARAMETERS 0x10 /* Serdes Xmit Parameters */
132 #define MBC_2300_EXECUTE_IOCB 0x12 /* ISP2300 Execute IOCB cmd */
133 #define MBC_GET_IO_STATUS 0x12 /* ISP2422 Get I/O Status */
134 #define MBC_STOP_FIRMWARE 0x14 /* Stop firmware */
135 #define MBC_ABORT_COMMAND_IOCB 0x15 /* Abort IOCB command. */
136 #define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN). */
137 #define MBC_ABORT_TARGET 0x17 /* Abort target (ID). */
138 #define MBC_RESET 0x18 /* Target reset. */
139 #define MBC_XMIT_PARM 0x19 /* Change default xmit parms */
140 #define MBC_PORT_PARAM 0x1a /* Get/set port speed parms */
141 #define MBC_GET_ID 0x20 /* Get loop id of ISP2200. */
142 #define MBC_GET_TIMEOUT_PARAMETERS 0x22 /* Get Timeout Parameters. */
143 #define MBC_TRACE_CONTROL 0x27 /* Trace control. */
144 #define MBC_GET_FIRMWARE_OPTIONS 0x28 /* Get firmware options */
145 #define MBC_READ_SFP 0x31 /* Read SFP. */
146
147 #define MBC_SET_ADDITIONAL_FIRMWARE_OPT 0x38 /* set firmware options */
148
149 #define OPT_PUREX_ENABLE (BIT_10)
150
151 #define MBC_RESET_MENLO 0x3a /* Reset Menlo. */
152 #define MBC_RESTART_MPI 0x3d /* Restart MPI. */
153 #define MBC_FLASH_ACCESS 0x3e /* Flash Access Control */
154 #define MBC_LOOP_PORT_BYPASS 0x40 /* Loop Port Bypass. */
155 #define MBC_LOOP_PORT_ENABLE 0x41 /* Loop Port Enable. */
156 #define MBC_GET_RESOURCE_COUNTS 0x42 /* Get Resource Counts. */
157 #define MBC_NON_PARTICIPATE 0x43 /* Non-Participating Mode. */
158 #define MBC_ECHO 0x44 /* ELS ECHO */
159 #define MBC_DIAGNOSTIC_LOOP_BACK 0x45 /* Diagnostic loop back. */
160 #define MBC_ONLINE_SELF_TEST 0x46 /* Online self-test. */
161 #define MBC_ENHANCED_GET_PORT_DATABASE 0x47 /* Get Port Database + login */
162 #define MBC_INITIALIZE_MULTI_ID_FW 0x48 /* Initialize multi-id fw */
163 #define MBC_GET_DCBX_PARAMS 0x51 /* Get DCBX parameters */
164 #define MBC_RESET_LINK_STATUS 0x52 /* Reset Link Error Status */
165 #define MBC_EXECUTE_IOCB 0x54 /* 64 Bit Execute IOCB cmd. */
166 #define MBC_SEND_RNID_ELS 0x57 /* Send RNID ELS request */
167
168 #define MBC_SET_PARAMETERS 0x59 /* Set parameters */
169
170 #define RNID_PARAMS_DF_FMT 0x00
171 #define RNID_PARAMS_E0_FMT 0x01
172 #define PUREX_ELS_CMDS 0x05
173 #define FLOGI_PARAMS 0x06
174
175 #define PARAM_TYPE_FIELD_MASK 0xff
176 #define PARAM_TYPE_FIELD_SHIFT 8
177 #define PARAM_TYPE(type) ((type & PARAM_TYPE_FIELD_MASK) << \
178 PARAM_TYPE_FIELD_SHIFT)
179
180 #define MBC_GET_PARAMETERS 0x5a /* Get RNID parameters */
181 #define MBC_DATA_RATE 0x5d /* Data Rate */
182 #define MBC_INITIALIZE_FIRMWARE 0x60 /* Initialize firmware */
183 #define MBC_INITIATE_LIP 0x62 /* Initiate LIP */
184 #define MBC_GET_FC_AL_POSITION_MAP 0x63 /* Get FC_AL Position Map. */
185 #define MBC_GET_PORT_DATABASE 0x64 /* Get Port Database. */
186 #define MBC_CLEAR_ACA 0x65 /* Clear ACA. */
187 #define MBC_TARGET_RESET 0x66 /* Target Reset. */
188 #define MBC_CLEAR_TASK_SET 0x67 /* Clear Task Set. */
189 #define MBC_ABORT_TASK_SET 0x68 /* Abort Task Set. */
190 #define MBC_GET_FIRMWARE_STATE 0x69 /* Get firmware state. */
191 #define MBC_GET_PORT_NAME 0x6a /* Get port name. */
192 #define MBC_GET_LINK_STATUS 0x6b /* Get Link Status. */
193 #define MBC_LIP_RESET 0x6c /* LIP reset. */
194 #define MBC_GET_STATUS_COUNTS 0x6d /* Get Link Statistics and */
195 /* Private Data Counts */
196 #define MBC_SEND_SNS_COMMAND 0x6e /* Send Simple Name Server */
197 #define MBC_LOGIN_FABRIC_PORT 0x6f /* Login fabric port. */
198 #define MBC_SEND_CHANGE_REQUEST 0x70 /* Send Change Request. */
199 #define MBC_LOGOUT_FABRIC_PORT 0x71 /* Logout fabric port. */
200 #define MBC_LIP_FULL_LOGIN 0x72 /* Full login LIP. */
201 #define MBC_LOGIN_LOOP_PORT 0x74 /* Login Loop Port. */
202 #define MBC_PORT_NODE_NAME_LIST 0x75 /* Get port/node name list */
203 #define MBC_INITIALIZE_IP 0x77 /* Initialize IP */
204 #define MBC_SEND_FARP_REQ_COMMAND 0x78 /* FARP request. */
205 #define MBC_UNLOAD_IP 0x79 /* Unload IP */
206 #define MBC_GET_XGMAC_STATS 0x7a /* Get XGMAC Statistics. */
207 #define MBC_GET_ID_LIST 0x7c /* Get port ID list. */
208 #define MBC_SEND_LFA_COMMAND 0x7d /* Send Loop Fabric Address */
209 #define MBC_LUN_RESET 0x7e /* Send Task mgmt LUN reset */
210 #define MBC_IDC_REQUEST 0x100 /* IDC request */
211 #define MBC_IDC_ACK 0x101 /* IDC acknowledge */
212 #define MBC_IDC_TIME_EXTEND 0x102 /* IDC extend time */
213 #define MBC_PORT_RESET 0x120 /* Port Reset */
214 #define MBC_SET_PORT_CONFIG 0x122 /* Set port configuration */
215 #define MBC_GET_PORT_CONFIG 0x123 /* Get port configuration */
216
217 #define IOCB_SIZE 64
218
219 /*
220 * These should not be constents but should be obtained from fw.
221 */
222 #define QLT_MAX_LOGINS 2048
223 #define QLT_MAX_XCHGES 2048
224
225 #define MAX_MBOXES 32
226 #define MBOX_TIMEOUT (2*1000*1000)
227 #define DEREG_RP_TIMEOUT (2*1000*1000)
228
229 typedef struct {
230 uint16_t to_fw[MAX_MBOXES];
231 uint32_t to_fw_mask;
232 uint16_t from_fw[MAX_MBOXES];
233 uint32_t from_fw_mask;
234 stmf_data_buf_t *dbuf;
235 } mbox_cmd_t;
236
237 typedef struct qlt_abts_cmd {
238 uint8_t buf[IOCB_SIZE];
239 } qlt_abts_cmd_t;
240
241 struct qlt_dmem_bucket;
242 struct qlt_ddi_dma_handle_pool;
243
244 #define QLT_INTR_FIXED 0x1
245 #define QLT_INTR_MSI 0x2
246 #define QLT_INTR_MSIX 0x4
247
248 typedef struct qlt_el_trace_desc {
249 kmutex_t mutex;
250 uint16_t next;
251 uint32_t trace_buffer_size;
252 char *trace_buffer;
253 } qlt_el_trace_desc_t;
254
255 typedef struct qlt_state {
256 dev_info_t *dip;
257 char qlt_minor_name[16];
258 char qlt_port_alias[16];
259 fct_local_port_t *qlt_port;
260 struct qlt_dmem_bucket **dmem_buckets;
261
262 struct qlt_dma_handle_pool
263 *qlt_dma_handle_pool;
264
265 int instance;
266 uint8_t qlt_state:7,
267 qlt_state_not_acked:1;
268 uint8_t qlt_intr_enabled:1,
269 qlt_25xx_chip:1,
270 qlt_stay_offline:1,
271 qlt_link_up,
272 qlt_81xx_chip:1,
273 qlt_rsvd1:3;
274 uint8_t cur_topology;
275
276 /* Registers */
277 caddr_t regs;
278 ddi_acc_handle_t regs_acc_handle;
279 ddi_acc_handle_t pcicfg_acc_handle;
280
281 /* Interrupt stuff */
282 kmutex_t intr_lock; /* Only used by intr routine */
283 int intr_sneak_counter;
284 ddi_intr_handle_t *htable;
285 int intr_size;
286 int intr_cnt;
287 uint_t intr_pri;
288 int intr_cap;
289 int intr_flags;
290
291 /* Queues */
292 ddi_dma_handle_t queue_mem_dma_handle;
293 ddi_acc_handle_t queue_mem_acc_handle;
294 caddr_t queue_mem_ptr;
295 ddi_dma_cookie_t queue_mem_cookie;
296
297 kmutex_t req_lock;
298 caddr_t req_ptr;
299 uint32_t req_ndx_to_fw;
300 uint32_t req_ndx_from_fw;
301 uint32_t req_available;
302
303 caddr_t resp_ptr;
304 uint32_t resp_ndx_to_fw;
305 uint32_t resp_ndx_from_fw;
306
307 kmutex_t preq_lock;
308 caddr_t preq_ptr;
309 uint32_t preq_ndx_to_fw;
310 uint32_t preq_ndx_from_fw;
311
312 kcondvar_t rp_dereg_cv; /* for deregister cmd */
313 uint32_t rp_id_in_dereg; /* remote port in deregistering */
314 fct_status_t rp_dereg_status;
315
316 caddr_t atio_ptr;
317 uint16_t atio_ndx_to_fw;
318 uint16_t atio_ndx_from_fw;
319
320 kmutex_t dma_mem_lock;
321
322 /* MailBox data */
323 kmutex_t mbox_lock;
324 kcondvar_t mbox_cv;
325 mbox_state_t mbox_io_state;
326 mbox_cmd_t *mcp;
327 qlt_nvram_t *nvram;
328
329 uint8_t link_speed; /* Cached from intr routine */
330 uint16_t fw_major;
331 uint16_t fw_minor;
332 uint16_t fw_subminor;
333 uint16_t fw_endaddrlo;
334 uint16_t fw_endaddrhi;
335 uint16_t fw_attr;
336
337 uint32_t fw_addr01;
338 uint32_t fw_length01;
339 uint32_t *fw_code01;
340 uint32_t fw_addr02;
341 uint32_t fw_length02;
342 uint32_t *fw_code02;
343
344 uint32_t qlt_ioctl_flags;
345 kmutex_t qlt_ioctl_lock;
346 caddr_t qlt_fwdump_buf; /* FWDUMP will use ioctl flags/lock */
347 uint32_t qlt_change_state_flags; /* Cached for ACK handling */
348
349 qlt_el_trace_desc_t *el_trace_desc;
350
351 /* temp ref & stat counters */
352 uint32_t qlt_bucketcnt[5]; /* element 0 = 2k */
353 uint64_t qlt_bufref[5]; /* element 0 = 2k */
354 uint64_t qlt_bumpbucket; /* bigger buffer supplied */
355 uint64_t qlt_pmintry;
356 uint64_t qlt_pmin_ok;
357 } qlt_state_t;
358
359 /*
360 * FWDUMP flags (part of IOCTL flags)
361 */
362 #define QLT_FWDUMP_INPROGRESS 0x0100 /* if it's dumping now */
363 #define QLT_FWDUMP_TRIGGERED_BY_USER 0x0200 /* if users triggered it */
364 #define QLT_FWDUMP_FETCHED_BY_USER 0x0400 /* if users have viewed it */
365 #define QLT_FWDUMP_ISVALID 0x0800
366
367 /*
368 * IOCTL supporting stuff
369 */
370 #define QLT_IOCTL_FLAG_MASK 0xFF
371 #define QLT_IOCTL_FLAG_IDLE 0x00
372 #define QLT_IOCTL_FLAG_OPEN 0x01
373 #define QLT_IOCTL_FLAG_EXCL 0x02
374
375 typedef struct qlt_cmd {
376 stmf_data_buf_t *dbuf; /* dbuf with handle 0 for SCSI cmds */
377 stmf_data_buf_t *dbuf_rsp_iu; /* dbuf for possible FCP_RSP IU */
378 uint32_t fw_xchg_addr;
379 uint16_t flags;
380 union {
381 uint16_t resp_offset;
382 uint8_t atio_byte3;
383 } param;
384 } qlt_cmd_t;
385
386 /*
387 * cmd flags
388 */
389 #define QLT_CMD_ABORTING 1
390 #define QLT_CMD_ABORTED 2
391 #define QLT_CMD_TYPE_SOLICITED 4
392
393 typedef struct {
394 int dummy;
395 } qlt_remote_port_t;
396
397 #define REQUEST_QUEUE_ENTRIES 2048
398 #define RESPONSE_QUEUE_ENTRIES 2048
399 #define ATIO_QUEUE_ENTRIES 2048
400 #define PRIORITY_QUEUE_ENTRIES 128
401
402 #define REQUEST_QUEUE_OFFSET 0
403 #define RESPONSE_QUEUE_OFFSET (REQUEST_QUEUE_OFFSET + \
404 (REQUEST_QUEUE_ENTRIES * IOCB_SIZE))
405 #define ATIO_QUEUE_OFFSET (RESPONSE_QUEUE_OFFSET + \
406 (RESPONSE_QUEUE_ENTRIES * IOCB_SIZE))
407 #define PRIORITY_QUEUE_OFFSET (ATIO_QUEUE_OFFSET + \
408 (ATIO_QUEUE_ENTRIES * IOCB_SIZE))
409 #define MBOX_DMA_MEM_SIZE 4096
410 #define MBOX_DMA_MEM_OFFSET (PRIORITY_QUEUE_OFFSET + \
411 (PRIORITY_QUEUE_ENTRIES * IOCB_SIZE))
412 #define TOTAL_DMA_MEM_SIZE (MBOX_DMA_MEM_OFFSET + MBOX_DMA_MEM_SIZE)
413
414 #define QLT_MAX_ITERATIONS_PER_INTR 32
415 #define QLT_INFO_LEN 160
416
417 #define REG_RD16(qlt, addr) \
418 ddi_get16(qlt->regs_acc_handle, (uint16_t *)(qlt->regs + addr))
419 #define REG_RD32(qlt, addr) \
420 ddi_get32(qlt->regs_acc_handle, (uint32_t *)(qlt->regs + addr))
421 #define REG_WR16(qlt, addr, data) \
422 ddi_put16(qlt->regs_acc_handle, (uint16_t *)(qlt->regs + addr), \
423 (uint16_t)(data))
424 #define REG_WR32(qlt, addr, data) \
425 ddi_put32(qlt->regs_acc_handle, (uint32_t *)(qlt->regs + addr), \
426 (uint32_t)(data))
427 #define PCICFG_RD16(qlt, addr) \
428 pci_config_get16(qlt->pcicfg_acc_handle, (off_t)(addr))
429 #define PCICFG_RD32(qlt, addr) \
430 pci_config_get32(qlt->pcicfg_acc_handle, (off_t)(addr))
431 #define PCICFG_WR16(qlt, addr, data) \
432 pci_config_put16(qlt->pcicfg_acc_handle, (off_t)(addr), \
433 (uint16_t)(data))
434 #define QMEM_RD16(qlt, addr) \
435 ddi_get16(qlt->queue_mem_acc_handle, (uint16_t *)(addr))
436 #define DMEM_RD16(qlt, addr) LE_16((uint16_t)(*((uint16_t *)(addr))))
437 #define QMEM_RD32(qlt, addr) \
438 ddi_get32(qlt->queue_mem_acc_handle, (uint32_t *)(addr))
439 #define DMEM_RD32(qlt, addr) LE_32((uint32_t)(*((uint32_t *)(addr))))
440 /*
441 * #define QMEM_RD64(qlt, addr) \
442 * ddi_get64(qlt->queue_mem_acc_handle, (uint64_t *)(addr))
443 */
444 #define QMEM_WR16(qlt, addr, data) \
445 ddi_put16(qlt->queue_mem_acc_handle, (uint16_t *)(addr), \
446 (uint16_t)(data))
447 #define DMEM_WR16(qlt, addr, data) (*((uint16_t *)(addr)) = \
448 (uint16_t)LE_16((uint16_t)(data)))
449 #define QMEM_WR32(qlt, addr, data) \
450 ddi_put32(qlt->queue_mem_acc_handle, (uint32_t *)(addr), \
451 (uint32_t)(data))
452 #define DMEM_WR32(qlt, addr, data) (*((uint32_t *)(addr)) = \
453 LE_32((uint32_t)(data)))
454
455 /*
456 * [QD]MEM is always little endian so the [QD]MEM_WR64 macro works for
457 * both sparc and x86.
458 */
459 #define QMEM_WR64(qlt, addr, data) \
460 QMEM_WR32(qlt, addr, (data & 0xffffffff)), \
461 QMEM_WR32(qlt, (addr)+4, ((uint64_t)data) >> 32)
462
463 #define DMEM_WR64(qlt, addr, data) \
464 DMEM_WR32(qlt, addr, (data & 0xffffffff)), \
465 DMEM_WR32(qlt, (addr)+4, ((uint64_t)data) >> 32)
466
467 /*
468 * Structure used to associate values with strings which describe them.
469 */
470 typedef struct string_table_entry {
471 uint32_t value;
472 char *string;
473 } string_table_t;
474
475 char *prop_text(int prop_status);
476 char *value2string(string_table_t *entry, int value, int delimiter);
477
478 #define PROP_STATUS_DELIMITER ((uint32_t)0xFFFF)
479
480 #define DDI_PROP_STATUS() \
481 { \
482 {DDI_PROP_SUCCESS, "DDI_PROP_SUCCESS"}, \
483 {DDI_PROP_NOT_FOUND, "DDI_PROP_NOT_FOUND"}, \
484 {DDI_PROP_UNDEFINED, "DDI_PROP_UNDEFINED"}, \
485 {DDI_PROP_NO_MEMORY, "DDI_PROP_NO_MEMORY"}, \
486 {DDI_PROP_INVAL_ARG, "DDI_PROP_INVAL_ARG"}, \
487 {DDI_PROP_BUF_TOO_SMALL, "DDI_PROP_BUF_TOO_SMALL"}, \
488 {DDI_PROP_CANNOT_DECODE, "DDI_PROP_CANNOT_DECODE"}, \
489 {DDI_PROP_CANNOT_ENCODE, "DDI_PROP_CANNOT_ENCODE"}, \
490 {DDI_PROP_END_OF_DATA, "DDI_PROP_END_OF_DATA"}, \
491 {PROP_STATUS_DELIMITER, "DDI_PROP_UNKNOWN"} \
492 }
493
494 #ifndef TRUE
495 #define TRUE B_TRUE
496 #endif
497
498 #ifndef FALSE
499 #define FALSE B_FALSE
500 #endif
501
502 /* Little endian machine correction defines. */
503 #ifdef _LITTLE_ENDIAN
504 #define LITTLE_ENDIAN_16(x)
505 #define LITTLE_ENDIAN_24(x)
506 #define LITTLE_ENDIAN_32(x)
507 #define LITTLE_ENDIAN_64(x)
508 #define LITTLE_ENDIAN(bp, bytes)
509 #define BIG_ENDIAN_16(x) qlt_chg_endian((uint8_t *)x, 2)
510 #define BIG_ENDIAN_24(x) qlt_chg_endian((uint8_t *)x, 3)
511 #define BIG_ENDIAN_32(x) qlt_chg_endian((uint8_t *)x, 4)
512 #define BIG_ENDIAN_64(x) qlt_chg_endian((uint8_t *)x, 8)
513 #define BIG_ENDIAN(bp, bytes) qlt_chg_endian((uint8_t *)bp, bytes)
514 #endif /* _LITTLE_ENDIAN */
515
516 /* Big endian machine correction defines. */
517 #ifdef _BIG_ENDIAN
518 #define LITTLE_ENDIAN_16(x) qlt_chg_endian((uint8_t *)x, 2)
519 #define LITTLE_ENDIAN_24(x) qlt_chg_endian((uint8_t *)x, 3)
520 #define LITTLE_ENDIAN_32(x) qlt_chg_endian((uint8_t *)x, 4)
521 #define LITTLE_ENDIAN_64(x) qlt_chg_endian((uint8_t *)x, 8)
522 #define LITTLE_ENDIAN(bp, bytes) qlt_chg_endian((uint8_t *)bp, bytes)
523 #define BIG_ENDIAN_16(x)
524 #define BIG_ENDIAN_24(x)
525 #define BIG_ENDIAN_32(x)
526 #define BIG_ENDIAN_64(x)
527 #define BIG_ENDIAN(bp, bytes)
528 #endif /* _BIG_ENDIAN */
529
530 #define LSB(x) (uint8_t)(x)
531 #define MSB(x) (uint8_t)((uint16_t)(x) >> 8)
532 #define MSW(x) (uint16_t)((uint32_t)(x) >> 16)
533 #define LSW(x) (uint16_t)(x)
534 #define LSD(x) (uint32_t)(x)
535 #define MSD(x) (uint32_t)((uint64_t)(x) >> 32)
536
537 void qlt_chg_endian(uint8_t *, size_t);
538
539 void qlt_el_msg(qlt_state_t *qlt, const char *fn, int ce, ...);
540 void qlt_dump_el_trace_buffer(qlt_state_t *qlt);
541 #define EL(qlt, ...) qlt_el_msg(qlt, __func__, CE_CONT, __VA_ARGS__);
542 #define EL_TRACE_BUF_SIZE 8192
543 #define EL_BUFFER_RESERVE 256
544 #define DEBUG_STK_DEPTH 24
545 #define EL_TRACE_BUF_SIZE 8192
546
547 #ifdef __cplusplus
548 }
549 #endif
550
551 #endif /* _QLT_H */
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