usr/src/uts/common/io/cxgbe/t4nex/offload.h

   1 /*
   2  * This file and its contents are supplied under the terms of the
   3  * Common Development and Distribution License ("CDDL"), version 1.0.
   4  * You may only use this file in accordance with the terms of version
   5  * 1.0 of the CDDL.
   6  *
   7  * A full copy of the text of the CDDL should have accompanied this
   8  * source. A copy of the CDDL is also available via the Internet at
   9  * http://www.illumos.org/license/CDDL.
  10  */
  11
  12 /*
  13  * This file is part of the Chelsio T4 support code.
  14  *
  15  * Copyright (C) 2010-2013 Chelsio Communications.  All rights reserved.
  16  *
  17  * This program is distributed in the hope that it will be useful, but WITHOUT
  18  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  19  * FITNESS FOR A PARTICULAR PURPOSE.  See the LICENSE file included in this
  20  * release for licensing terms and conditions.
  21  */
  22
  23 #ifndef __CXGBE_OFFLOAD_H
  24 #define __CXGBE_OFFLOAD_H
  25
  26 /*
  27  * Max # of ATIDs.  The absolute HW max is 16K but we keep it lower.
  28  */
  29 #define MAX_ATIDS 8192U
  30
  31 #define INIT_ULPTX_WR(w, wrlen, atomic, tid) do { \
  32         (w)->wr.wr_hi = htonl(V_FW_WR_OP(FW_ULPTX_WR) | \
  33                 V_FW_WR_ATOMIC(atomic)); \
  34         (w)->wr.wr_mid = htonl(V_FW_WR_LEN16(DIV_ROUND_UP(wrlen, 16)) | \
  35                 V_FW_WR_FLOWID(tid)); \
  36         (w)->wr.wr_lo = cpu_to_be64(0); \
  37 } while (0)
  38
  39 #define INIT_TP_WR(w, tid) do { \
  40         (w)->wr.wr_hi = htonl(V_FW_WR_OP(FW_TP_WR) | \
  41                 V_FW_WR_IMMDLEN(sizeof (*w) - sizeof (w->wr))); \
  42         (w)->wr.wr_mid = htonl(V_FW_WR_LEN16(DIV_ROUND_UP(sizeof (*w), 16)) | \
  43                 V_FW_WR_FLOWID(tid)); \
  44         (w)->wr.wr_lo = cpu_to_be64(0); \
  45 } while (0)
  46
  47 #define INIT_TP_WR_MIT_CPL(w, cpl, tid) do { \
  48         INIT_TP_WR(w, tid); \
  49         OPCODE_TID(w) = htonl(MK_OPCODE_TID(cpl, tid)); \
  50 } while (0)
  51
  52 union serv_entry {
  53         void *data;
  54         union serv_entry *next;
  55 };
  56
  57 union aopen_entry {
  58         void *data;
  59         union aopen_entry *next;
  60 };
  61
  62 /*
  63  * Holds the size, base address, free list start, etc of the TID, server TID,
  64  * and active-open TID tables.  The tables themselves are allocated dynamically.
  65  */
  66 struct tid_info {
  67         void **tid_tab;
  68         unsigned int ntids;
  69
  70         union serv_entry *stid_tab;
  71         unsigned int nstids;
  72         unsigned int stid_base;
  73
  74         union aopen_entry *atid_tab;
  75         unsigned int natids;
  76
  77         struct filter_entry *ftid_tab;
  78         unsigned int nftids;
  79         unsigned int ftid_base;
  80         unsigned int ftids_in_use;
  81
  82         kmutex_t atid_lock;
  83         union aopen_entry *afree;
  84         unsigned int atids_in_use;
  85
  86         kmutex_t stid_lock;
  87         union serv_entry *sfree;
  88         unsigned int stids_in_use;
  89
  90         unsigned int tids_in_use;
  91 };
  92
  93 struct t4_range {
  94         u_int start;
  95         u_int size;
  96 };
  97
  98 struct t4_virt_res {            /* virtualized HW resources */
  99         struct t4_range ddp;
 100         struct t4_range iscsi;
 101         struct t4_range stag;
 102         struct t4_range rq;
 103         struct t4_range pbl;
 104         struct t4_range l2t;
 105 };
 106
 107 struct adapter;
 108 struct port_info;
 109
 110 enum {
 111         ULD_TOM = 1,
 112 };
 113
 114 enum cxgb4_control {
 115         CXGB4_CONTROL_SET_OFFLOAD_POLICY,
 116 };
 117
 118 struct uld_info {
 119         SLIST_ENTRY(uld_info) link;
 120         int refcount;
 121         int uld_id;
 122         int (*attach)(struct adapter *, void **);
 123         int (*detach)(void *);
 124         int (*rx)(void *, const void *, mblk_t *);
 125         int (*control)(void *handle, enum cxgb4_control control, ...);
 126 };
 127
 128 struct uld_softc {
 129         struct uld_info *uld;
 130         void *softc;
 131 };
 132
 133 struct tom_tunables {
 134         int sndbuf;
 135         int ddp;
 136         int indsz;
 137         int ddp_thres;
 138 };
 139
 140 #ifndef TCP_OFFLOAD_DISABLE
 141 struct offload_req {
 142         __be32 sip[4];
 143         __be32 dip[4];
 144         __be16 sport;
 145         __be16 dport;
 146         __u8   ipvers_opentype;
 147         __u8   tos;
 148         __be16 vlan;
 149         __u32  mark;
 150 };
 151
 152 enum { OPEN_TYPE_LISTEN, OPEN_TYPE_ACTIVE, OPEN_TYPE_PASSIVE };
 153
 154 struct offload_settings {
 155         __u8  offload;
 156         int8_t  ddp;
 157         int8_t  rx_coalesce;
 158         int8_t  cong_algo;
 159         int32_t rssq;
 160         int16_t sched_class;
 161         int8_t  tstamp;
 162         int8_t  sack;
 163
 164 };
 165 #endif
 166
 167 extern int t4_register_uld(struct uld_info *ui);
 168 extern int t4_unregister_uld(struct uld_info *ui);
 169
 170 #endif /* __CXGBE_OFFLOAD_H */