usr/src/uts/intel/io/drm/radeon_io32.h

   1 /*
   2  * CDDL HEADER START
   3  *
   4  * The contents of this file are subject to the terms of the
   5  * Common Development and Distribution License (the "License").
   6  * You may not use this file except in compliance with the License.
   7  *
   8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
   9  * or http://www.opensolaris.org/os/licensing.
  10  * See the License for the specific language governing permissions
  11  * and limitations under the License.
  12  *
  13  * When distributing Covered Code, include this CDDL HEADER in each
  14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
  15  * If applicable, add the following below this CDDL HEADER, with the
  16  * fields enclosed by brackets "[]" replaced with your own identifying
  17  * information: Portions Copyright [yyyy] [name of copyright owner]
  18  *
  19  * CDDL HEADER END
  20  */
  21 /*
  22  * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
  23  * Use is subject to license terms.
  24  */
  25
  26 #pragma ident   "%Z%%M% %I%     %E% SMI"
  27
  28 #ifndef __RADEON_IO32_H__
  29 #define __RADEON_IO32_H__
  30
  31
  32 #ifdef  _MULTI_DATAMODEL
  33 /*
  34  * For radeon_cp_init()
  35  */
  36 typedef struct drm_radeon_init_32 {
  37         int     func;
  38         unsigned int sarea_priv_offset;
  39         int is_pci; /* for overriding only */
  40         int cp_mode;
  41         int gart_size;
  42         int ring_size;
  43         int usec_timeout;
  44
  45         unsigned int fb_bpp;
  46         unsigned int front_offset, front_pitch;
  47         unsigned int back_offset, back_pitch;
  48         unsigned int depth_bpp;
  49         unsigned int depth_offset, depth_pitch;
  50
  51         unsigned int fb_offset DEPRECATED;
  52         unsigned int mmio_offset DEPRECATED;
  53         unsigned int ring_offset;
  54         unsigned int ring_rptr_offset;
  55         unsigned int buffers_offset;
  56         unsigned int gart_textures_offset;
  57 } drm_radeon_init_32_t;
  58
  59 /*
  60  * radeon_cp_buffers()
  61  */
  62 typedef struct drm_dma_32 {
  63         int             context;
  64         int             send_count;
  65         uint32_t        send_indices;
  66         uint32_t        send_sizes;
  67         drm_dma_flags_t flags;
  68         int             request_count;
  69         int             request_size;
  70         uint32_t        request_indices;
  71         uint32_t        request_sizes;
  72         int granted_count;
  73 } drm_dma_32_t;
  74
  75 /*
  76  * drm_radeon_clear()
  77  */
  78 typedef struct drm_radeon_clear_32 {
  79         unsigned int    flags;
  80         unsigned int    clear_color;
  81         unsigned int    clear_depth;
  82         unsigned int    color_mask;
  83         unsigned int    depth_mask;
  84         uint32_t        depth_boxes;
  85 } drm_radeon_clear_32_t;
  86
  87 /*
  88  * For radeon_cp_texture()
  89  */
  90 typedef struct drm_radeon_tex_image_32 {
  91         unsigned int    x, y;
  92         unsigned int    width, height;
  93         uint32_t        data;
  94 } drm_radeon_tex_image_32_t;
  95
  96 typedef struct drm_radeon_texture_32 {
  97         unsigned int offset;
  98         int             pitch;
  99         int             format;
 100         int             width;
 101         int             height;
 102         uint32_t        image;
 103 } drm_radeon_texture_32_t;
 104
 105 /*
 106  * for radeon_cp_stipple()
 107  */
 108 typedef struct drm_radeon_stipple_32 {
 109         uint32_t mask;
 110 } drm_radeon_stipple_32_t;
 111
 112 /*
 113  * radeon_cp_vertex2()
 114  */
 115 typedef struct drm_radeon_vertex2_32 {
 116         int             idx;
 117         int             discard;
 118         int             nr_states;
 119         uint32_t        state;
 120         int     nr_prims;
 121         uint32_t prim;
 122 } drm_radeon_vertex2_32_t;
 123
 124 /*
 125  * radeon_cp_cmdbuf()
 126  */
 127 typedef struct drm_radeon_kcmd_buffer_32 {
 128         int     bufsz;
 129         uint32_t buf;
 130         int     nbox;
 131         uint32_t boxes;
 132 } drm_radeon_kcmd_buffer_32_t;
 133
 134 /*
 135  * radeon_cp_getparam()
 136  */
 137 typedef struct drm_radeon_getparam_32 {
 138         int     param;
 139         uint32_t value;
 140 } drm_radeon_getparam_32_t;
 141
 142
 143 /*
 144  * radeon_mem_alloc()
 145  */
 146 typedef struct drm_radeon_mem_alloc_32 {
 147         int     region;
 148         int     alignment;
 149         int     size;
 150         uint32_t region_offset; /* offset from start of fb or GART */
 151 } drm_radeon_mem_alloc_32_t;
 152
 153
 154 /*
 155  * radeon_irq_emit()
 156  */
 157 typedef struct drm_radeon_irq_emit_32 {
 158         uint32_t        irq_seq;
 159 } drm_radeon_irq_emit_32_t;
 160
 161
 162 /*
 163  * radeon_cp_setparam()
 164  */
 165 #pragma pack(1)
 166 typedef struct drm_radeon_setparam_32 {
 167         unsigned int param;
 168         uint64_t        value;
 169 } drm_radeon_setparam_32_t;
 170 #pragma pack()
 171
 172 #endif  /* _MULTI_DATAMODEL */
 173 #endif  /* __RADEON_IO32_H__ */