usr/src/grub/grub-0.97/netboot/sis900.h

   1 /* -*- Mode:C; c-basic-offset:4; -*- */
   2
   3 /* Definitions for SiS ethernet controllers including 7014/7016 and 900
   4  * References:
   5  *   SiS 7016 Fast Ethernet PCI Bus 10/100 Mbps LAN Controller with OnNow Support,
   6  *      preliminary Rev. 1.0 Jan. 14, 1998
   7  *   SiS 900 Fast Ethernet PCI Bus 10/100 Mbps LAN Single Chip with OnNow Support,
   8  *      preliminary Rev. 1.0 Nov. 10, 1998
   9  *   SiS 7014 Single Chip 100BASE-TX/10BASE-T Physical Layer Solution,
  10  *      preliminary Rev. 1.0 Jan. 18, 1998
  11  *   http://www.sis.com.tw/support/databook.htm
  12  */
  13
  14 /* MAC operationl registers of SiS 7016 and SiS 900 ethernet controller */
  15 /* The I/O extent, SiS 900 needs 256 bytes of io address */
  16 #define SIS900_TOTAL_SIZE 0x100
  17
  18 /* Symbolic offsets to registers. */
  19 enum sis900_registers {
  20     cr=0x0,                 /* Command Register */
  21     cfg=0x4,                /* Configuration Register */
  22     mear=0x8,               /* EEPROM Access Register */
  23     ptscr=0xc,              /* PCI Test Control Register */
  24     isr=0x10,               /* Interrupt Status Register */
  25     imr=0x14,               /* Interrupt Mask Register */
  26     ier=0x18,               /* Interrupt Enable Register */
  27     epar=0x18,              /* Enhanced PHY Access Register */
  28     txdp=0x20,              /* Transmit Descriptor Pointer Register */
  29     txcfg=0x24,             /* Transmit Configuration Register */
  30     rxdp=0x30,              /* Receive Descriptor Pointer Register */
  31     rxcfg=0x34,             /* Receive Configuration Register */
  32     flctrl=0x38,            /* Flow Control Register */
  33     rxlen=0x3c,             /* Receive Packet Length Register */
  34     rfcr=0x48,              /* Receive Filter Control Register */
  35     rfdr=0x4C,              /* Receive Filter Data Register */
  36     pmctrl=0xB0,            /* Power Management Control Register */
  37     pmer=0xB4               /* Power Management Wake-up Event Register */
  38 };
  39
  40 /* Symbolic names for bits in various registers */
  41 enum sis900_command_register_bits {
  42     RELOAD     = 0x00000400,
  43     ACCESSMODE = 0x00000200,
  44     RESET      = 0x00000100,
  45     SWI        = 0x00000080,
  46     RxRESET    = 0x00000020,
  47     TxRESET    = 0x00000010,
  48     RxDIS      = 0x00000008,
  49     RxENA      = 0x00000004,
  50     TxDIS      = 0x00000002,
  51     TxENA      = 0x00000001
  52 };
  53
  54 enum sis900_configuration_register_bits {
  55     DESCRFMT = 0x00000100, /* 7016 specific */
  56     REQALG   = 0x00000080,
  57     SB       = 0x00000040,
  58     POW      = 0x00000020,
  59     EXD      = 0x00000010,
  60     PESEL    = 0x00000008,
  61     LPM      = 0x00000004,
  62     BEM      = 0x00000001,
  63     RND_CNT  = 0x00000400,
  64     FAIR_BACKOFF = 0x00000200,
  65     EDB_MASTER_EN = 0x00002000
  66 };
  67
  68 enum sis900_eeprom_access_reigster_bits {
  69     MDC   = 0x00000040,
  70     MDDIR = 0x00000020,
  71     MDIO  = 0x00000010, /* 7016 specific */
  72     EECS  = 0x00000008,
  73     EECLK = 0x00000004,
  74     EEDO  = 0x00000002,
  75     EEDI  = 0x00000001
  76 };
  77
  78 enum sis900_interrupt_register_bits {
  79     WKEVT      = 0x10000000,
  80     TxPAUSEEND = 0x08000000,
  81     TxPAUSE    = 0x04000000,
  82     TxRCMP     = 0x02000000,
  83     RxRCMP     = 0x01000000,
  84     DPERR      = 0x00800000,
  85     SSERR      = 0x00400000,
  86     RMABT      = 0x00200000,
  87     RTABT      = 0x00100000,
  88     RxSOVR     = 0x00010000,
  89     HIBERR     = 0x00008000,
  90     SWINT      = 0x00001000,
  91     MIBINT     = 0x00000800,
  92     TxURN      = 0x00000400,
  93     TxIDLE     = 0x00000200,
  94     TxERR      = 0x00000100,
  95     TxDESC     = 0x00000080,
  96     TxOK       = 0x00000040,
  97     RxORN      = 0x00000020,
  98     RxIDLE     = 0x00000010,
  99     RxEARLY    = 0x00000008,
 100     RxERR      = 0x00000004,
 101     RxDESC     = 0x00000002,
 102     RxOK       = 0x00000001
 103 };
 104
 105 enum sis900_interrupt_enable_reigster_bits {
 106     IE = 0x00000001
 107 };
 108
 109 /* maximum dma burst fro transmission and receive*/
 110 #define MAX_DMA_RANGE   7       /* actually 0 means MAXIMUM !! */
 111 #define TxMXDMA_shift   20
 112 #define RxMXDMA_shift   20
 113 #define TX_DMA_BURST    0
 114 #define RX_DMA_BURST    0
 115
 116 enum sis900_tx_rx_dma{
 117                 DMA_BURST_512 = 0,      DMA_BURST_64 = 5
 118 };
 119
 120 /* transmit FIFO threshholds */
 121 #define TX_FILL_THRESH  16      /* 1/4 FIFO size */
 122 #define TxFILLT_shift   8
 123 #define TxDRNT_shift    0
 124 #define TxDRNT_100      48      /* 3/4 FIFO size */
 125 #define TxDRNT_10       16      /* 1/2 FIFO size */
 126
 127 enum sis900_transmit_config_register_bits {
 128     TxCSI   = 0x80000000,
 129     TxHBI   = 0x40000000,
 130     TxMLB   = 0x20000000,
 131     TxATP   = 0x10000000,
 132     TxIFG   = 0x0C000000,
 133     TxFILLT = 0x00003F00,
 134     TxDRNT  = 0x0000003F
 135 };
 136
 137 /* recevie FIFO thresholds */
 138 #define RxDRNT_shift     1
 139 #define RxDRNT_100      16      /* 1/2 FIFO size */
 140 #define RxDRNT_10       24      /* 3/4 FIFO size */
 141
 142 enum sis900_reveive_config_register_bits {
 143     RxAEP  = 0x80000000,
 144     RxARP  = 0x40000000,
 145     RxATX  = 0x10000000,
 146     RxAJAB = 0x08000000,
 147     RxDRNT = 0x0000007F
 148 };
 149
 150 #define RFAA_shift      28
 151 #define RFADDR_shift    16
 152
 153 enum sis900_receive_filter_control_register_bits {
 154     RFEN  = 0x80000000,
 155     RFAAB = 0x40000000,
 156     RFAAM = 0x20000000,
 157     RFAAP = 0x10000000,
 158     RFPromiscuous = (RFAAB|RFAAM|RFAAP)
 159 };
 160
 161 enum sis900_reveive_filter_data_mask {
 162     RFDAT =  0x0000FFFF
 163 };
 164
 165 /* EEPROM Addresses */
 166 enum sis900_eeprom_address {
 167     EEPROMSignature = 0x00,
 168     EEPROMVendorID  = 0x02,
 169     EEPROMDeviceID  = 0x03,
 170     EEPROMMACAddr   = 0x08,
 171     EEPROMChecksum  = 0x0b
 172 };
 173
 174 /* The EEPROM commands include the alway-set leading bit. Refer to NM93Cxx datasheet */
 175 enum sis900_eeprom_command {
 176     EEread          = 0x0180,
 177     EEwrite         = 0x0140,
 178     EEerase         = 0x01C0,
 179     EEwriteEnable   = 0x0130,
 180     EEwriteDisable  = 0x0100,
 181     EEeraseAll      = 0x0120,
 182     EEwriteAll      = 0x0110,
 183     EEaddrMask      = 0x013F,
 184     EEcmdShift      = 16
 185 };
 186 /* For SiS962 or SiS963, request the eeprom software access */
 187 enum sis96x_eeprom_command {
 188         EEREQ = 0x00000400, EEDONE = 0x00000200, EEGNT = 0x00000100
 189 };
 190
 191 /* Manamgement Data I/O (mdio) frame */
 192 #define MIIread         0x6000
 193 #define MIIwrite        0x5002
 194 #define MIIpmdShift     7
 195 #define MIIregShift     2
 196 #define MIIcmdLen       16
 197 #define MIIcmdShift     16
 198
 199 /* Buffer Descriptor Status*/
 200 enum sis900_buffer_status {
 201     OWN    = 0x80000000,
 202     MORE   = 0x40000000,
 203     INTR   = 0x20000000,
 204     SUPCRC = 0x10000000,
 205     INCCRC = 0x10000000,
 206     OK     = 0x08000000,
 207     DSIZE  = 0x00000FFF
 208 };
 209
 210 /* Status for TX Buffers */
 211 enum sis900_tx_buffer_status {
 212     ABORT      = 0x04000000,
 213     UNDERRUN   = 0x02000000,
 214     NOCARRIER  = 0x01000000,
 215     DEFERD     = 0x00800000,
 216     EXCDEFER   = 0x00400000,
 217     OWCOLL     = 0x00200000,
 218     EXCCOLL    = 0x00100000,
 219     COLCNT     = 0x000F0000
 220 };
 221
 222 enum sis900_rx_bufer_status {
 223     OVERRUN    = 0x02000000,
 224     DEST       = 0x00800000,
 225     BCAST      = 0x01800000,
 226     MCAST      = 0x01000000,
 227     UNIMATCH   = 0x00800000,
 228     TOOLONG    = 0x00400000,
 229     RUNT       = 0x00200000,
 230     RXISERR    = 0x00100000,
 231     CRCERR     = 0x00080000,
 232     FAERR      = 0x00040000,
 233     LOOPBK     = 0x00020000,
 234     RXCOL      = 0x00010000
 235 };
 236
 237 /* MII register offsets */
 238 enum mii_registers {
 239     MII_CONTROL = 0x0000,
 240     MII_STATUS  = 0x0001,
 241     MII_PHY_ID0 = 0x0002,
 242     MII_PHY_ID1 = 0x0003,
 243     MII_ANADV   = 0x0004,
 244     MII_ANLPAR  = 0x0005,
 245     MII_ANEXT   = 0x0006
 246 };
 247
 248 /* mii registers specific to SiS 900 */
 249 enum sis_mii_registers {
 250     MII_CONFIG1 = 0x0010,
 251     MII_CONFIG2 = 0x0011,
 252     MII_STSOUT  = 0x0012,
 253     MII_MASK    = 0x0013,
 254     MII_RESV    = 0x0014
 255 };
 256
 257 /* mii registers specific to AMD 79C901 */
 258 enum amd_mii_registers {
 259     MII_STATUS_SUMMARY = 0x0018
 260 };
 261
 262 /* mii registers specific to ICS 1893 */
 263 enum ics_mii_registers {
 264         MII_EXTCTRL  = 0x0010, MII_QPDSTS = 0x0011, MII_10BTOP = 0x0012,
 265         MII_EXTCTRL2 = 0x0013
 266 };
 267
 268
 269
 270 /* MII Control register bit definitions. */
 271 enum mii_control_register_bits {
 272     MII_CNTL_FDX      = 0x0100,
 273     MII_CNTL_RST_AUTO = 0x0200,
 274     MII_CNTL_ISOLATE  = 0x0400,
 275     MII_CNTL_PWRDWN   = 0x0800,
 276     MII_CNTL_AUTO     = 0x1000,
 277     MII_CNTL_SPEED    = 0x2000,
 278     MII_CNTL_LPBK     = 0x4000,
 279     MII_CNTL_RESET    = 0x8000
 280 };
 281
 282 /* MII Status register bit  */
 283 enum mii_status_register_bits {
 284     MII_STAT_EXT        = 0x0001,
 285     MII_STAT_JAB        = 0x0002,
 286     MII_STAT_LINK       = 0x0004,
 287     MII_STAT_CAN_AUTO   = 0x0008,
 288     MII_STAT_FAULT      = 0x0010,
 289     MII_STAT_AUTO_DONE  = 0x0020,
 290     MII_STAT_CAN_T      = 0x0800,
 291     MII_STAT_CAN_T_FDX  = 0x1000,
 292     MII_STAT_CAN_TX     = 0x2000,
 293     MII_STAT_CAN_TX_FDX = 0x4000,
 294     MII_STAT_CAN_T4     = 0x8000
 295 };
 296
 297 #define         MII_ID1_OUI_LO          0xFC00  /* low bits of OUI mask */
 298 #define         MII_ID1_MODEL           0x03F0  /* model number */
 299 #define         MII_ID1_REV             0x000F  /* model number */
 300
 301 /* MII NWAY Register Bits ...
 302    valid for the ANAR (Auto-Negotiation Advertisement) and
 303    ANLPAR (Auto-Negotiation Link Partner) registers */
 304 enum mii_nway_register_bits {
 305     MII_NWAY_NODE_SEL = 0x001f,
 306     MII_NWAY_CSMA_CD  = 0x0001,
 307     MII_NWAY_T        = 0x0020,
 308     MII_NWAY_T_FDX    = 0x0040,
 309     MII_NWAY_TX       = 0x0080,
 310     MII_NWAY_TX_FDX   = 0x0100,
 311     MII_NWAY_T4       = 0x0200,
 312     MII_NWAY_PAUSE    = 0x0400,
 313     MII_NWAY_RF       = 0x2000,
 314     MII_NWAY_ACK      = 0x4000,
 315     MII_NWAY_NP       = 0x8000
 316 };
 317
 318 enum mii_stsout_register_bits {
 319     MII_STSOUT_LINK_FAIL = 0x4000,
 320     MII_STSOUT_SPD       = 0x0080,
 321     MII_STSOUT_DPLX      = 0x0040
 322 };
 323
 324 enum mii_stsics_register_bits {
 325         MII_STSICS_SPD  = 0x8000, MII_STSICS_DPLX = 0x4000,
 326         MII_STSICS_LINKSTS = 0x0001
 327 };
 328
 329 enum mii_stssum_register_bits {
 330     MII_STSSUM_LINK = 0x0008,
 331     MII_STSSUM_DPLX = 0x0004,
 332     MII_STSSUM_AUTO = 0x0002,
 333     MII_STSSUM_SPD  = 0x0001
 334 };
 335
 336 enum sis900_revision_id {
 337         SIS630A_900_REV = 0x80,         SIS630E_900_REV = 0x81,
 338         SIS630S_900_REV = 0x82,         SIS630EA1_900_REV = 0x83,
 339         SIS630ET_900_REV = 0x84,        SIS635A_900_REV = 0x90,
 340         SIS96x_900_REV = 0X91,          SIS900B_900_REV = 0x03
 341 };
 342
 343 enum sis630_revision_id {
 344         SIS630A0    = 0x00, SIS630A1      = 0x01,
 345         SIS630B0    = 0x10, SIS630B1      = 0x11
 346 };
 347
 348 #define FDX_CAPABLE_DUPLEX_UNKNOWN      0
 349 #define FDX_CAPABLE_HALF_SELECTED       1
 350 #define FDX_CAPABLE_FULL_SELECTED       2
 351
 352 #define HW_SPEED_UNCONFIG               0
 353 #define HW_SPEED_HOME                   1
 354 #define HW_SPEED_10_MBPS                10
 355 #define HW_SPEED_100_MBPS               100
 356 #define HW_SPEED_DEFAULT                (HW_SPEED_100_MBPS)
 357
 358 #define CRC_SIZE        4
 359 #define MAC_HEADER_SIZE 14
 360
 361 #define TX_BUF_SIZE     1536
 362 #define RX_BUF_SIZE     1536
 363
 364 #define NUM_RX_DESC     4              /* Number of Rx descriptor registers. */
 365
 366 typedef unsigned char  u8;
 367 typedef   signed char  s8;
 368 typedef unsigned short u16;
 369 typedef   signed short s16;
 370 typedef unsigned int   u32;
 371 typedef   signed int   s32;
 372
 373 /* Time in ticks before concluding the transmitter is hung. */
 374 #define TX_TIMEOUT       (4*TICKS_PER_SEC)
 375
 376 typedef struct _BufferDesc {
 377     u32              link;
 378     volatile u32     cmdsts;
 379     u32              bufptr;
 380 } BufferDesc;