usr/src/uts/common/io/e1000api/e1000_ich8lan.h

   1 /******************************************************************************
   2
   3   Copyright (c) 2001-2014, Intel Corporation
   4   All rights reserved.
   5
   6   Redistribution and use in source and binary forms, with or without
   7   modification, are permitted provided that the following conditions are met:
   8
   9    1. Redistributions of source code must retain the above copyright notice,
  10       this list of conditions and the following disclaimer.
  11
  12    2. Redistributions in binary form must reproduce the above copyright
  13       notice, this list of conditions and the following disclaimer in the
  14       documentation and/or other materials provided with the distribution.
  15
  16    3. Neither the name of the Intel Corporation nor the names of its
  17       contributors may be used to endorse or promote products derived from
  18       this software without specific prior written permission.
  19
  20   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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  29   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30   POSSIBILITY OF SUCH DAMAGE.
  31
  32 ******************************************************************************/
  33 /*$FreeBSD$*/
  34
  35 #ifndef _E1000_ICH8LAN_H_
  36 #define _E1000_ICH8LAN_H_
  37
  38 #define ICH_FLASH_GFPREG                0x0000
  39 #define ICH_FLASH_HSFSTS                0x0004
  40 #define ICH_FLASH_HSFCTL                0x0006
  41 #define ICH_FLASH_FADDR                 0x0008
  42 #define ICH_FLASH_FDATA0                0x0010
  43
  44 /* Requires up to 10 seconds when MNG might be accessing part. */
  45 #define ICH_FLASH_READ_COMMAND_TIMEOUT  10000000
  46 #define ICH_FLASH_WRITE_COMMAND_TIMEOUT 10000000
  47 #define ICH_FLASH_ERASE_COMMAND_TIMEOUT 10000000
  48 #define ICH_FLASH_LINEAR_ADDR_MASK      0x00FFFFFF
  49 #define ICH_FLASH_CYCLE_REPEAT_COUNT    10
  50
  51 #define ICH_CYCLE_READ                  0
  52 #define ICH_CYCLE_WRITE                 2
  53 #define ICH_CYCLE_ERASE                 3
  54
  55 #define FLASH_GFPREG_BASE_MASK          0x1FFF
  56 #define FLASH_SECTOR_ADDR_SHIFT         12
  57
  58 #define ICH_FLASH_SEG_SIZE_256          256
  59 #define ICH_FLASH_SEG_SIZE_4K           4096
  60 #define ICH_FLASH_SEG_SIZE_8K           8192
  61 #define ICH_FLASH_SEG_SIZE_64K          65536
  62
  63 #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
  64 /* FW established a valid mode */
  65 #define E1000_ICH_FWSM_FW_VALID 0x00008000
  66 #define E1000_ICH_FWSM_PCIM2PCI 0x01000000 /* ME PCIm-to-PCI active */
  67 #define E1000_ICH_FWSM_PCIM2PCI_COUNT   2000
  68
  69 #define E1000_ICH_MNG_IAMT_MODE         0x2
  70
  71 #define E1000_FWSM_WLOCK_MAC_MASK       0x0380
  72 #define E1000_FWSM_WLOCK_MAC_SHIFT      7
  73 #define E1000_FWSM_ULP_CFG_DONE         0x00000400  /* Low power cfg done */
  74
  75 /* Shared Receive Address Registers */
  76 #define E1000_SHRAL_PCH_LPT(_i)         (0x05408 + ((_i) * 8))
  77 #define E1000_SHRAH_PCH_LPT(_i)         (0x0540C + ((_i) * 8))
  78
  79 #define E1000_H2ME              0x05B50    /* Host to ME */
  80 #define E1000_H2ME_ULP          0x00000800 /* ULP Indication Bit */
  81 #define E1000_H2ME_ENFORCE_SETTINGS     0x00001000 /* Enforce Settings */
  82
  83 #define ID_LED_DEFAULT_ICH8LAN  ((ID_LED_DEF1_DEF2 << 12) | \
  84                                  (ID_LED_OFF1_OFF2 <<  8) | \
  85                                  (ID_LED_OFF1_ON2  <<  4) | \
  86                                  (ID_LED_DEF1_DEF2))
  87
  88 #define E1000_ICH_NVM_SIG_WORD          0x13
  89 #define E1000_ICH_NVM_SIG_MASK          0xC000
  90 #define E1000_ICH_NVM_VALID_SIG_MASK    0xC0
  91 #define E1000_ICH_NVM_SIG_VALUE         0x80
  92
  93 #define E1000_ICH8_LAN_INIT_TIMEOUT     1500
  94
  95 /* FEXT register bit definition */
  96 #define E1000_FEXT_PHY_CABLE_DISCONNECTED       0x00000004
  97
  98 #define E1000_FEXTNVM_SW_CONFIG         1
  99 #define E1000_FEXTNVM_SW_CONFIG_ICH8M   (1 << 27) /* different on ICH8M */
 100
 101 #define E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK     0x0C000000
 102 #define E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC   0x08000000
 103
 104 #define E1000_FEXTNVM4_BEACON_DURATION_MASK     0x7
 105 #define E1000_FEXTNVM4_BEACON_DURATION_8USEC    0x7
 106 #define E1000_FEXTNVM4_BEACON_DURATION_16USEC   0x3
 107
 108 #define E1000_FEXTNVM6_REQ_PLL_CLK      0x00000100
 109 #define E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION        0x00000200
 110
 111 #define E1000_FEXTNVM7_DISABLE_SMB_PERST        0x00000020
 112
 113 #define PCIE_ICH8_SNOOP_ALL     PCIE_NO_SNOOP_ALL
 114
 115 #define E1000_ICH_RAR_ENTRIES   7
 116 #define E1000_PCH2_RAR_ENTRIES  5 /* RAR[0], SHRA[0-3] */
 117 #define E1000_PCH_LPT_RAR_ENTRIES       12 /* RAR[0], SHRA[0-10] */
 118
 119 #define PHY_PAGE_SHIFT          5
 120 #define PHY_REG(page, reg)      (((page) << PHY_PAGE_SHIFT) | \
 121                                  ((reg) & MAX_PHY_REG_ADDRESS))
 122 #define IGP3_KMRN_DIAG  PHY_REG(770, 19) /* KMRN Diagnostic */
 123 #define IGP3_VR_CTRL    PHY_REG(776, 18) /* Voltage Regulator Control */
 124
 125 #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS            0x0002
 126 #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK    0x0300
 127 #define IGP3_VR_CTRL_MODE_SHUTDOWN              0x0200
 128
 129 /* PHY Wakeup Registers and defines */
 130 #define BM_PORT_GEN_CFG         PHY_REG(BM_PORT_CTRL_PAGE, 17)
 131 #define BM_RCTL                 PHY_REG(BM_WUC_PAGE, 0)
 132 #define BM_WUC                  PHY_REG(BM_WUC_PAGE, 1)
 133 #define BM_WUFC                 PHY_REG(BM_WUC_PAGE, 2)
 134 #define BM_WUS                  PHY_REG(BM_WUC_PAGE, 3)
 135 #define BM_RAR_L(_i)            (BM_PHY_REG(BM_WUC_PAGE, 16 + ((_i) << 2)))
 136 #define BM_RAR_M(_i)            (BM_PHY_REG(BM_WUC_PAGE, 17 + ((_i) << 2)))
 137 #define BM_RAR_H(_i)            (BM_PHY_REG(BM_WUC_PAGE, 18 + ((_i) << 2)))
 138 #define BM_RAR_CTRL(_i)         (BM_PHY_REG(BM_WUC_PAGE, 19 + ((_i) << 2)))
 139 #define BM_MTA(_i)              (BM_PHY_REG(BM_WUC_PAGE, 128 + ((_i) << 1)))
 140
 141 #define BM_RCTL_UPE             0x0001 /* Unicast Promiscuous Mode */
 142 #define BM_RCTL_MPE             0x0002 /* Multicast Promiscuous Mode */
 143 #define BM_RCTL_MO_SHIFT        3      /* Multicast Offset Shift */
 144 #define BM_RCTL_MO_MASK         (3 << 3) /* Multicast Offset Mask */
 145 #define BM_RCTL_BAM             0x0020 /* Broadcast Accept Mode */
 146 #define BM_RCTL_PMCF            0x0040 /* Pass MAC Control Frames */
 147 #define BM_RCTL_RFCE            0x0080 /* Rx Flow Control Enable */
 148
 149 #define HV_LED_CONFIG           PHY_REG(768, 30) /* LED Configuration */
 150 #define HV_MUX_DATA_CTRL        PHY_REG(776, 16)
 151 #define HV_MUX_DATA_CTRL_GEN_TO_MAC     0x0400
 152 #define HV_MUX_DATA_CTRL_FORCE_SPEED    0x0004
 153 #define HV_STATS_PAGE   778
 154 /* Half-duplex collision counts */
 155 #define HV_SCC_UPPER    PHY_REG(HV_STATS_PAGE, 16) /* Single Collision */
 156 #define HV_SCC_LOWER    PHY_REG(HV_STATS_PAGE, 17)
 157 #define HV_ECOL_UPPER   PHY_REG(HV_STATS_PAGE, 18) /* Excessive Coll. */
 158 #define HV_ECOL_LOWER   PHY_REG(HV_STATS_PAGE, 19)
 159 #define HV_MCC_UPPER    PHY_REG(HV_STATS_PAGE, 20) /* Multiple Collision */
 160 #define HV_MCC_LOWER    PHY_REG(HV_STATS_PAGE, 21)
 161 #define HV_LATECOL_UPPER PHY_REG(HV_STATS_PAGE, 23) /* Late Collision */
 162 #define HV_LATECOL_LOWER PHY_REG(HV_STATS_PAGE, 24)
 163 #define HV_COLC_UPPER   PHY_REG(HV_STATS_PAGE, 25) /* Collision */
 164 #define HV_COLC_LOWER   PHY_REG(HV_STATS_PAGE, 26)
 165 #define HV_DC_UPPER     PHY_REG(HV_STATS_PAGE, 27) /* Defer Count */
 166 #define HV_DC_LOWER     PHY_REG(HV_STATS_PAGE, 28)
 167 #define HV_TNCRS_UPPER  PHY_REG(HV_STATS_PAGE, 29) /* Tx with no CRS */
 168 #define HV_TNCRS_LOWER  PHY_REG(HV_STATS_PAGE, 30)
 169
 170 #define E1000_FCRTV_PCH 0x05F40 /* PCH Flow Control Refresh Timer Value */
 171
 172 #define E1000_NVM_K1_CONFIG     0x1B /* NVM K1 Config Word */
 173 #define E1000_NVM_K1_ENABLE     0x1  /* NVM Enable K1 bit */
 174
 175 /* SMBus Control Phy Register */
 176 #define CV_SMB_CTRL             PHY_REG(769, 23)
 177 #define CV_SMB_CTRL_FORCE_SMBUS 0x0001
 178
 179 /* I218 Ultra Low Power Configuration 1 Register */
 180 #define I218_ULP_CONFIG1                PHY_REG(779, 16)
 181 #define I218_ULP_CONFIG1_START          0x0001 /* Start auto ULP config */
 182 #define I218_ULP_CONFIG1_IND            0x0004 /* Pwr up from ULP indication */
 183 #define I218_ULP_CONFIG1_STICKY_ULP     0x0010 /* Set sticky ULP mode */
 184 #define I218_ULP_CONFIG1_INBAND_EXIT    0x0020 /* Inband on ULP exit */
 185 #define I218_ULP_CONFIG1_WOL_HOST       0x0040 /* WoL Host on ULP exit */
 186 #define I218_ULP_CONFIG1_RESET_TO_SMBUS 0x0100 /* Reset to SMBus mode */
 187 #define I218_ULP_CONFIG1_DISABLE_SMB_PERST      0x1000 /* Disable on PERST# */
 188
 189 /* SMBus Address Phy Register */
 190 #define HV_SMB_ADDR             PHY_REG(768, 26)
 191 #define HV_SMB_ADDR_MASK        0x007F
 192 #define HV_SMB_ADDR_PEC_EN      0x0200
 193 #define HV_SMB_ADDR_VALID       0x0080
 194 #define HV_SMB_ADDR_FREQ_MASK           0x1100
 195 #define HV_SMB_ADDR_FREQ_LOW_SHIFT      8
 196 #define HV_SMB_ADDR_FREQ_HIGH_SHIFT     12
 197
 198 /* Strapping Option Register - RO */
 199 #define E1000_STRAP                     0x0000C
 200 #define E1000_STRAP_SMBUS_ADDRESS_MASK  0x00FE0000
 201 #define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17
 202 #define E1000_STRAP_SMT_FREQ_MASK       0x00003000
 203 #define E1000_STRAP_SMT_FREQ_SHIFT      12
 204
 205 /* OEM Bits Phy Register */
 206 #define HV_OEM_BITS             PHY_REG(768, 25)
 207 #define HV_OEM_BITS_LPLU        0x0004 /* Low Power Link Up */
 208 #define HV_OEM_BITS_GBE_DIS     0x0040 /* Gigabit Disable */
 209 #define HV_OEM_BITS_RESTART_AN  0x0400 /* Restart Auto-negotiation */
 210
 211 /* KMRN Mode Control */
 212 #define HV_KMRN_MODE_CTRL       PHY_REG(769, 16)
 213 #define HV_KMRN_MDIO_SLOW       0x0400
 214
 215 /* KMRN FIFO Control and Status */
 216 #define HV_KMRN_FIFO_CTRLSTA                    PHY_REG(770, 16)
 217 #define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK      0x7000
 218 #define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT     12
 219
 220 /* PHY Power Management Control */
 221 #define HV_PM_CTRL              PHY_REG(770, 17)
 222 #define HV_PM_CTRL_PLL_STOP_IN_K1_GIGA  0x100
 223 #define HV_PM_CTRL_K1_ENABLE            0x4000
 224
 225 #define SW_FLAG_TIMEOUT         1000 /* SW Semaphore flag timeout in ms */
 226
 227 /* Inband Control */
 228 #define I217_INBAND_CTRL                                PHY_REG(770, 18)
 229 #define I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK      0x3F00
 230 #define I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT     8
 231
 232 /* Low Power Idle GPIO Control */
 233 #define I217_LPI_GPIO_CTRL                      PHY_REG(772, 18)
 234 #define I217_LPI_GPIO_CTRL_AUTO_EN_LPI          0x0800
 235
 236 /* PHY Low Power Idle Control */
 237 #define I82579_LPI_CTRL                         PHY_REG(772, 20)
 238 #define I82579_LPI_CTRL_100_ENABLE              0x2000
 239 #define I82579_LPI_CTRL_1000_ENABLE             0x4000
 240 #define I82579_LPI_CTRL_ENABLE_MASK             0x6000
 241
 242 /* 82579 DFT Control */
 243 #define I82579_DFT_CTRL                 PHY_REG(769, 20)
 244 #define I82579_DFT_CTRL_GATE_PHY_RESET  0x0040 /* Gate PHY Reset on MAC Reset */
 245
 246 /* Extended Management Interface (EMI) Registers */
 247 #define I82579_EMI_ADDR         0x10
 248 #define I82579_EMI_DATA         0x11
 249 #define I82579_LPI_UPDATE_TIMER 0x4805 /* in 40ns units + 40 ns base value */
 250 #define I82579_MSE_THRESHOLD    0x084F /* 82579 Mean Square Error Threshold */
 251 #define I82577_MSE_THRESHOLD    0x0887 /* 82577 Mean Square Error Threshold */
 252 #define I82579_MSE_LINK_DOWN    0x2411 /* MSE count before dropping link */
 253 #define I82579_RX_CONFIG                0x3412 /* Receive configuration */
 254 #define I82579_LPI_PLL_SHUT             0x4412 /* LPI PLL Shut Enable */
 255 #define I82579_EEE_PCS_STATUS           0x182E  /* IEEE MMD Register 3.1 >> 8 */
 256 #define I82579_EEE_CAPABILITY           0x0410 /* IEEE MMD Register 3.20 */
 257 #define I82579_EEE_ADVERTISEMENT        0x040E /* IEEE MMD Register 7.60 */
 258 #define I82579_EEE_LP_ABILITY           0x040F /* IEEE MMD Register 7.61 */
 259 #define I82579_EEE_100_SUPPORTED        (1 << 1) /* 100BaseTx EEE */
 260 #define I82579_EEE_1000_SUPPORTED       (1 << 2) /* 1000BaseTx EEE */
 261 #define I82579_LPI_100_PLL_SHUT (1 << 2) /* 100M LPI PLL Shut Enabled */
 262 #define I217_EEE_PCS_STATUS     0x9401   /* IEEE MMD Register 3.1 */
 263 #define I217_EEE_CAPABILITY     0x8000   /* IEEE MMD Register 3.20 */
 264 #define I217_EEE_ADVERTISEMENT  0x8001   /* IEEE MMD Register 7.60 */
 265 #define I217_EEE_LP_ABILITY     0x8002   /* IEEE MMD Register 7.61 */
 266 #define I217_RX_CONFIG          0xB20C /* Receive configuration */
 267
 268 #define E1000_EEE_RX_LPI_RCVD   0x0400  /* Tx LP idle received */
 269 #define E1000_EEE_TX_LPI_RCVD   0x0800  /* Rx LP idle received */
 270
 271 /* Intel Rapid Start Technology Support */
 272 #define I217_PROXY_CTRL         BM_PHY_REG(BM_WUC_PAGE, 70)
 273 #define I217_PROXY_CTRL_AUTO_DISABLE    0x0080
 274 #define I217_SxCTRL                     PHY_REG(BM_PORT_CTRL_PAGE, 28)
 275 #define I217_SxCTRL_ENABLE_LPI_RESET    0x1000
 276 #define I217_CGFREG                     PHY_REG(772, 29)
 277 #define I217_CGFREG_ENABLE_MTA_RESET    0x0002
 278 #define I217_MEMPWR                     PHY_REG(772, 26)
 279 #define I217_MEMPWR_DISABLE_SMB_RELEASE 0x0010
 280
 281 /* Receive Address Initial CRC Calculation */
 282 #define E1000_PCH_RAICC(_n)     (0x05F50 + ((_n) * 4))
 283
 284 /* Latency Tolerance Reporting */
 285 #define E1000_LTRV                      0x000F8
 286 #define E1000_LTRV_VALUE_MASK           0x000003FF
 287 #define E1000_LTRV_SCALE_MAX            5
 288 #define E1000_LTRV_SCALE_FACTOR         5
 289 #define E1000_LTRV_SCALE_SHIFT          10
 290 #define E1000_LTRV_SCALE_MASK           0x00001C00
 291 #define E1000_LTRV_REQ_SHIFT            15
 292 #define E1000_LTRV_NOSNOOP_SHIFT        16
 293 #define E1000_LTRV_SEND                 (1 << 30)
 294
 295 /* Proprietary Latency Tolerance Reporting PCI Capability */
 296 #define E1000_PCI_LTR_CAP_LPT           0xA8
 297
 298 /* OBFF Control & Threshold Defines */
 299 #define E1000_SVCR_OFF_EN               0x00000001
 300 #define E1000_SVCR_OFF_MASKINT          0x00001000
 301 #define E1000_SVCR_OFF_TIMER_MASK       0xFFFF0000
 302 #define E1000_SVCR_OFF_TIMER_SHIFT      16
 303 #define E1000_SVT_OFF_HWM_MASK          0x0000001F
 304
 305 void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
 306                                                  bool state);
 307 void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw);
 308 void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw);
 309 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw);
 310 void e1000_resume_workarounds_pchlan(struct e1000_hw *hw);
 311 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable);
 312 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw);
 313 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable);
 314 s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data);
 315 s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data);
 316 s32 e1000_set_eee_pchlan(struct e1000_hw *hw);
 317 s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx);
 318 s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force);
 319 #endif /* _E1000_ICH8LAN_H_ */