4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License, v.1, (the "License").
6 * You may not use this file except in compliance with the License.
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://opensource.org/licenses/CDDL-1.0.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
23 * Copyright 2014-2017 Cavium, Inc.
24 * The contents of this file are subject to the terms of the Common Development
25 * and Distribution License, v.1, (the "License").
27 * You may not use this file except in compliance with the License.
29 * You can obtain a copy of the License at available
30 * at http://opensource.org/licenses/CDDL-1.0
32 * See the License for the specific language governing permissions and
33 * limitations under the License.
36 /****************************************************************************
39 * Description: Everest NVRAM map
41 ****************************************************************************/
46 #define CRC_MAGIC_VALUE 0xDEBB20E3
47 #define CRC32_POLYNOMIAL 0xEDB88320
48 #define NVM_CRC_SIZE (sizeof(u32))
49 enum nvm_sw_arbitrator
{
56 /****************************************************************************
58 ****************************************************************************/
59 struct legacy_bootstrap_region
{
60 u32 magic_value
; /* a pattern not likely to occur randomly */
61 #define NVM_MAGIC_VALUE 0x669955aa
62 u32 sram_start_addr
; /* where to locate LIM code (byte addr) */
63 u32 code_len
; /* boot code length (in dwords) */
64 u32 code_start_addr
; /* location of code on media (media byte addr) */
65 u32 crc
; /* 32-bit CRC */
68 /****************************************************************************
69 * Directories Region *
70 ****************************************************************************/
71 struct nvm_code_entry
{
72 u32 image_type
; /* Image type */
73 u32 nvm_start_addr
; /* NVM address of the image */
74 u32 len
; /* Include CRC */
75 u32 sram_start_addr
; /* Where to load the image on the scratchpad */
76 u32 sram_run_addr
; /* Relevant in case of MIM only */
85 NVM_TYPE_MODULES_PN
= 0x06,
87 NVM_TYPE_MFW_TRACE1
= 0x08,
88 NVM_TYPE_MFW_TRACE2
= 0x09,
89 NVM_TYPE_NVM_CFG1
= 0x0a,
92 NVM_TYPE_EAGLE_FW1
= 0x0d,
93 NVM_TYPE_FALCON_FW1
= 0x0e,
94 NVM_TYPE_PCIE_FW1
= 0x0f,
95 NVM_TYPE_HW_SET
= 0x10,
97 NVM_TYPE_AVS_FW1
= 0x12,
100 NVM_TYPE_EAGLE_FW2
= 0x15,
101 NVM_TYPE_FALCON_FW2
= 0x16,
102 NVM_TYPE_PCIE_FW2
= 0x17,
103 NVM_TYPE_AVS_FW2
= 0x18,
104 NVM_TYPE_INIT_HW
= 0x19,
105 NVM_TYPE_DEFAULT_CFG
= 0x1a,
106 NVM_TYPE_MDUMP
= 0x1b,
107 NVM_TYPE_NVM_META
= 0x1c,
108 NVM_TYPE_ISCSI_CFG
= 0x1d,
109 NVM_TYPE_FCOE_CFG
= 0x1f,
110 NVM_TYPE_ETH_PHY_FW1
= 0x20,
111 NVM_TYPE_ETH_PHY_FW2
= 0x21,
113 NVM_TYPE_8485X_PHY_FW
= 0x23,
114 NVM_TYPE_PUB_KEY
= 0x24,
115 NVM_TYPE_RECOVERY
= 0x25,
119 #ifdef DEFINE_IMAGE_TABLE
126 struct image_map g_image_table
[] = {
127 {"TIM1", "-tim1", NVM_TYPE_TIM1
},
128 {"TIM2", "-tim2", NVM_TYPE_TIM2
},
129 {"MIM1", "-mim1", NVM_TYPE_MIM1
},
130 {"MIM2", "-mim2", NVM_TYPE_MIM2
},
131 {"MBA", "-mba", NVM_TYPE_MBA
},
132 {"OPT_MODULES", "-optm", NVM_TYPE_MODULES_PN
},
133 {"VPD", "-vpd", NVM_TYPE_VPD
},
134 {"MFW_TRACE1", "-mfwt1", NVM_TYPE_MFW_TRACE1
},
135 {"MFW_TRACE2", "-mfwt2", NVM_TYPE_MFW_TRACE2
},
136 {"NVM_CFG1", "-cfg", NVM_TYPE_NVM_CFG1
},
137 {"L2B", "-l2b", NVM_TYPE_L2B
},
138 {"DIR1", "-dir1", NVM_TYPE_DIR1
},
139 {"EAGLE_FW1", "-eagle1", NVM_TYPE_EAGLE_FW1
},
140 {"FALCON_FW1", "-falcon1", NVM_TYPE_FALCON_FW1
},
141 {"PCIE_FW1", "-pcie1", NVM_TYPE_PCIE_FW1
},
142 {"HW_SET", "-hw_set", NVM_TYPE_HW_SET
},
143 {"LIM", "-lim", NVM_TYPE_LIM
},
144 {"AVS_FW1", "-avs1", NVM_TYPE_AVS_FW1
},
145 {"DIR2", "-dir2", NVM_TYPE_DIR2
},
146 {"CCM", "-ccm", NVM_TYPE_CCM
},
147 {"EAGLE_FW2", "-eagle2", NVM_TYPE_EAGLE_FW2
},
148 {"FALCON_FW2", "-falcon2", NVM_TYPE_FALCON_FW2
},
149 {"PCIE_FW2", "-pcie2", NVM_TYPE_PCIE_FW2
},
150 {"AVS_FW2", "-avs2", NVM_TYPE_AVS_FW2
},
151 {"INIT_HW", "-init_hw", NVM_TYPE_INIT_HW
},
152 {"DEFAULT_CFG", "-def_cfg", NVM_TYPE_DEFAULT_CFG
},
153 {"CRASH_DUMP", "-mdump", NVM_TYPE_MDUMP
},
154 {"META", "-meta", NVM_TYPE_NVM_META
},
155 {"ISCSI_CFG", "-iscsi_cfg", NVM_TYPE_ISCSI_CFG
},
156 {"FCOE_CFG", "-fcoe_cfg",NVM_TYPE_FCOE_CFG
},
157 {"ETH_PHY_FW1", "-ethphy1", NVM_TYPE_ETH_PHY_FW1
},
158 {"ETH_PHY_FW2", "-ethphy2", NVM_TYPE_ETH_PHY_FW2
},
159 {"BDN", "-bdn", NVM_TYPE_BDN
},
160 {"PK", "-pk", NVM_TYPE_PUB_KEY
},
161 {"RECOVERY", "-recovery",NVM_TYPE_RECOVERY
}
164 #define IMAGE_TABLE_SIZE (sizeof(g_image_table) / sizeof(struct image_map))
166 #endif /* #ifdef DEFINE_IMAGE_TABLE */
167 #define MAX_NVM_DIR_ENTRIES 150
168 /* Note: The has given 150 possible entries since anyway each file captures at least one page. */
171 s32 seq
; /* This dword is used to indicate whether this dir is valid, and whether it is more updated than the other dir */
172 #define NVM_DIR_NEXT_MFW_MASK 0x00000001
173 #define NVM_DIR_SEQ_MASK 0xfffffffe
174 #define NVM_DIR_NEXT_MFW(seq) ((seq) & NVM_DIR_NEXT_MFW_MASK)
175 #define NVM_DIR_UPDATE_SEQ(_seq, swap_mfw) \
177 _seq = (((_seq + 2) & NVM_DIR_SEQ_MASK) | (NVM_DIR_NEXT_MFW(_seq ^ swap_mfw))); \
179 #define IS_DIR_SEQ_VALID(seq) ((seq & NVM_DIR_SEQ_MASK) != NVM_DIR_SEQ_MASK)
183 struct nvm_code_entry code
[1]; /* Up to MAX_NVM_DIR_ENTRIES */
185 #define NVM_DIR_SIZE(_num_images) (sizeof(struct nvm_dir) + (_num_images - 1) * sizeof(struct nvm_code_entry) + NVM_CRC_SIZE)
187 struct nvm_vpd_image
{
189 #define VPD_IMAGE_VERSION 1
191 /* This array length depends on the number of VPD fields */
195 /****************************************************************************
197 ****************************************************************************/
200 #define MAX_DIR_IDS (2)
202 #define MFW_BUNDLE_1 (0)
203 #define MFW_BUNDLE_2 (1)
204 #define MAX_MFW_BUNDLES (2)
206 #define FLASH_PAGE_SIZE 0x1000
207 #define NVM_DIR_MAX_SIZE (FLASH_PAGE_SIZE) /* 4Kb */
208 #define ASIC_MIM_MAX_SIZE (300*FLASH_PAGE_SIZE) /* 1.2Mb */
209 #define FPGA_MIM_MAX_SIZE (62*FLASH_PAGE_SIZE) /* 250Kb */
211 /* Each image must start on its own page. Bootstrap and LIM are bound together, so they can share the same page.
212 * The LIM itself should be very small, so limit it to 8Kb, but in order to open a new page, we decrement the bootstrap size out of it.
214 #define LIM_MAX_SIZE ((2*FLASH_PAGE_SIZE) - sizeof(struct legacy_bootstrap_region) - NVM_RSV_SIZE)
215 #define LIM_OFFSET (NVM_OFFSET(lim_image))
216 #define NVM_RSV_SIZE (44)
217 #define MIM_MAX_SIZE(is_asic) ((is_asic) ? ASIC_MIM_MAX_SIZE : FPGA_MIM_MAX_SIZE )
218 #define MIM_OFFSET(idx, is_asic) (NVM_OFFSET(dir[MAX_MFW_BUNDLES]) + ((idx == NVM_TYPE_MIM2) ? MIM_MAX_SIZE(is_asic) : 0))
219 #define NVM_FIXED_AREA_SIZE(is_asic) (sizeof(struct nvm_image) + MIM_MAX_SIZE(is_asic)*2)
221 union nvm_dir_union
{
223 u8 page
[FLASH_PAGE_SIZE
];
227 * +-------------------+ 0x000000
230 * | sram_start_addr |
232 * | code_start_addr |
234 * +-------------------+ 0x000014
236 * +-------------------+ 0x000040
238 * +-------------------+ 0x002000
240 * +-------------------+ 0x003000
242 * +-------------------+ 0x004000
244 * +-------------------+ 0x130000
246 * +-------------------+ 0x25C000
250 * | Eagle/Falcon FW |
256 * +-------------------+ 0x400000
259 /*********** !!! FIXED SECTIONS !!! DO NOT MODIFY !!! **********************/
260 /* NVM Offset (size) */
261 struct legacy_bootstrap_region bootstrap
; /* 0x000000 (0x000014) */
262 u8 rsrv
[NVM_RSV_SIZE
]; /* 0x000014 (0x00002c) */
263 u8 lim_image
[LIM_MAX_SIZE
]; /* 0x000040 (0x001fc0) */
264 union nvm_dir_union dir
[MAX_MFW_BUNDLES
]; /* 0x002000 (0x001000)x2 */
265 /* MIM1_IMAGE 0x004000 (0x12c000) */
266 /* MIM2_IMAGE 0x130000 (0x12c000) */
267 /*********** !!! FIXED SECTIONS !!! DO NOT MODIFY !!! **********************/
270 #define NVM_OFFSET(f) ((u32_t)((int_ptr_t)(&(((struct nvm_image*)0)->f))))
274 #define GRC_REG_TYPE 1
275 #define PHY_REG_TYPE 2
276 #define PCI_REG_TYPE 4
290 #define POR_RESET_TYPE (1 << 0)
291 #define HARD_RESET_TYPE (1 << 1)
292 #define CORE_RESET_TYPE (1 << 2)
293 #define MCP_RESET_TYPE (1 << 3)
294 #define PERSET_ASSERT (1 << 4)
295 #define PERSET_DEASSERT (1 << 5)
299 struct hw_set_image
{
301 #define HW_SET_IMAGE_VERSION 1
303 /* This array length depends on the no_hw_sets */
304 struct hw_set_info hw_sets
[1];