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Unleashed v1.4
[unleashed.git] / include / sys / nxge / nxge_ipp_hw.h
blob890ac7824d8885191b03bb912f9372f1ca2e82b6
1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21 /*
22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved.
23 * Use is subject to license terms.
24 */
25
26 #ifndef _SYS_NXGE_NXGE_IPP_HW_H
27 #define _SYS_NXGE_NXGE_IPP_HW_H
28
29 #pragma ident "%Z%%M% %I% %E% SMI"
30
31 #ifdef __cplusplus
32 extern "C" {
33 #endif
34
35 #include <nxge_defs.h>
36
37 /* IPP Registers */
38 #define IPP_CONFIG_REG 0x000
39 #define IPP_DISCARD_PKT_CNT_REG 0x020
40 #define IPP_BAD_CKSUM_ERR_CNT_REG 0x028
41 #define IPP_ECC_ERR_COUNTER_REG 0x030
42 #define IPP_INT_STATUS_REG 0x040
43 #define IPP_INT_MASK_REG 0x048
44
45 #define IPP_PFIFO_RD_DATA0_REG 0x060
46 #define IPP_PFIFO_RD_DATA1_REG 0x068
47 #define IPP_PFIFO_RD_DATA2_REG 0x070
48 #define IPP_PFIFO_RD_DATA3_REG 0x078
49 #define IPP_PFIFO_RD_DATA4_REG 0x080
50 #define IPP_PFIFO_WR_DATA0_REG 0x088
51 #define IPP_PFIFO_WR_DATA1_REG 0x090
52 #define IPP_PFIFO_WR_DATA2_REG 0x098
53 #define IPP_PFIFO_WR_DATA3_REG 0x0a0
54 #define IPP_PFIFO_WR_DATA4_REG 0x0a8
55 #define IPP_PFIFO_RD_PTR_REG 0x0b0
56 #define IPP_PFIFO_WR_PTR_REG 0x0b8
57 #define IPP_DFIFO_RD_DATA0_REG 0x0c0
58 #define IPP_DFIFO_RD_DATA1_REG 0x0c8
59 #define IPP_DFIFO_RD_DATA2_REG 0x0d0
60 #define IPP_DFIFO_RD_DATA3_REG 0x0d8
61 #define IPP_DFIFO_RD_DATA4_REG 0x0e0
62 #define IPP_DFIFO_WR_DATA0_REG 0x0e8
63 #define IPP_DFIFO_WR_DATA1_REG 0x0f0
64 #define IPP_DFIFO_WR_DATA2_REG 0x0f8
65 #define IPP_DFIFO_WR_DATA3_REG 0x100
66 #define IPP_DFIFO_WR_DATA4_REG 0x108
67 #define IPP_DFIFO_RD_PTR_REG 0x110
68 #define IPP_DFIFO_WR_PTR_REG 0x118
69 #define IPP_STATE_MACHINE_REG 0x120
70 #define IPP_CKSUM_STATUS_REG 0x128
71 #define IPP_FFLP_CKSUM_INFO_REG 0x130
72 #define IPP_DEBUG_SELECT_REG 0x138
73 #define IPP_DFIFO_ECC_SYNDROME_REG 0x140
74 #define IPP_DFIFO_EOPM_RD_PTR_REG 0x148
75 #define IPP_ECC_CTRL_REG 0x150
76
77 #define IPP_PORT_OFFSET 0x4000
78 #define IPP_PORT0_OFFSET 0
79 #define IPP_PORT1_OFFSET 0x8000
80 #define IPP_PORT2_OFFSET 0x4000
81 #define IPP_PORT3_OFFSET 0xc000
82 #define IPP_REG_ADDR(port_num, reg)\
83 ((port_num == 0) ? FZC_IPP + reg : \
84 FZC_IPP + reg + (((port_num % 2) * IPP_PORT_OFFSET) + \
85 ((port_num / 3) * IPP_PORT_OFFSET) + IPP_PORT_OFFSET))
86 #define IPP_PORT_ADDR(port_num)\
87 ((port_num == 0) ? FZC_IPP: \
88 FZC_IPP + (((port_num % 2) * IPP_PORT_OFFSET) + \
89 ((port_num / 3) * IPP_PORT_OFFSET) + IPP_PORT_OFFSET))
90
91 /* IPP Configuration Register */
92
93 #define IPP_SOFT_RESET (1ULL << 31)
94 #define IPP_IP_MAX_PKT_BYTES_SHIFT 8
95 #define IPP_IP_MAX_PKT_BYTES_MASK 0x1FFFF
96 #define IPP_FFLP_CKSUM_INFO_PIO_WR_EN (1 << 7)
97 #define IPP_PRE_FIFO_PIO_WR_EN (1 << 6)
98 #define IPP_DFIFO_PIO_WR_EN (1 << 5)
99 #define IPP_TCP_UDP_CKSUM_EN (1 << 4)
100 #define IPP_DROP_BAD_CRC_EN (1 << 3)
101 #define IPP_DFIFO_ECC_CORRECT_EN (1 << 2)
102 #define IPP_EN (1 << 0)
103
104 /* IPP Interrupt Status Registers */
105
106 #define IPP_DFIFO_MISSED_SOP (1ULL << 31)
107 #define IPP_DFIFO_MISSED_EOP (1 << 30)
108 #define IPP_DFIFO_ECC_UNCORR_ERR_MASK 0x3
109 #define IPP_DFIFO_ECC_UNCORR_ERR_SHIFT 28
110 #define IPP_DFIFO_ECC_CORR_ERR_MASK 0x3
111 #define IPP_DFIFO_ECC_CORR_ERR_SHIFT 26
112 #define IPP_DFIFO_ECC_ERR_MASK 0x3
113 #define IPP_DFIFO_ECC_ERR_SHIFT 24
114 #define IPP_DFIFO_NO_ECC_ERR (1 << 23)
115 #define IPP_DFIFO_ECC_ERR_ENTRY_INDEX_MASK 0x7FF
116 #define IPP_DFIFO_ECC_ERR_ENTRY_INDEX_SHIFT 12
117 #define IPP_PRE_FIFO_PERR (1 << 11)
118 #define IPP_ECC_ERR_CNT_MAX (1 << 10)
119 #define IPP_PRE_FIFO_PERR_ENTRY_INDEX_MASK 0x3F
120 #define IPP_PRE_FIFO_PERR_ENTRY_INDEX_SHIFT 4
121 #define IPP_PRE_FIFO_OVERRUN (1 << 3)
122 #define IPP_PRE_FIFO_UNDERRUN (1 << 2)
123 #define IPP_BAD_TCPIP_CHKSUM_CNT_MAX (1 << 1)
124 #define IPP_PKT_DISCARD_CNT_MAX (1 << 0)
125
126 #define IPP_P0_P1_DFIFO_ENTRIES 2048
127 #define IPP_P2_P3_DFIFO_ENTRIES 1024
128 #define IPP_NIU_DFIFO_ENTRIES 1024
129
130 typedef union _ipp_status {
131 uint64_t value;
132
133 struct {
134 #if defined(_BIG_ENDIAN)
135 uint32_t w1;
136 #endif
137 struct {
138 #if defined(_BIT_FIELDS_HTOL)
139 uint32_t dfifo_missed_sop : 1;
140 uint32_t dfifo_missed_eop : 1;
141 uint32_t dfifo_uncorr_ecc_err : 2;
142 uint32_t dfifo_corr_ecc_err : 2;
143 uint32_t dfifo_ecc_err : 2;
144 uint32_t dfifo_no_ecc_err : 1;
145 uint32_t dfifo_ecc_err_idx : 11;
146 uint32_t pre_fifo_perr : 1;
147 uint32_t ecc_err_cnt_ovfl : 1;
148 uint32_t pre_fifo_perr_idx : 6;
149 uint32_t pre_fifo_overrun : 1;
150 uint32_t pre_fifo_underrun : 1;
151 uint32_t bad_cksum_cnt_ovfl : 1;
152 uint32_t pkt_discard_cnt_ovfl : 1;
153 #elif defined(_BIT_FIELDS_LTOH)
154 uint32_t pkt_discard_cnt_ovfl : 1;
155 uint32_t bad_cksum_cnt_ovfl : 1;
156 uint32_t pre_fifo_underrun : 1;
157 uint32_t pre_fifo_overrun : 1;
158 uint32_t pre_fifo_perr_idx : 6;
159 uint32_t ecc_err_cnt_ovfl : 1;
160 uint32_t pre_fifo_perr : 1;
161 uint32_t dfifo_ecc_err_idx : 11;
162 uint32_t dfifo_no_ecc_err : 1;
163 uint32_t dfifo_ecc_err : 2;
164 uint32_t dfifo_corr_ecc_err : 2;
165 uint32_t dfifo_uncorr_ecc_err : 2;
166 uint32_t dfifo_missed_eop : 1;
167 uint32_t dfifo_missed_sop : 1;
168 #else
169 #error one of _BIT_FIELDS_HTOL or _BIT_FIELDS_LTOH must be defined
170 #endif
171 } w0;
172
173 #if !defined(_BIG_ENDIAN)
174 uint32_t w1;
175 #endif
176 } bits;
177 } ipp_status_t;
178
179 typedef union _ipp_ecc_ctrl {
180 uint64_t value;
181
182 struct {
183 #if defined(_BIG_ENDIAN)
184 uint32_t w1;
185 #endif
186 struct {
187 #if defined(_BIT_FIELDS_HTOL)
188 uint32_t dis_dbl : 1;
189 uint32_t res3 : 13;
190 uint32_t cor_dbl : 1;
191 uint32_t cor_sng : 1;
192 uint32_t rsvd : 5;
193 uint32_t cor_all : 1;
194 uint32_t res2 : 1;
195 uint32_t cor_1 : 1;
196 uint32_t res1 : 5;
197 uint32_t cor_lst : 1;
198 uint32_t cor_snd : 1;
199 uint32_t cor_fst : 1;
200 #elif defined(_BIT_FIELDS_LTOH)
201 uint32_t cor_fst : 1;
202 uint32_t cor_snd : 1;
203 uint32_t cor_lst : 1;
204 uint32_t res1 : 5;
205 uint32_t cor_1 : 1;
206 uint32_t res2 : 1;
207 uint32_t cor_all : 1;
208 uint32_t rsvd : 5;
209 uint32_t cor_sng : 1;
210 uint32_t cor_dbl : 1;
211 uint32_t res3 : 13;
212 uint32_t dis_dbl : 1;
213 #else
214 #error one of _BIT_FIELDS_HTOL or _BIT_FIELDS_LTOH must be defined
215 #endif
216 } w0;
217
218 #if !defined(_BIG_ENDIAN)
219 uint32_t w1;
220 #endif
221 } bits;
222 } ipp_ecc_ctrl_t;
223
224
225 /* IPP Interrupt Mask Registers */
226
227 #define IPP_ECC_ERR_CNT_MAX_INTR_DIS (1 << 7)
228 #define IPP_DFIFO_MISSING_EOP_SOP_INTR_DIS (1 << 6)
229 #define IPP_DFIFO_ECC_UNCORR_ERR_INTR_DIS (1 << 5)
230 #define IPP_PRE_FIFO_PERR_INTR_DIS (1 << 4)
231 #define IPP_PRE_FIFO_OVERRUN_INTR_DIS (1 << 3)
232 #define IPP_PRE_FIFO_UNDERRUN_INTR_DIS (1 << 2)
233 #define IPP_BAD_TCPIP_CKSUM_CNT_INTR_DIS (1 << 1)
234 #define IPP_PKT_DISCARD_CNT_INTR_DIS (1 << 0)
235
236 #define IPP_RESET_WAIT 10
237
238 /* DFIFO RD/WR pointers mask */
239
240 #define IPP_XMAC_DFIFO_PTR_MASK 0x7FF
241 #define IPP_BMAC_DFIFO_PTR_MASK 0x3FF
242
243 #define IPP_ECC_CNT_MASK 0xFF
244 #define IPP_BAD_CS_CNT_MASK 0x3FFF
245 #define IPP_PKT_DIS_CNT_MASK 0x3FFF
246
247 #ifdef __cplusplus
248 }
249 #endif
250
251 #endif /* _SYS_NXGE_NXGE_IPP_HW_H */
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