include/sys/nxge/nxge_espc_hw.h

   1 /*
   2  * CDDL HEADER START
   3  *
   4  * The contents of this file are subject to the terms of the
   5  * Common Development and Distribution License (the "License").
   6  * You may not use this file except in compliance with the License.
   7  *
   8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
   9  * or http://www.opensolaris.org/os/licensing.
  10  * See the License for the specific language governing permissions
  11  * and limitations under the License.
  12  *
  13  * When distributing Covered Code, include this CDDL HEADER in each
  14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
  15  * If applicable, add the following below this CDDL HEADER, with the
  16  * fields enclosed by brackets "[]" replaced with your own identifying
  17  * information: Portions Copyright [yyyy] [name of copyright owner]
  18  *
  19  * CDDL HEADER END
  20  */
  21 /*
  22  * Copyright 2006 Sun Microsystems, Inc.  All rights reserved.
  23  * Use is subject to license terms.
  24  */
  25
  26 #ifndef _SYS_NXGE_NXGE_ESPC_HW_H
  27 #define _SYS_NXGE_NXGE_ESPC_HW_H
  28
  29 #pragma ident   "%Z%%M% %I%     %E% SMI"
  30
  31 #ifdef  __cplusplus
  32 extern "C" {
  33 #endif
  34
  35 #include <nxge_defs.h>
  36
  37 /* EPC / SPC Registers offsets */
  38 #define ESPC_PIO_EN_REG         0x040000
  39 #define ESPC_PIO_EN_MASK        0x0000000000000001ULL
  40 #define ESPC_PIO_STATUS_REG     0x040008
  41
  42 /* EPC Status Register */
  43 #define EPC_READ_INITIATE       (1ULL << 31)
  44 #define EPC_READ_COMPLETE       (1 << 30)
  45 #define EPC_WRITE_INITIATE      (1 << 29)
  46 #define EPC_WRITE_COMPLETE      (1 << 28)
  47 #define EPC_EEPROM_ADDR_BITS    0x3FFFF
  48 #define EPC_EEPROM_ADDR_SHIFT   8
  49 #define EPC_EEPROM_ADDR_MASK    (EPC_EEPROM_ADDR_BITS << EPC_EEPROM_ADDR_SHIFT)
  50 #define EPC_EEPROM_DATA_MASK    0xFF
  51
  52 #define EPC_RW_WAIT             10      /* TBD */
  53
  54 #define ESPC_NCR_REG            0x040020   /* Count 128, step 8 */
  55 #define ESPC_REG_ADDR(reg)      (FZC_PROM + (reg))
  56
  57 #define ESPC_NCR_REGN(n)        ((ESPC_REG_ADDR(ESPC_NCR_REG)) + n*8)
  58 #define ESPC_NCR_VAL_MASK       0x00000000FFFFFFFFULL
  59
  60 #ifdef __cplusplus
  61 }
  62 #endif
  63
  64 #endif  /* _SYS_NXGE_NXGE_ESPC_HW_H */