kernel/drivers/scsi/cpqary3/cpqary3_ioctl.h

   1 /*
   2  * This file and its contents are supplied under the terms of the
   3  * Common Development and Distribution License ("CDDL"), version 1.0.
   4  * You may only use this file in accordance with the terms of version
   5  * 1.0 of the CDDL.
   6  *
   7  * A full copy of the text of the CDDL should have accompanied this
   8  * source.  A copy of the CDDL is also available via the Internet at
   9  * http://www.illumos.org/license/CDDL.
  10  */
  11
  12 /*
  13  * Copyright (C) 2013 Hewlett-Packard Development Company, L.P.
  14  */
  15
  16 #ifndef _CPQARY3_IOCTL_H
  17 #define _CPQARY3_IOCTL_H
  18
  19 #ifdef  __cplusplus
  20 extern "C" {
  21 #endif
  22
  23 /*
  24  * USED in Ioctls
  25  */
  26
  27 #define CPQARY3_SCSI_IN         0
  28 #define CPQARY3_SCSI_OUT        1
  29 #define CPQARY3_NODATA_XFER     2
  30 #define SUCCESS                 0
  31 #define FAILURE                 -1
  32
  33 /* for SAS support */
  34 /* BMIC Commands */
  35 #define HPSAS_ID_LOG_DRIVE              0x10
  36 #define HPSAS_ID_CONTROLLER             0x11
  37 #define HPSAS_SENSE_LOG_DRIVE           0x12
  38 #define HPSAS_ID_PHYSICAL_DRIVE         0x15
  39 #define HPSAS_READ                      0x20
  40 #define HPSAS_WRITE                     0x30
  41 #define HPSAS_WRITE_THROUGH             0x31
  42 #define HPSAS_SENSE_CONFIG              0x50
  43 #define HPSAS_SET_CONFIG                0x51
  44 #define HPSAS_BYPASS_VOL_STATE          0x52
  45 #define HPSAS_CHANGE_CONFIG             0x54
  46 #define HPSAS_SENSE_ORIG_CONFIG         0x55
  47 #define HPSAS_LABEL_LOG_DRIVE           0x57
  48 #define HPSAS_SENSE_BUS_PARAMS          0x65
  49 #define HPSAS_TAPE_INQUIRY              0x92
  50 #define HPSAS_RESUME_BKGND_ACTIVITY     0x99
  51 #define HPSAS_SENSE_MP_STAT             0xA0
  52 #define HPSAS_SET_MP_THRESHOLD          0xA1
  53 #define HPSAS_MP_PARAM_CONTROL          0xA4
  54 #define HPSAS_SENSE_DRV_ERR_LOG         0xA6
  55 #define HPSAS_FLUSH_CACHE               0xc2
  56 #define HPSAS_REPORT_LOGICAL_LUN        0xC2
  57 #define HPSAS_REPORT_PHYSICAL_LUN       0xC3
  58 #define HPSAS_SET_MP_VALUE              0xF3
  59 #define HPSAS_BMIC_CMD_LEN              16
  60
  61
  62 #pragma pack(1)
  63
  64 typedef struct cpqary3_ioctl_request {
  65         uint32_t        len;            /* Data Buffer length */
  66         uint32_t        reserved;       /* For future enhancements */
  67         uint64_t        argp;           /* Data or data Buffer of the request */
  68 } cpqary3_ioctl_request_t;
  69
  70 typedef struct cpqary3_drvrev {
  71         uint8_t         minor;          /* Version info */
  72         uint8_t         major;
  73         uint8_t         mm;             /* Revision Date */
  74         uint8_t         dd;
  75         uint16_t        yyyy;
  76 } cpqary3_drvrev_t;
  77
  78 typedef struct cpqary3_driver_info {
  79         int8_t          name[16];       /* Null Term. ASCII driver name */
  80         cpqary3_drvrev_t version;       /* Driver version and revision */
  81         uint32_t        num_ctlr;       /* Num of ctlrs currently handled */
  82         uint32_t        max_num_ctlr;   /* Max num ctlrs supported */
  83         int8_t          reserved[98];   /* Structure size = 128 bytes */
  84 } cpqary3_driver_info_t;
  85
  86 typedef struct cpqary3_ctlr_info {
  87         uint16_t        state;          /* currently set to active */
  88         uint32_t        board_id;       /* controllers board_id */
  89         uint32_t        subsystem_id;   /* controllers subsystem_id */
  90         uint8_t         bus;            /* controllers PCI Bus number */
  91         uint8_t         dev : 5;        /* 5 bit device number */
  92         uint8_t         fun : 3;        /* 3 bit function number */
  93         uint16_t        slot_num;       /* physical slot number */
  94         uint8_t         num_of_tgts;    /* No of Logical Drives */
  95         uint32_t        controller_instance; /* Ap id number */
  96         int8_t          reserved[109];  /* Structure size = 128 bytes */
  97 } cpqary3_ctlr_info_t;
  98
  99 typedef struct cpqary3_bmic_pass {
 100         uint8_t         lun_addr[8];    /* 8 byte LUN address */
 101         uint8_t         cmd;            /* BMIC command opcode */
 102         uint8_t         cmd_len;        /* BMIC command length */
 103         uint16_t        unit_number;    /* Unit number */
 104         uint32_t        blk_number;     /* BMIC Detail */
 105         uint16_t        bmic_index;     /* bmic_index */
 106         uint16_t        timeout;        /* timeout for command */
 107         uint8_t         io_direction;   /* IN(0) or OUT(1) */
 108         uint8_t         err_status;     /* command completion status */
 109         ErrorInfo_t     err_info;       /* error info */
 110         uint16_t        buf_len;        /* buffer/transfer length */
 111         uint64_t        buf;            /* buffer */
 112 } cpqary3_bmic_pass_t;
 113
 114 typedef struct cpqary3_scsi_pass {
 115         uint8_t         lun_addr[8];    /* 8 byte LUN address */
 116         uint8_t         cdb[16];        /* 16 byte CDB */
 117         uint8_t         cdb_len;        /* SCSI CDB length */
 118         uint16_t        timeout;        /* timeout for command */
 119         uint8_t         io_direction;   /* IN(0) or OUT(1) */
 120         uint8_t         err_status;     /* command completion status */
 121         ErrorInfo_t     err_info;       /* error info */
 122         uint16_t        buf_len;        /* buffer/transfer length */
 123         uint64_t        buf;            /* buffer */
 124 } cpqary3_scsi_pass_t;
 125
 126 #pragma pack()
 127
 128 #ifdef  __cplusplus
 129 }
 130 #endif
 131
 132 #endif  /* _CPQARY3_IOCTL_H */