usr/src/uts/sun4/ml/subr_asm.s

   1 /*
   2  * CDDL HEADER START
   3  *
   4  * The contents of this file are subject to the terms of the
   5  * Common Development and Distribution License (the "License").
   6  * You may not use this file except in compliance with the License.
   7  *
   8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
   9  * or http://www.opensolaris.org/os/licensing.
  10  * See the License for the specific language governing permissions
  11  * and limitations under the License.
  12  *
  13  * When distributing Covered Code, include this CDDL HEADER in each
  14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
  15  * If applicable, add the following below this CDDL HEADER, with the
  16  * fields enclosed by brackets "[]" replaced with your own identifying
  17  * information: Portions Copyright [yyyy] [name of copyright owner]
  18  *
  19  * CDDL HEADER END
  20  */
  21 /*
  22  * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
  23  * Use is subject to license terms.
  24  */
  25
  26 #pragma ident   "%Z%%M% %I%     %E% SMI"
  27
  28 /*
  29  * General machine architecture & implementation specific
  30  * assembly language routines.
  31  */
  32 #include "assym.h"
  33
  34 #include <sys/asm_linkage.h>
  35 #include <sys/async.h>
  36 #include <sys/machthread.h>
  37 #include <sys/vis.h>
  38 #include <sys/machsig.h>
  39
  40
  41         ENTRY(set_trap_table)
  42         set     trap_table, %o1
  43         rdpr    %tba, %o0
  44         wrpr    %o1, %tba
  45         retl
  46         wrpr    %g0, WSTATE_KERN, %wstate
  47         SET_SIZE(set_trap_table)
  48
  49
  50
  51         ! Store long word value at physical address
  52         !
  53         ! void  stdphys(uint64_t physaddr, uint64_t value)
  54         !
  55         ENTRY(stdphys)
  56         /*
  57          * disable interrupts, clear Address Mask to access 64 bit physaddr
  58          */
  59         rdpr    %pstate, %o4
  60         andn    %o4, PSTATE_IE | PSTATE_AM, %o5
  61         wrpr    %o5, 0, %pstate
  62         stxa    %o1, [%o0]ASI_MEM
  63         retl
  64         wrpr    %g0, %o4, %pstate       ! restore earlier pstate register value
  65         SET_SIZE(stdphys)
  66
  67
  68         ! Store long word value at physical i/o address
  69         !
  70         ! void  stdphysio(u_longlong_t physaddr, u_longlong_t value)
  71         !
  72         ENTRY(stdphysio)
  73         /*
  74          * disable interrupts, clear Address Mask to access 64 bit physaddr
  75          */
  76         rdpr    %pstate, %o4
  77         andn    %o4, PSTATE_IE | PSTATE_AM, %o5
  78         wrpr    %o5, 0, %pstate         ! clear IE, AM bits
  79         stxa    %o1, [%o0]ASI_IO
  80         retl
  81         wrpr    %g0, %o4, %pstate       ! restore earlier pstate register value
  82         SET_SIZE(stdphysio)
  83
  84
  85         !
  86         ! Load long word value at physical address
  87         !
  88         ! uint64_t lddphys(uint64_t physaddr)
  89         !
  90         ENTRY(lddphys)
  91         rdpr    %pstate, %o4
  92         andn    %o4, PSTATE_IE | PSTATE_AM, %o5
  93         wrpr    %o5, 0, %pstate
  94         ldxa    [%o0]ASI_MEM, %o0
  95         retl
  96         wrpr    %g0, %o4, %pstate       ! restore earlier pstate register value
  97         SET_SIZE(lddphys)
  98
  99         !
 100         ! Load long word value at physical i/o address
 101         !
 102         ! unsigned long long lddphysio(u_longlong_t physaddr)
 103         !
 104         ENTRY(lddphysio)
 105         rdpr    %pstate, %o4
 106         andn    %o4, PSTATE_IE | PSTATE_AM, %o5
 107         wrpr    %o5, 0, %pstate ! clear IE, AM bits
 108         ldxa    [%o0]ASI_IO, %o0
 109         retl
 110         wrpr    %g0, %o4, %pstate       ! restore earlier pstate register value
 111         SET_SIZE(lddphysio)
 112
 113         !
 114         ! Store value at physical address
 115         !
 116         ! void  stphys(uint64_t physaddr, int value)
 117         !
 118         ENTRY(stphys)
 119         rdpr    %pstate, %o4
 120         andn    %o4, PSTATE_IE | PSTATE_AM, %o5
 121         wrpr    %o5, 0, %pstate
 122         sta     %o1, [%o0]ASI_MEM
 123         retl
 124         wrpr    %g0, %o4, %pstate       ! restore earlier pstate register value
 125         SET_SIZE(stphys)
 126
 127
 128         !
 129         ! load value at physical address
 130         !
 131         ! int   ldphys(uint64_t physaddr)
 132         !
 133         ENTRY(ldphys)
 134         rdpr    %pstate, %o4
 135         andn    %o4, PSTATE_IE | PSTATE_AM, %o5
 136         wrpr    %o5, 0, %pstate
 137         lda     [%o0]ASI_MEM, %o0
 138         srl     %o0, 0, %o0     ! clear upper 32 bits
 139         retl
 140         wrpr    %g0, %o4, %pstate       ! restore earlier pstate register value
 141         SET_SIZE(ldphys)
 142
 143         !
 144         ! Store value into physical address in I/O space
 145         !
 146         ! void stphysio(u_longlong_t physaddr, uint_t value)
 147         !
 148         ENTRY_NP(stphysio)
 149         rdpr    %pstate, %o4            /* read PSTATE reg */
 150         andn    %o4, PSTATE_IE | PSTATE_AM, %o5
 151         wrpr    %o5, 0, %pstate
 152         stwa    %o1, [%o0]ASI_IO        /* store value via bypass ASI */
 153         retl
 154         wrpr    %g0, %o4, %pstate       /* restore the PSTATE */
 155         SET_SIZE(stphysio)
 156
 157         !
 158         ! Store value into physical address in I/O space
 159         !
 160         ! void sthphysio(u_longlong_t physaddr, ushort_t value)
 161         !
 162         ENTRY_NP(sthphysio)
 163         rdpr    %pstate, %o4            /* read PSTATE reg */
 164         andn    %o4, PSTATE_IE | PSTATE_AM, %o5
 165         wrpr    %o5, 0, %pstate
 166         stha    %o1, [%o0]ASI_IO        /* store value via bypass ASI */
 167         retl
 168         wrpr    %g0, %o4, %pstate               /* restore the PSTATE */
 169         SET_SIZE(sthphysio)
 170
 171         !
 172         ! Store value into one byte physical address in I/O space
 173         !
 174         ! void stbphysio(u_longlong_t physaddr, uchar_t value)
 175         !
 176         ENTRY_NP(stbphysio)
 177         rdpr    %pstate, %o4            /* read PSTATE reg */
 178         andn    %o4, PSTATE_IE | PSTATE_AM, %o5
 179         wrpr    %o5, 0, %pstate
 180         stba    %o1, [%o0]ASI_IO        /* store byte via bypass ASI */
 181         retl
 182         wrpr    %g0, %o4, %pstate       /* restore the PSTATE */
 183         SET_SIZE(stbphysio)
 184
 185         !
 186         ! load value at physical address in I/O space
 187         !
 188         ! uint_t   ldphysio(u_longlong_t physaddr)
 189         !
 190         ENTRY_NP(ldphysio)
 191         rdpr    %pstate, %o4            /* read PSTATE reg */
 192         andn    %o4, PSTATE_IE | PSTATE_AM, %o5
 193         wrpr    %o5, 0, %pstate
 194         lduwa   [%o0]ASI_IO, %o0        /* load value via bypass ASI */
 195         retl
 196         wrpr    %g0, %o4, %pstate       /* restore pstate */
 197         SET_SIZE(ldphysio)
 198
 199         !
 200         ! load value at physical address in I/O space
 201         !
 202         ! ushort_t   ldhphysio(u_longlong_t physaddr)
 203         !
 204         ENTRY_NP(ldhphysio)
 205         rdpr    %pstate, %o4            /* read PSTATE reg */
 206         andn    %o4, PSTATE_IE | PSTATE_AM, %o5
 207         wrpr    %o5, 0, %pstate
 208         lduha   [%o0]ASI_IO, %o0        /* load value via bypass ASI */
 209         retl
 210         wrpr    %g0, %o4, %pstate       /* restore pstate */
 211         SET_SIZE(ldhphysio)
 212
 213         !
 214         ! load byte value at physical address in I/O space
 215         !
 216         ! uchar_t   ldbphysio(u_longlong_t physaddr)
 217         !
 218         ENTRY_NP(ldbphysio)
 219         rdpr    %pstate, %o4            /* read PSTATE reg */
 220         andn    %o4, PSTATE_IE | PSTATE_AM, %o5
 221         wrpr    %o5, 0, %pstate
 222         lduba   [%o0]ASI_IO, %o0        /* load value via bypass ASI */
 223         retl
 224         wrpr    %g0, %o4, %pstate       /* restore pstate */
 225         SET_SIZE(ldbphysio)
 226
 227 /*
 228  * save_gsr(kfpu_t *fp)
 229  * Store the graphics status register
 230  */
 231
 232
 233         ENTRY_NP(save_gsr)
 234         rd      %gsr, %g2                       ! save gsr
 235         retl
 236         stx     %g2, [%o0 + FPU_GSR]
 237         SET_SIZE(save_gsr)
 238
 239
 240
 241         ENTRY_NP(restore_gsr)
 242         ldx     [%o0 + FPU_GSR], %g2
 243         wr      %g2, %g0, %gsr
 244         retl
 245         nop
 246         SET_SIZE(restore_gsr)
 247
 248
 249 /*
 250  * uint64_t
 251  * _fp_read_pgsr()
 252  * Get the graphics status register info from fp and return it
 253  */
 254
 255
 256         ENTRY_NP(_fp_read_pgsr)
 257         retl
 258         rd      %gsr, %o0
 259         SET_SIZE(_fp_read_pgsr)
 260
 261
 262
 263 /*
 264  * uint64_t
 265  * get_gsr(kfpu_t *fp)
 266  * Get the graphics status register info from fp and return it
 267  */
 268
 269
 270         ENTRY_NP(get_gsr)
 271         retl
 272         ldx     [%o0 + FPU_GSR], %o0
 273         SET_SIZE(get_gsr)
 274
 275
 276 /*
 277  * _fp_write_pgsr(uint64_t *buf, kfpu_t *fp)
 278  * Set the graphics status register info to fp from buf
 279  */
 280
 281
 282         ENTRY_NP(_fp_write_pgsr)
 283         retl
 284         mov     %o0, %gsr
 285         SET_SIZE(_fp_write_pgsr)
 286
 287
 288 /*
 289  * set_gsr(uint64_t buf, kfpu_t *fp)
 290  * Set the graphics status register info to fp from buf
 291  */
 292
 293
 294         ENTRY_NP(set_gsr)
 295         retl
 296         stx     %o0, [%o1 + FPU_GSR]
 297         SET_SIZE(set_gsr)
 298
 299
 300
 301         ENTRY_NP(kdi_cpu_index)
 302         CPU_INDEX(%g1, %g2)
 303         jmp     %g7
 304         nop
 305         SET_SIZE(kdi_cpu_index)
 306
 307
 308
 309         ENTRY_NP(kmdb_enter)
 310         t       ST_KMDB_TRAP
 311         retl
 312         nop
 313         SET_SIZE(kmdb_enter)
 314
 315
 316 /*
 317  * The Spitfire floating point code has been changed not to use install/
 318  * save/restore/fork/freectx() because of the special memcpy library
 319  * routines, which will lose too much performance if they have to go
 320  * through the fp_disabled trap (which used to call installctx()). So
 321  * now fp_save/fp_restore are called from resume, and they don't care
 322  * whether floating point was enabled from the user program via the
 323  * fp_enabled trap or from the memcpy library, which just turns on floating
 324  * point in the fprs register itself. The new routine lwp_freeregs is
 325  * called everywhere freectx is called, and code was added to the sun4u-
 326  * specific version of lwp_forkregs (which is called everywhere forkctx
 327  * is called) to handle forking the floating point registers.
 328  *
 329  * Note that for the fprs dirty upper/lower bits are not used for now,
 330  * because the #instructions to determine if we need to use them is probably
 331  * greater than the #insructions just using them. This is a possible future
 332  * optimization, only do it with very careful benchmarking!
 333  *
 334  * The fp_fksave and and fp_load were split into two routines for the
 335  * sake of efficiency between the getfpregs/xregs_getfpregs and
 336  * setfpregs/xregs_setfpregs. But note that for saving and restoring
 337  * context, both *must* happen. For prmachdep, aka access from [k]adb,
 338  * it's OK if only one part happens.
 339  */
 340
 341 /*
 342  * fp_save(kfpu_t *fp)
 343  * fp_fksave(kfpu_t *fp)
 344  * Store the floating point registers.
 345  */
 346
 347
 348         ENTRY_NP(fp_save)
 349         ALTENTRY(fp_fksave)
 350         BSTORE_FPREGS(%o0, %o1)                 ! store V9 regs
 351         retl
 352         stx     %fsr, [%o0 + FPU_FSR]           ! store fsr
 353         SET_SIZE(fp_fksave)
 354         SET_SIZE(fp_save)
 355
 356
 357 /*
 358  * fp_v8_fksave(kfpu_t *fp)
 359  *
 360  * This is like the above routine but only saves the lower half.
 361  */
 362
 363
 364         ENTRY_NP(fp_v8_fksave)
 365         BSTORE_V8_FPREGS(%o0, %o1)              ! store V8 regs
 366         retl
 367         stx     %fsr, [%o0 + FPU_FSR]           ! store fsr
 368         SET_SIZE(fp_v8_fksave)
 369
 370
 371 /*
 372  * fp_v8p_fksave(kfpu_t *fp)
 373  *
 374  * This is like the above routine but only saves the upper half.
 375  */
 376
 377
 378         ENTRY_NP(fp_v8p_fksave)
 379         BSTORE_V8P_FPREGS(%o0, %o1)             ! store V9 extra regs
 380         retl
 381         stx     %fsr, [%o0 + FPU_FSR]           ! store fsr
 382         SET_SIZE(fp_v8p_fksave)
 383
 384
 385 /*
 386  * fp_restore(kfpu_t *fp)
 387  */
 388
 389
 390         ENTRY_NP(fp_restore)
 391         BLOAD_FPREGS(%o0, %o1)                  ! load V9 regs
 392         retl
 393         ldx     [%o0 + FPU_FSR], %fsr           ! restore fsr
 394         SET_SIZE(fp_restore)
 395
 396
 397 /*
 398  * fp_v8_load(kfpu_t *fp)
 399  */
 400
 401
 402         ENTRY_NP(fp_v8_load)
 403         BLOAD_V8_FPREGS(%o0, %o1)               ! load V8 regs
 404         retl
 405         ldx     [%o0 + FPU_FSR], %fsr           ! restore fsr
 406         SET_SIZE(fp_v8_load)
 407
 408
 409 /*
 410  * fp_v8p_load(kfpu_t *fp)
 411  */
 412
 413
 414         ENTRY_NP(fp_v8p_load)
 415         BLOAD_V8P_FPREGS(%o0, %o1)              ! load V9 extra regs
 416         retl
 417         ldx     [%o0 + FPU_FSR], %fsr           ! restore fsr
 418         SET_SIZE(fp_v8p_load)
 419