| blob | c21c392d77434cd49bf7f0fc47ead4db50c87a77 |
1 /*
2 *
3 * CDDL HEADER START
4 *
5 * The contents of this file are subject to the terms of the
6 * Common Development and Distribution License (the "License").
7 * You may not use this file except in compliance with the License.
8 *
9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
10 * or http://www.opensolaris.org/os/licensing.
11 * See the License for the specific language governing permissions
12 * and limitations under the License.
13 *
14 * When distributing Covered Code, include this CDDL HEADER in each
15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
16 * If applicable, add the following below this CDDL HEADER, with the
17 * fields enclosed by brackets "[]" replaced with your own identifying
18 * information: Portions Copyright [yyyy] [name of copyright owner]
19 *
20 * CDDL HEADER END
21 */
22 /*
23 * Copyright (c) 2003, 2010, Oracle and/or its affiliates. All rights reserved.
24 * Copyright (c) 2015, Joyent, Inc.
25 */
27 /*
28 * Copyright (c) 2010, Intel Corporation.
29 * All rights reserved.
30 */
32 /* Copyright (c) 1988 AT&T */
33 /* All Rights Reserved */
37 /* BEGIN CSTYLED */
39 /*
40 * Disassembly begins in dis_distable, which is equivalent to the One-byte
41 * Opcode Map in the Intel IA32 ISA Reference (page A-6 in my copy). The
42 * decoding loops then traverse out through the other tables as necessary to
43 * decode a given instruction.
44 *
45 * The behavior of this file can be controlled by one of the following flags:
46 *
47 * DIS_TEXT Include text for disassembly
48 * DIS_MEM Include memory-size calculations
49 *
50 * Either or both of these can be defined.
51 *
52 * This file is not, and will never be, cstyled. If anything, the tables should
53 * be taken out another tab stop or two so nothing overlaps.
54 */
56 /*
57 * These functions must be provided for the consumer to do disassembly.
58 */
59 #ifdef DIS_TEXT
65 #endif
69 /* field terminates - no pointer. */
71 /* Used to decode instructions. */
74 uchar_t it_adrmode;
75 #ifdef DIS_TEXT
78 #endif
79 #ifdef DIS_MEM
81 #endif
90 /*
91 * Instruction formats.
92 */
94 UNKNOWN,
95 MRw,
96 IMlw,
97 IMw,
98 IR,
99 OA,
100 AO,
101 MS,
102 SM,
103 Mv,
104 Mw,
109 PREF,
110 SWAPGS_RDTSCP,
111 MONITOR_MWAIT,
112 R,
113 RA,
114 SEG,
115 MR,
116 RM,
118 IA,
119 MA,
120 SD,
121 AD,
122 SA,
123 D,
124 INM,
125 SO,
126 BD,
127 I,
128 P,
129 V,
131 U,
132 OVERRIDE,
164 /*
165 * MMX/SIMD addressing modes.
166 */
216 XGETBV_XSETBV,
241 ADX /* ADX instructions, support REX.w, mod_rm->mod_reg */
242 };
244 /*
245 * VEX prefixes
246 */
252 /*
253 ** Register numbers for the i386
254 */
255 #define EAX_REGNO 0
256 #define ECX_REGNO 1
257 #define EDX_REGNO 2
258 #define EBX_REGNO 3
259 #define ESP_REGNO 4
260 #define EBP_REGNO 5
261 #define ESI_REGNO 6
262 #define EDI_REGNO 7
264 /*
265 * modes for immediate values
266 */
267 #define MODE_NONE 0
274 /*
275 * The letters used in these macros are:
276 * IND - indirect to another to another table
277 * "T" - means to Terminate indirections (this is the final opcode)
278 * "S" - means "operand length suffix required"
279 * "Sa" - means AVX2 suffix (d/q) required
280 * "NS" - means "no suffix" which is the operand length suffix of the opcode
281 * "Z" - means instruction size arg required
282 * "u" - means the opcode is invalid in IA32 but valid in amd64
283 * "x" - means the opcode is invalid in amd64, but not IA32
284 * "y" - means the operand size is always 64 bits in 64 bit mode
285 * "p" - means push/pop stack operation
286 * "vr" - means VEX instruction that operates on normal registers, not fpu
287 */
289 #if defined(DIS_TEXT) && defined(DIS_MEM)
292 #define TNS(name, amode) {TERM, amode, name, 0, 0, 0, 0, 0, 0}
293 #define TNSu(name, amode) {TERM, amode, name, 0, 0, 0, 0, 1, 0}
294 #define TNSx(name, amode) {TERM, amode, name, 0, 0, 1, 0, 0, 0}
295 #define TNSy(name, amode) {TERM, amode, name, 0, 0, 0, 1, 0, 0}
296 #define TNSyp(name, amode) {TERM, amode, name, 0, 0, 0, 1, 0, 1}
297 #define TNSZ(name, amode, sz) {TERM, amode, name, 0, sz, 0, 0, 0, 0}
298 #define TNSZy(name, amode, sz) {TERM, amode, name, 0, sz, 0, 1, 0, 0}
299 #define TNSZvr(name, amode, sz) {TERM, amode, name, 0, sz, 0, 0, 0, 0, 1}
300 #define TS(name, amode) {TERM, amode, name, 1, 0, 0, 0, 0, 0}
301 #define TSx(name, amode) {TERM, amode, name, 1, 0, 1, 0, 0, 0}
302 #define TSy(name, amode) {TERM, amode, name, 1, 0, 0, 1, 0, 0}
303 #define TSp(name, amode) {TERM, amode, name, 1, 0, 0, 0, 0, 1}
304 #define TSZ(name, amode, sz) {TERM, amode, name, 1, sz, 0, 0, 0, 0}
305 #define TSaZ(name, amode, sz) {TERM, amode, name, 1, sz, 0, 0, 0, 0, 0, 1}
306 #define TSZx(name, amode, sz) {TERM, amode, name, 1, sz, 1, 0, 0, 0}
307 #define TSZy(name, amode, sz) {TERM, amode, name, 1, sz, 0, 1, 0, 0}
309 #elif defined(DIS_TEXT)
312 #define TNS(name, amode) {TERM, amode, name, 0, 0, 0, 0, 0}
313 #define TNSu(name, amode) {TERM, amode, name, 0, 0, 0, 1, 0}
314 #define TNSx(name, amode) {TERM, amode, name, 0, 1, 0, 0, 0}
315 #define TNSy(name, amode) {TERM, amode, name, 0, 0, 1, 0, 0}
316 #define TNSyp(name, amode) {TERM, amode, name, 0, 0, 1, 0, 1}
317 #define TNSZ(name, amode, sz) {TERM, amode, name, 0, 0, 0, 0, 0}
318 #define TNSZy(name, amode, sz) {TERM, amode, name, 0, 0, 1, 0, 0}
319 #define TNSZvr(name, amode, sz) {TERM, amode, name, 0, 0, 0, 0, 0, 1}
320 #define TS(name, amode) {TERM, amode, name, 1, 0, 0, 0, 0}
321 #define TSx(name, amode) {TERM, amode, name, 1, 1, 0, 0, 0}
322 #define TSy(name, amode) {TERM, amode, name, 1, 0, 1, 0, 0}
323 #define TSp(name, amode) {TERM, amode, name, 1, 0, 0, 0, 1}
324 #define TSZ(name, amode, sz) {TERM, amode, name, 1, 0, 0, 0, 0}
325 #define TSaZ(name, amode, sz) {TERM, amode, name, 1, 0, 0, 0, 0, 0, 1}
326 #define TSZx(name, amode, sz) {TERM, amode, name, 1, 1, 0, 0, 0}
327 #define TSZy(name, amode, sz) {TERM, amode, name, 1, 0, 1, 0, 0}
329 #elif defined(DIS_MEM)
330 #define IND(table) {(instable_t *)table, 0, 0, 0, 0, 0, 0}
331 #define INDx(table) {(instable_t *)table, 0, 0, 1, 0, 0, 0}
332 #define TNS(name, amode) {TERM, amode, 0, 0, 0, 0, 0}
333 #define TNSu(name, amode) {TERM, amode, 0, 0, 0, 1, 0}
334 #define TNSy(name, amode) {TERM, amode, 0, 0, 1, 0, 0}
335 #define TNSyp(name, amode) {TERM, amode, 0, 0, 1, 0, 1}
336 #define TNSx(name, amode) {TERM, amode, 0, 1, 0, 0, 0}
337 #define TNSZ(name, amode, sz) {TERM, amode, sz, 0, 0, 0, 0}
338 #define TNSZy(name, amode, sz) {TERM, amode, sz, 0, 1, 0, 0}
339 #define TNSZvr(name, amode, sz) {TERM, amode, sz, 0, 0, 0, 0, 1}
340 #define TS(name, amode) {TERM, amode, 0, 0, 0, 0, 0}
341 #define TSx(name, amode) {TERM, amode, 0, 1, 0, 0, 0}
342 #define TSy(name, amode) {TERM, amode, 0, 0, 1, 0, 0}
343 #define TSp(name, amode) {TERM, amode, 0, 0, 0, 0, 1}
344 #define TSZ(name, amode, sz) {TERM, amode, sz, 0, 0, 0, 0}
345 #define TSaZ(name, amode, sz) {TERM, amode, sz, 0, 0, 0, 0, 0, 1}
346 #define TSZx(name, amode, sz) {TERM, amode, sz, 1, 0, 0, 0}
347 #define TSZy(name, amode, sz) {TERM, amode, sz, 0, 1, 0, 0}
348 #define INVALID {TERM, UNKNOWN, 0, 0, 0, 0, 0}
349 #else
350 #define IND(table) {(instable_t *)table, 0, 0, 0, 0, 0}
351 #define INDx(table) {(instable_t *)table, 0, 1, 0, 0, 0}
352 #define TNS(name, amode) {TERM, amode, 0, 0, 0, 0}
353 #define TNSu(name, amode) {TERM, amode, 0, 0, 1, 0}
354 #define TNSy(name, amode) {TERM, amode, 0, 1, 0, 0}
355 #define TNSyp(name, amode) {TERM, amode, 0, 1, 0, 1}
356 #define TNSx(name, amode) {TERM, amode, 1, 0, 0, 0}
357 #define TNSZ(name, amode, sz) {TERM, amode, 0, 0, 0, 0}
358 #define TNSZy(name, amode, sz) {TERM, amode, 0, 1, 0, 0}
359 #define TNSZvr(name, amode, sz) {TERM, amode, 0, 0, 0, 0, 1}
360 #define TS(name, amode) {TERM, amode, 0, 0, 0, 0}
361 #define TSx(name, amode) {TERM, amode, 1, 0, 0, 0}
362 #define TSy(name, amode) {TERM, amode, 0, 1, 0, 0}
363 #define TSp(name, amode) {TERM, amode, 0, 0, 0, 1}
364 #define TSZ(name, amode, sz) {TERM, amode, 0, 0, 0, 0}
365 #define TSaZ(name, amode, sz) {TERM, amode, 0, 0, 0, 0, 0, 1}
366 #define TSZx(name, amode, sz) {TERM, amode, 1, 0, 0, 0}
367 #define TSZy(name, amode, sz) {TERM, amode, 0, 1, 0, 0}
368 #define INVALID {TERM, UNKNOWN, 0, 0, 0, 0}
369 #endif
371 #ifdef DIS_TEXT
372 /*
373 * this decodes the r_m field for mode's 0, 1, 2 in 16 bit mode
374 */
382 };
385 /*
386 * This decodes 32 bit addressing mode r_m field for modes 0, 1, 2
387 */
391 };
396 };
398 /*
399 * This decodes 64 bit addressing mode r_m field for modes 0, 1, 2
400 */
404 };
408 };
410 /*
411 * decode for scale from SIB byte
412 */
415 /*
416 * decode for scale from VSIB byte, note that we always include the scale factor
417 * to match gas.
418 */
421 /*
422 * register decoding for normal references to registers (ie. not addressing)
423 */
427 };
432 };
437 };
442 };
447 };
452 };
457 };
462 };
467 };
472 };
477 };
482 };
484 /*
485 * SIMD predicate suffixes
486 */
489 };
492 /*0 1 2 3 4 5 6 7*/
496 };
500 /*
501 * "decode table" for 64 bit mode MOVSXD instruction (opcode 0x63)
502 */
505 /*
506 * "decode table" for pause and clflush instructions
507 */
510 /*
511 * Decode table for 0x0F00 opcodes
512 */
517 };
520 /*
521 * Decode table for 0x0F01 opcodes
522 */
525 /* [0] */ TNSZ("sgdt",VMx,6), TNSZ("sidt",MONITOR_MWAIT,6), TNSZ("lgdt",XGETBV_XSETBV,6), TNSZ("lidt",SVM,6),
527 };
529 /*
530 * Decode table for 0x0F18 opcodes -- SIMD prefetch
531 */
534 /* [0] */ TNS("prefetchnta",PREF),TNS("prefetcht0",PREF), TNS("prefetcht1",PREF), TNS("prefetcht2",PREF),
536 };
538 /*
539 * Decode table for 0x0FAE opcodes -- SIMD state save/restore
540 */
543 /* [4] */ TNSZ("xsave",M,512), TNS("lfence",XMMFENCE), TNS("mfence",XMMFENCE), TNS("sfence",XMMSFNC),
544 };
546 /*
547 * Decode table for 0x0FBA opcodes
548 */
554 };
556 /*
557 * Decode table for 0x0FC7 opcode (group 9)
558 */
564 };
566 /*
567 * Decode table for 0x0FC7 opcode (group 9) mode 3
568 */
574 };
576 /*
577 * Decode table for 0x0FC7 opcode with 0x66 prefix
578 */
584 };
586 /*
587 * Decode table for 0x0FC7 opcode with 0xF3 prefix
588 */
594 };
596 /*
597 * Decode table for 0x0FC8 opcode -- 486 bswap instruction
598 *
599 *bit pattern: 0000 1111 1100 1reg
600 */
603 };
605 /*
606 * Decode table for 0x0F71, 0x0F72, and 0x0F73 opcodes -- MMX instructions
607 */
609 {
612 }, {
615 }, {
618 }, {
621 } };
623 /*
624 * Decode table for SIMD extensions to above 0x0F71-0x0F73 opcodes.
625 */
638 };
640 /*
641 * SIMD instructions have been wedged into the existing IA32 instruction
642 * set through the use of prefixes. That is, while 0xf0 0x58 may be
643 * addps, 0xf3 0xf0 0x58 (literally, repz addps) is a completely different
644 * instruction - addss. At present, three prefixes have been coopted in
645 * this manner - address size (0x66), repnz (0xf2) and repz (0xf3). The
646 * following tables are used to provide the prefixed instruction names.
647 * The arrays are sparse, but they're fast.
648 */
650 /*
651 * Decode table for SIMD instructions with the address size (0x66) prefix.
652 */
659 /* [10] */ TNSZ("movupd",XMM,16), TNSZ("movupd",XMMS,16), TNSZ("movlpd",XMMM,8), TNSZ("movlpd",XMMMS,8),
660 /* [14] */ TNSZ("unpcklpd",XMM,16),TNSZ("unpckhpd",XMM,16),TNSZ("movhpd",XMMM,8), TNSZ("movhpd",XMMMS,8),
666 /* [28] */ TNSZ("movapd",XMM,16), TNSZ("movapd",XMMS,16), TNSZ("cvtpi2pd",XMMOMX,8),TNSZ("movntpd",XMMOMS,16),
667 /* [2C] */ TNSZ("cvttpd2pi",XMMXMM,16),TNSZ("cvtpd2pi",XMMXMM,16),TNSZ("ucomisd",XMM,8),TNSZ("comisd",XMM,8),
680 /* [54] */ TNSZ("andpd",XMM,16), TNSZ("andnpd",XMM,16), TNSZ("orpd",XMM,16), TNSZ("xorpd",XMM,16),
681 /* [58] */ TNSZ("addpd",XMM,16), TNSZ("mulpd",XMM,16), TNSZ("cvtpd2ps",XMM,16),TNSZ("cvtps2dq",XMM,16),
682 /* [5C] */ TNSZ("subpd",XMM,16), TNSZ("minpd",XMM,16), TNSZ("divpd",XMM,16), TNSZ("maxpd",XMM,16),
684 /* [60] */ TNSZ("punpcklbw",XMM,16),TNSZ("punpcklwd",XMM,16),TNSZ("punpckldq",XMM,16),TNSZ("packsswb",XMM,16),
685 /* [64] */ TNSZ("pcmpgtb",XMM,16), TNSZ("pcmpgtw",XMM,16), TNSZ("pcmpgtd",XMM,16), TNSZ("packuswb",XMM,16),
686 /* [68] */ TNSZ("punpckhbw",XMM,16),TNSZ("punpckhwd",XMM,16),TNSZ("punpckhdq",XMM,16),TNSZ("packssdw",XMM,16),
687 /* [6C] */ TNSZ("punpcklqdq",XMM,16),TNSZ("punpckhqdq",XMM,16),TNSZ("movd",XMM3MX,4),TNSZ("movdqa",XMM,16),
720 /* [D4] */ TNSZ("paddq",XMM,16), TNSZ("pmullw",XMM,16), TNSZ("movq",XMMS,8), TNS("pmovmskb",XMMX3),
721 /* [D8] */ TNSZ("psubusb",XMM,16), TNSZ("psubusw",XMM,16), TNSZ("pminub",XMM,16), TNSZ("pand",XMM,16),
722 /* [DC] */ TNSZ("paddusb",XMM,16), TNSZ("paddusw",XMM,16), TNSZ("pmaxub",XMM,16), TNSZ("pandn",XMM,16),
724 /* [E0] */ TNSZ("pavgb",XMM,16), TNSZ("psraw",XMM,16), TNSZ("psrad",XMM,16), TNSZ("pavgw",XMM,16),
725 /* [E4] */ TNSZ("pmulhuw",XMM,16), TNSZ("pmulhw",XMM,16), TNSZ("cvttpd2dq",XMM,16),TNSZ("movntdq",XMMS,16),
726 /* [E8] */ TNSZ("psubsb",XMM,16), TNSZ("psubsw",XMM,16), TNSZ("pminsw",XMM,16), TNSZ("por",XMM,16),
727 /* [EC] */ TNSZ("paddsb",XMM,16), TNSZ("paddsw",XMM,16), TNSZ("pmaxsw",XMM,16), TNSZ("pxor",XMM,16),
730 /* [F4] */ TNSZ("pmuludq",XMM,16), TNSZ("pmaddwd",XMM,16), TNSZ("psadbw",XMM,16), TNSZ("maskmovdqu", XMMXIMPL,16),
731 /* [F8] */ TNSZ("psubb",XMM,16), TNSZ("psubw",XMM,16), TNSZ("psubd",XMM,16), TNSZ("psubq",XMM,16),
733 };
741 /* [10] */ TNSZ("vmovupd",VEX_MX,16), TNSZ("vmovupd",VEX_RX,16), TNSZ("vmovlpd",VEX_RMrX,8), TNSZ("vmovlpd",VEX_RM,8),
742 /* [14] */ TNSZ("vunpcklpd",VEX_RMrX,16),TNSZ("vunpckhpd",VEX_RMrX,16),TNSZ("vmovhpd",VEX_RMrX,8), TNSZ("vmovhpd",VEX_RM,8),
748 /* [28] */ TNSZ("vmovapd",VEX_MX,16), TNSZ("vmovapd",VEX_RX,16), INVALID, TNSZ("vmovntpd",VEX_RM,16),
762 /* [54] */ TNSZ("vandpd",VEX_RMrX,16), TNSZ("vandnpd",VEX_RMrX,16), TNSZ("vorpd",VEX_RMrX,16), TNSZ("vxorpd",VEX_RMrX,16),
763 /* [58] */ TNSZ("vaddpd",VEX_RMrX,16), TNSZ("vmulpd",VEX_RMrX,16), TNSZ("vcvtpd2ps",VEX_MX,16),TNSZ("vcvtps2dq",VEX_MX,16),
764 /* [5C] */ TNSZ("vsubpd",VEX_RMrX,16), TNSZ("vminpd",VEX_RMrX,16), TNSZ("vdivpd",VEX_RMrX,16), TNSZ("vmaxpd",VEX_RMrX,16),
766 /* [60] */ TNSZ("vpunpcklbw",VEX_RMrX,16),TNSZ("vpunpcklwd",VEX_RMrX,16),TNSZ("vpunpckldq",VEX_RMrX,16),TNSZ("vpacksswb",VEX_RMrX,16),
767 /* [64] */ TNSZ("vpcmpgtb",VEX_RMrX,16), TNSZ("vpcmpgtw",VEX_RMrX,16), TNSZ("vpcmpgtd",VEX_RMrX,16), TNSZ("vpackuswb",VEX_RMrX,16),
768 /* [68] */ TNSZ("vpunpckhbw",VEX_RMrX,16),TNSZ("vpunpckhwd",VEX_RMrX,16),TNSZ("vpunpckhdq",VEX_RMrX,16),TNSZ("vpackssdw",VEX_RMrX,16),
769 /* [6C] */ TNSZ("vpunpcklqdq",VEX_RMrX,16),TNSZ("vpunpckhqdq",VEX_RMrX,16),TNSZ("vmovd",VEX_MX,4),TNSZ("vmovdqa",VEX_MX,16),
771 /* [70] */ TNSZ("vpshufd",VEX_MXI,16), TNSZ("vgrp71",VEX_XXI,16), TNSZ("vgrp72",VEX_XXI,16), TNSZ("vgrp73",VEX_XXI,16),
772 /* [74] */ TNSZ("vpcmpeqb",VEX_RMrX,16), TNSZ("vpcmpeqw",VEX_RMrX,16), TNSZ("vpcmpeqd",VEX_RMrX,16), INVALID,
774 /* [7C] */ TNSZ("vhaddpd",VEX_RMrX,16), TNSZ("vhsubpd",VEX_RMrX,16), TNSZ("vmovd",VEX_RR,4), TNSZ("vmovdqa",VEX_RX,16),
797 /* [C4] */ TNSZ("vpinsrw",VEX_RMRX,2),TNS("vpextrw",VEX_MR), TNSZ("vshufpd",VEX_RMRX,16), INVALID,
801 /* [D0] */ TNSZ("vaddsubpd",VEX_RMrX,16),TNSZ("vpsrlw",VEX_RMrX,16), TNSZ("vpsrld",VEX_RMrX,16), TNSZ("vpsrlq",VEX_RMrX,16),
802 /* [D4] */ TNSZ("vpaddq",VEX_RMrX,16), TNSZ("vpmullw",VEX_RMrX,16), TNSZ("vmovq",VEX_RX,8), TNS("vpmovmskb",VEX_MR),
803 /* [D8] */ TNSZ("vpsubusb",VEX_RMrX,16), TNSZ("vpsubusw",VEX_RMrX,16), TNSZ("vpminub",VEX_RMrX,16), TNSZ("vpand",VEX_RMrX,16),
804 /* [DC] */ TNSZ("vpaddusb",VEX_RMrX,16), TNSZ("vpaddusw",VEX_RMrX,16), TNSZ("vpmaxub",VEX_RMrX,16), TNSZ("vpandn",VEX_RMrX,16),
806 /* [E0] */ TNSZ("vpavgb",VEX_RMrX,16), TNSZ("vpsraw",VEX_RMrX,16), TNSZ("vpsrad",VEX_RMrX,16), TNSZ("vpavgw",VEX_RMrX,16),
807 /* [E4] */ TNSZ("vpmulhuw",VEX_RMrX,16), TNSZ("vpmulhw",VEX_RMrX,16), TNSZ("vcvttpd2dq",VEX_MX,16),TNSZ("vmovntdq",VEX_RM,16),
808 /* [E8] */ TNSZ("vpsubsb",VEX_RMrX,16), TNSZ("vpsubsw",VEX_RMrX,16), TNSZ("vpminsw",VEX_RMrX,16), TNSZ("vpor",VEX_RMrX,16),
809 /* [EC] */ TNSZ("vpaddsb",VEX_RMrX,16), TNSZ("vpaddsw",VEX_RMrX,16), TNSZ("vpmaxsw",VEX_RMrX,16), TNSZ("vpxor",VEX_RMrX,16),
811 /* [F0] */ INVALID, TNSZ("vpsllw",VEX_RMrX,16), TNSZ("vpslld",VEX_RMrX,16), TNSZ("vpsllq",VEX_RMrX,16),
812 /* [F4] */ TNSZ("vpmuludq",VEX_RMrX,16), TNSZ("vpmaddwd",VEX_RMrX,16), TNSZ("vpsadbw",VEX_RMrX,16), TNS("vmaskmovdqu",VEX_MX),
813 /* [F8] */ TNSZ("vpsubb",VEX_RMrX,16), TNSZ("vpsubw",VEX_RMrX,16), TNSZ("vpsubd",VEX_RMrX,16), TNSZ("vpsubq",VEX_RMrX,16),
814 /* [FC] */ TNSZ("vpaddb",VEX_RMrX,16), TNSZ("vpaddw",VEX_RMrX,16), TNSZ("vpaddd",VEX_RMrX,16), INVALID,
815 };
817 /*
818 * Decode table for SIMD instructions with the repnz (0xf2) prefix.
819 */
900 };
908 /* [10] */ TNSZ("vmovsd",VEX_RMrX,8), TNSZ("vmovsd",VEX_RRX,8), TNSZ("vmovddup",VEX_MX,8), INVALID,
930 /* [58] */ TNSZ("vaddsd",VEX_RMrX,8), TNSZ("vmulsd",VEX_RMrX,8), TNSZ("vcvtsd2ss",VEX_RMrX,8), INVALID,
931 /* [5C] */ TNSZ("vsubsd",VEX_RMrX,8), TNSZ("vminsd",VEX_RMrX,8), TNSZ("vdivsd",VEX_RMrX,8), TNSZ("vmaxsd",VEX_RMrX,8),
982 };
1064 };
1143 /* [F4] */ INVALID, TNSZvr("pdep",VEX_RMrX,5),TNSZvr("mulx",VEX_RMrX,5),TNSZvr("shrx",VEX_VRMrX,5),
1146 };
1228 };
1229 /*
1230 * Decode table for SIMD instructions with the repz (0xf3) prefix.
1231 */
1260 /* [58] */ TNSZ("addss",XMM,4), TNSZ("mulss",XMM,4), TNSZ("cvtss2sd",XMM,4), TNSZ("cvttps2dq",XMM,16),
1312 };
1320 /* [10] */ TNSZ("vmovss",VEX_RMrX,4), TNSZ("vmovss",VEX_RRX,4), TNSZ("vmovsldup",VEX_MX,4), INVALID,
1340 /* [50] */ INVALID, TNSZ("vsqrtss",VEX_RMrX,4), TNSZ("vrsqrtss",VEX_RMrX,4), TNSZ("vrcpss",VEX_RMrX,4),
1342 /* [58] */ TNSZ("vaddss",VEX_RMrX,4), TNSZ("vmulss",VEX_RMrX,4), TNSZ("vcvtss2sd",VEX_RMrX,4), TNSZ("vcvttps2dq",VEX_MX,16),
1343 /* [5C] */ TNSZ("vsubss",VEX_RMrX,4), TNSZ("vminss",VEX_RMrX,4), TNSZ("vdivss",VEX_RMrX,4), TNSZ("vmaxss",VEX_RMrX,4),
1394 };
1395 /*
1396 * The following two tables are used to encode crc32 and movbe
1397 * since they share the same opcodes.
1398 */
1402 };
1407 };
1409 /*
1410 * The following table is used to distinguish between adox and adcx which share
1411 * the same opcodes.
1412 */
1416 };
1419 /* [00] */ TNSZ("pshufb",XMM_66o,16),TNSZ("phaddw",XMM_66o,16),TNSZ("phaddd",XMM_66o,16),TNSZ("phaddsw",XMM_66o,16),
1420 /* [04] */ TNSZ("pmaddubsw",XMM_66o,16),TNSZ("phsubw",XMM_66o,16), TNSZ("phsubd",XMM_66o,16),TNSZ("phsubsw",XMM_66o,16),
1421 /* [08] */ TNSZ("psignb",XMM_66o,16),TNSZ("psignw",XMM_66o,16),TNSZ("psignd",XMM_66o,16),TNSZ("pmulhrsw",XMM_66o,16),
1425 /* [14] */ TNSZ("blendvps",XMM_66r,16),TNSZ("blendvpd",XMM_66r,16),INVALID, TNSZ("ptest",XMM_66r,16),
1429 /* [20] */ TNSZ("pmovsxbw",XMM_66r,16),TNSZ("pmovsxbd",XMM_66r,16),TNSZ("pmovsxbq",XMM_66r,16),TNSZ("pmovsxwd",XMM_66r,16),
1431 /* [28] */ TNSZ("pmuldq",XMM_66r,16),TNSZ("pcmpeqq",XMM_66r,16),TNSZ("movntdqa",XMMM_66r,16),TNSZ("packusdw",XMM_66r,16),
1434 /* [30] */ TNSZ("pmovzxbw",XMM_66r,16),TNSZ("pmovzxbd",XMM_66r,16),TNSZ("pmovzxbq",XMM_66r,16),TNSZ("pmovzxwd",XMM_66r,16),
1435 /* [34] */ TNSZ("pmovzxwq",XMM_66r,16),TNSZ("pmovzxdq",XMM_66r,16),INVALID, TNSZ("pcmpgtq",XMM_66r,16),
1436 /* [38] */ TNSZ("pminsb",XMM_66r,16),TNSZ("pminsd",XMM_66r,16),TNSZ("pminuw",XMM_66r,16),TNSZ("pminud",XMM_66r,16),
1437 /* [3C] */ TNSZ("pmaxsb",XMM_66r,16),TNSZ("pmaxsd",XMM_66r,16),TNSZ("pmaxuw",XMM_66r,16),TNSZ("pmaxud",XMM_66r,16),
1487 /* [DC] */ TNSZ("aesenc",XMM_66r,16),TNSZ("aesenclast",XMM_66r,16),TNSZ("aesdec",XMM_66r,16),TNSZ("aesdeclast",XMM_66r,16),
1497 };
1500 /* [00] */ TNSZ("vpshufb",VEX_RMrX,16),TNSZ("vphaddw",VEX_RMrX,16),TNSZ("vphaddd",VEX_RMrX,16),TNSZ("vphaddsw",VEX_RMrX,16),
1501 /* [04] */ TNSZ("vpmaddubsw",VEX_RMrX,16),TNSZ("vphsubw",VEX_RMrX,16), TNSZ("vphsubd",VEX_RMrX,16),TNSZ("vphsubsw",VEX_RMrX,16),
1502 /* [08] */ TNSZ("vpsignb",VEX_RMrX,16),TNSZ("vpsignw",VEX_RMrX,16),TNSZ("vpsignd",VEX_RMrX,16),TNSZ("vpmulhrsw",VEX_RMrX,16),
1503 /* [0C] */ TNSZ("vpermilps",VEX_RMrX,8),TNSZ("vpermilpd",VEX_RMrX,16),TNSZ("vtestps",VEX_RRI,8), TNSZ("vtestpd",VEX_RRI,16),
1507 /* [18] */ TNSZ("vbroadcastss",VEX_MX,4),TNSZ("vbroadcastsd",VEX_MX,8),TNSZ("vbroadcastf128",VEX_MX,16),INVALID,
1510 /* [20] */ TNSZ("vpmovsxbw",VEX_MX,16),TNSZ("vpmovsxbd",VEX_MX,16),TNSZ("vpmovsxbq",VEX_MX,16),TNSZ("vpmovsxwd",VEX_MX,16),
1512 /* [28] */ TNSZ("vpmuldq",VEX_RMrX,16),TNSZ("vpcmpeqq",VEX_RMrX,16),TNSZ("vmovntdqa",VEX_MX,16),TNSZ("vpackusdw",VEX_RMrX,16),
1513 /* [2C] */ TNSZ("vmaskmovps",VEX_RMrX,8),TNSZ("vmaskmovpd",VEX_RMrX,16),TNSZ("vmaskmovps",VEX_RRM,8),TNSZ("vmaskmovpd",VEX_RRM,16),
1515 /* [30] */ TNSZ("vpmovzxbw",VEX_MX,16),TNSZ("vpmovzxbd",VEX_MX,16),TNSZ("vpmovzxbq",VEX_MX,16),TNSZ("vpmovzxwd",VEX_MX,16),
1516 /* [34] */ TNSZ("vpmovzxwq",VEX_MX,16),TNSZ("vpmovzxdq",VEX_MX,16),TNSZ("vpermd",VEX_RMrX,16),TNSZ("vpcmpgtq",VEX_RMrX,16),
1517 /* [38] */ TNSZ("vpminsb",VEX_RMrX,16),TNSZ("vpminsd",VEX_RMrX,16),TNSZ("vpminuw",VEX_RMrX,16),TNSZ("vpminud",VEX_RMrX,16),
1518 /* [3C] */ TNSZ("vpmaxsb",VEX_RMrX,16),TNSZ("vpmaxsd",VEX_RMrX,16),TNSZ("vpmaxuw",VEX_RMrX,16),TNSZ("vpmaxud",VEX_RMrX,16),
1521 /* [44] */ INVALID, TSaZ("vpsrlv",VEX_RMrX,16),TNSZ("vpsravd",VEX_RMrX,16),TSaZ("vpsllv",VEX_RMrX,16),
1527 /* [58] */ TNSZ("vpbroadcastd",VEX_MX,16),TNSZ("vpbroadcastq",VEX_MX,16),TNSZ("vbroadcasti128",VEX_MX,16),INVALID,
1545 /* [90] */ TNSZ("vpgatherd",VEX_SbVM,16),TNSZ("vpgatherq",VEX_SbVM,16),TNSZ("vgatherdp",VEX_SbVM,16),TNSZ("vgatherqp",VEX_SbVM,16),
1547 /* [98] */ TNSZ("vfmadd132p",FMA,16),TNSZ("vfmadd132s",FMA,16),TNSZ("vfmsub132p",FMA,16),TNSZ("vfmsub132s",FMA,16),
1548 /* [9C] */ TNSZ("vfnmadd132p",FMA,16),TNSZ("vfnmadd132s",FMA,16),TNSZ("vfnmsub132p",FMA,16),TNSZ("vfnmsub132s",FMA,16),
1552 /* [A8] */ TNSZ("vfmadd213p",FMA,16),TNSZ("vfmadd213s",FMA,16),TNSZ("vfmsub213p",FMA,16),TNSZ("vfmsub213s",FMA,16),
1553 /* [AC] */ TNSZ("vfnmadd213p",FMA,16),TNSZ("vfnmadd213s",FMA,16),TNSZ("vfnmsub213p",FMA,16),TNSZ("vfnmsub213s",FMA,16),
1557 /* [B8] */ TNSZ("vfmadd231p",FMA,16),TNSZ("vfmadd231s",FMA,16),TNSZ("vfmsub231p",FMA,16),TNSZ("vfmsub231s",FMA,16),
1558 /* [BC] */ TNSZ("vfnmadd231p",FMA,16),TNSZ("vfnmadd231s",FMA,16),TNSZ("vfnmsub231p",FMA,16),TNSZ("vfnmsub231s",FMA,16),
1568 /* [DC] */ TNSZ("vaesenc",VEX_RMrX,16),TNSZ("vaesenclast",VEX_RMrX,16),TNSZ("vaesdec",VEX_RMrX,16),TNSZ("vaesdeclast",VEX_RMrX,16),
1578 };
1583 /* [08] */ TNSZ("roundps",XMMP_66r,16),TNSZ("roundpd",XMMP_66r,16),TNSZ("roundss",XMMP_66r,16),TNSZ("roundsd",XMMP_66r,16),
1584 /* [0C] */ TNSZ("blendps",XMMP_66r,16),TNSZ("blendpd",XMMP_66r,16),TNSZ("pblendw",XMMP_66r,16),TNSZ("palignr",XMMP_66o,16),
1587 /* [14] */ TNSZ("pextrb",XMM3PM_66r,8),TNSZ("pextrw",XMM3PM_66r,16),TSZ("pextr",XMM3PM_66r,16),TNSZ("extractps",XMM3PM_66r,16),
1591 /* [20] */ TNSZ("pinsrb",XMMPRM_66r,8),TNSZ("insertps",XMMP_66r,16),TSZ("pinsr",XMMPRM_66r,16),INVALID,
1601 /* [40] */ TNSZ("dpps",XMMP_66r,16),TNSZ("dppd",XMMP_66r,16),TNSZ("mpsadbw",XMMP_66r,16),INVALID,
1611 /* [60] */ TNSZ("pcmpestrm",XMMP_66r,16),TNSZ("pcmpestri",XMMP_66r,16),TNSZ("pcmpistrm",XMMP_66r,16),TNSZ("pcmpistri",XMMP_66r,16),
1660 };
1663 /* [00] */ TNSZ("vpermq",VEX_MXI,16),TNSZ("vpermpd",VEX_MXI,16),TNSZ("vpblendd",VEX_RMRX,16),INVALID,
1664 /* [04] */ TNSZ("vpermilps",VEX_MXI,8),TNSZ("vpermilpd",VEX_MXI,16),TNSZ("vperm2f128",VEX_RMRX,16),INVALID,
1665 /* [08] */ TNSZ("vroundps",VEX_MXI,16),TNSZ("vroundpd",VEX_MXI,16),TNSZ("vroundss",VEX_RMRX,16),TNSZ("vroundsd",VEX_RMRX,16),
1666 /* [0C] */ TNSZ("vblendps",VEX_RMRX,16),TNSZ("vblendpd",VEX_RMRX,16),TNSZ("vpblendw",VEX_RMRX,16),TNSZ("vpalignr",VEX_RMRX,16),
1669 /* [14] */ TNSZ("vpextrb",VEX_RRi,8),TNSZ("vpextrw",VEX_RRi,16),TNSZ("vpextrd",VEX_RRi,16),TNSZ("vextractps",VEX_RM,16),
1673 /* [20] */ TNSZ("vpinsrb",VEX_RMRX,8),TNSZ("vinsertps",VEX_RMRX,16),TNSZ("vpinsrd",VEX_RMRX,16),INVALID,
1683 /* [40] */ TNSZ("vdpps",VEX_RMRX,16),TNSZ("vdppd",VEX_RMRX,16),TNSZ("vmpsadbw",VEX_RMRX,16),INVALID,
1693 /* [60] */ TNSZ("vpcmpestrm",VEX_MXI,16),TNSZ("vpcmpestri",VEX_MXI,16),TNSZ("vpcmpistrm",VEX_MXI,16),TNSZ("vpcmpistri",VEX_MXI,16),
1742 };
1744 /*
1745 * Decode table for 0x0F0D which uses the first byte of the mod_rm to
1746 * indicate a sub-code.
1747 */
1751 };
1753 /*
1754 * Decode table for 0x0F opcodes
1755 */
1758 {
1763 }, {
1764 /* [10] */ TNSZ("movups",XMMO,16), TNSZ("movups",XMMOS,16),TNSZ("movlps",XMMO,8), TNSZ("movlps",XMMOS,8),
1765 /* [14] */ TNSZ("unpcklps",XMMO,16),TNSZ("unpckhps",XMMO,16),TNSZ("movhps",XMMOM,8),TNSZ("movhps",XMMOMS,8),
1768 }, {
1771 /* [28] */ TNSZ("movaps",XMMO,16), TNSZ("movaps",XMMOS,16),TNSZ("cvtpi2ps",XMMOMX,8),TNSZ("movntps",XMMOS,16),
1772 /* [2C] */ TNSZ("cvttps2pi",XMMOXMM,8),TNSZ("cvtps2pi",XMMOXMM,8),TNSZ("ucomiss",XMMO,4),TNSZ("comiss",XMMO,4),
1773 }, {
1778 }, {
1783 }, {
1784 /* [50] */ TNS("movmskps",XMMOX3), TNSZ("sqrtps",XMMO,16), TNSZ("rsqrtps",XMMO,16),TNSZ("rcpps",XMMO,16),
1785 /* [54] */ TNSZ("andps",XMMO,16), TNSZ("andnps",XMMO,16), TNSZ("orps",XMMO,16), TNSZ("xorps",XMMO,16),
1786 /* [58] */ TNSZ("addps",XMMO,16), TNSZ("mulps",XMMO,16), TNSZ("cvtps2pd",XMMO,8),TNSZ("cvtdq2ps",XMMO,16),
1787 /* [5C] */ TNSZ("subps",XMMO,16), TNSZ("minps",XMMO,16), TNSZ("divps",XMMO,16), TNSZ("maxps",XMMO,16),
1788 }, {
1789 /* [60] */ TNSZ("punpcklbw",MMO,4),TNSZ("punpcklwd",MMO,4),TNSZ("punpckldq",MMO,4),TNSZ("packsswb",MMO,8),
1790 /* [64] */ TNSZ("pcmpgtb",MMO,8), TNSZ("pcmpgtw",MMO,8), TNSZ("pcmpgtd",MMO,8), TNSZ("packuswb",MMO,8),
1791 /* [68] */ TNSZ("punpckhbw",MMO,8),TNSZ("punpckhwd",MMO,8),TNSZ("punpckhdq",MMO,8),TNSZ("packssdw",MMO,8),
1792 /* [6C] */ TNSZ("INVALID",MMO,0), TNSZ("INVALID",MMO,0), TNSZ("movd",MMO,4), TNSZ("movq",MMO,8),
1793 }, {
1795 /* [74] */ TNSZ("pcmpeqb",MMO,8), TNSZ("pcmpeqw",MMO,8), TNSZ("pcmpeqd",MMO,8), TNS("emms",NORM),
1798 }, {
1803 }, {
1808 }, {
1813 }, {
1818 }, {
1820 /* [C4] */ TNSZ("pinsrw",MMOPRM,2),TNS("pextrw",MMO3P), TNSZ("shufps",XMMOPM,16),IND(dis_op0FC7),
1823 }, {
1825 /* [D4] */ TNSZ("paddq",MMO,8), TNSZ("pmullw",MMO,8), TNSZ("INVALID",MMO,0), TNS("pmovmskb",MMOM3),
1826 /* [D8] */ TNSZ("psubusb",MMO,8), TNSZ("psubusw",MMO,8), TNSZ("pminub",MMO,8), TNSZ("pand",MMO,8),
1827 /* [DC] */ TNSZ("paddusb",MMO,8), TNSZ("paddusw",MMO,8), TNSZ("pmaxub",MMO,8), TNSZ("pandn",MMO,8),
1828 }, {
1830 /* [E4] */ TNSZ("pmulhuw",MMO,8), TNSZ("pmulhw",MMO,8), TNS("INVALID",XMMO), TNSZ("movntq",MMOMS,8),
1831 /* [E8] */ TNSZ("psubsb",MMO,8), TNSZ("psubsw",MMO,8), TNSZ("pminsw",MMO,8), TNSZ("por",MMO,8),
1832 /* [EC] */ TNSZ("paddsb",MMO,8), TNSZ("paddsw",MMO,8), TNSZ("pmaxsw",MMO,8), TNSZ("pxor",MMO,8),
1833 }, {
1835 /* [F4] */ TNSZ("pmuludq",MMO,8), TNSZ("pmaddwd",MMO,8), TNSZ("psadbw",MMO,8), TNSZ("maskmovq",MMOIMPL,8),
1838 } };
1841 {
1846 }, {
1847 /* [10] */ TNSZ("vmovups",VEX_MX,16), TNSZ("vmovups",VEX_RM,16),TNSZ("vmovlps",VEX_RMrX,8), TNSZ("vmovlps",VEX_RM,8),
1848 /* [14] */ TNSZ("vunpcklps",VEX_RMrX,16),TNSZ("vunpckhps",VEX_RMrX,16),TNSZ("vmovhps",VEX_RMrX,8),TNSZ("vmovhps",VEX_RM,8),
1851 }, {
1854 /* [28] */ TNSZ("vmovaps",VEX_MX,16), TNSZ("vmovaps",VEX_RX,16),INVALID, TNSZ("vmovntps",VEX_RM,16),
1856 }, {
1861 }, {
1866 }, {
1867 /* [50] */ TNS("vmovmskps",VEX_MR), TNSZ("vsqrtps",VEX_MX,16), TNSZ("vrsqrtps",VEX_MX,16),TNSZ("vrcpps",VEX_MX,16),
1868 /* [54] */ TNSZ("vandps",VEX_RMrX,16), TNSZ("vandnps",VEX_RMrX,16), TNSZ("vorps",VEX_RMrX,16), TNSZ("vxorps",VEX_RMrX,16),
1869 /* [58] */ TNSZ("vaddps",VEX_RMrX,16), TNSZ("vmulps",VEX_RMrX,16), TNSZ("vcvtps2pd",VEX_MX,8),TNSZ("vcvtdq2ps",VEX_MX,16),
1870 /* [5C] */ TNSZ("vsubps",VEX_RMrX,16), TNSZ("vminps",VEX_RMrX,16), TNSZ("vdivps",VEX_RMrX,16), TNSZ("vmaxps",VEX_RMrX,16),
1871 }, {
1876 }, {
1881 }, {
1886 }, {
1891 }, {
1896 }, {
1901 }, {
1906 }, {
1911 }, {
1916 }, {
1921 } };
1923 /*
1924 * Decode table for 0x80 opcodes
1925 */
1931 };
1934 /*
1935 * Decode table for 0x81 opcodes.
1936 */
1942 };
1945 /*
1946 * Decode table for 0x82 opcodes.
1947 */
1953 };
1954 /*
1955 * Decode table for 0x83 opcodes.
1956 */
1962 };
1964 /*
1965 * Decode table for 0xC0 opcodes.
1966 */
1972 };
1974 /*
1975 * Decode table for 0xD0 opcodes.
1976 */
1982 };
1984 /*
1985 * Decode table for 0xC1 opcodes.
1986 * 186 instruction set
1987 */
1993 };
1995 /*
1996 * Decode table for 0xD1 opcodes.
1997 */
2003 };
2006 /*
2007 * Decode table for 0xD2 opcodes.
2008 */
2014 };
2015 /*
2016 * Decode table for 0xD3 opcodes.
2017 */
2023 };
2026 /*
2027 * Decode table for 0xF6 opcodes.
2028 */
2034 };
2037 /*
2038 * Decode table for 0xF7 opcodes.
2039 */
2045 };
2048 /*
2049 * Decode table for 0xFE opcodes.
2050 */
2056 };
2057 /*
2058 * Decode table for 0xFF opcodes.
2059 */
2065 };
2067 /* for 287 instructions, which are a mess to decode */
2070 {
2071 /* bit pattern: 1101 1xxx MODxx xR/M */
2074 }, {
2077 }, {
2080 }, {
2083 }, {
2086 }, {
2089 }, {
2092 }, {
2095 } };
2098 {
2099 /* bit pattern: 1101 1xxx 11xx xREG */
2102 }, {
2105 }, {
2108 }, {
2111 }, {
2114 }, {
2117 }, {
2120 }, {
2123 } };
2126 {
2127 /* bit pattern: 1101 1001 111x xxxx */
2130 }, {
2133 }, {
2136 }, {
2139 } };
2142 /* bit pattern: 1101 1011 111x xxxx */
2145 };
2148 /* bit pattern: 1101 1011 11yy yxxx */
2151 };
2154 /* bit pattern: 1101 1010 11yy yxxx */
2157 };
2159 /*
2160 * Main decode table for the op codes. The first two nibbles
2161 * will be used as an index into the table. If there is a
2162 * a need to further decode an instruction, the array to be
2163 * referenced is indicated with the other two entries being
2164 * empty.
2165 */
2168 {
2173 }, {
2178 }, {
2183 }, {
2188 }, {
2193 }, {
2198 }, {
2199 /* [6,0] */ TSZx("pusha",IMPLMEM,28),TSZx("popa",IMPLMEM,28), TSx("bound",MR), TNS("arpl",RMw),
2202 /* [6,C] */ TNSZ("insb",IMPLMEM,1), TSZ("ins",IMPLMEM,4), TNSZ("outsb",IMPLMEM,1),TSZ("outs",IMPLMEM,4),
2203 }, {
2208 }, {
2213 }, {
2217 /* [9,C] */ TSZy("pushf",IMPLMEM,4),TSZy("popf",IMPLMEM,4), TNS("sahf",NORM), TNS("lahf",NORM),
2218 }, {
2223 }, {
2228 }, {
2233 }, {
2237 /* 287 instructions. Note that although the indirect field */
2238 /* indicates opFP1n2 for further decoding, this is not necessarily */
2239 /* the case since the opFP arrays are not partitioned according to key1 */
2240 /* and key2. opFP1n2 is given only to indicate that we haven't */
2241 /* finished decoding the instruction. */
2244 }, {
2249 }, {
2254 } };
2256 /* END CSTYLED */
2258 /*
2259 * common functions to decode and disassemble an x86 or amd64 instruction
2260 */
2262 /*
2263 * These are the individual fields of a REX prefix. Note that a REX
2264 * prefix with none of these set is still needed to:
2265 * - use the MOVSXD (sign extend 32 to 64 bits) instruction
2266 * - access the %sil, %dil, %bpl, %spl registers
2267 */
2273 /*
2274 * These are the individual fields of a VEX prefix.
2275 */
2279 /* Vector Length, 0: scalar or 128-bit vector, 1: 256-bit vector */
2280 #define VEX_L 0x04
2286 /* VEX m-mmmm field, only used by three bytes prefix */
2291 /* VEX pp field, providing equivalent functionality of a SIMD prefix */
2292 #define VEX_p_66 0x01
2293 #define VEX_p_F3 0x02
2294 #define VEX_p_F2 0x03
2296 /*
2297 * Even in 64 bit mode, usually only 4 byte immediate operands are supported.
2298 */
2302 /*
2303 * Just a bunch of useful macros.
2304 */
2308 #define OPSIZE(osize, wbit) ((wbit) ? isize[osize] : 1)
2309 #define OPSIZE64(osize, wbit) ((wbit) ? isize64[osize] : 1)
2324 /*
2325 * The AVX2 gather instructions are a bit of a mess. While there's a pattern,
2326 * there's not really a consistent scheme that we can use to know what the mode
2327 * is supposed to be for a given type. Various instructions, like VPGATHERDD,
2328 * always match the value of VEX_L. Other instructions like VPGATHERDQ, have
2329 * some registers match VEX_L, but the VSIB is always XMM.
2330 *
2331 * The simplest way to deal with this is to just define a table based on the
2332 * instruction opcodes, which are 0x90-0x93, so we subtract 0x90 to index into
2333 * them.
2334 *
2335 * We further have to subdivide this based on the value of VEX_W and the value
2336 * of VEX_L. The array is constructed to be indexed as:
2337 * [opcode - 0x90][VEX_W][VEX_L].
2338 */
2339 /* w = 0, 0x90 */
2348 {
2349 /* op 0x90, W.0 */
2350 {
2353 },
2354 /* op 0x90, W.1 */
2355 {
2358 }
2359 },
2360 {
2361 /* op 0x91, W.0 */
2362 {
2365 },
2366 /* op 0x91, W.1 */
2367 {
2370 }
2371 },
2372 {
2373 /* op 0x92, W.0 */
2374 {
2377 },
2378 /* op 0x92, W.1 */
2379 {
2382 }
2383 },
2384 {
2385 /* op 0x93, W.0 */
2386 {
2389 },
2390 /* op 0x93, W.1 */
2391 {
2394 }
2395 }
2396 };
2398 /*
2399 * Get the next byte and separate the op code into the high and low nibbles.
2400 */
2401 static int
2403 {
2406 /*
2407 * x86 instructions have a maximum length of 15 bytes. Bail out if
2408 * we try to read more.
2409 */
2422 }
2424 /*
2425 * Get and decode an SIB (scaled index base) byte
2426 */
2427 static void
2429 {
2439 }
2445 }
2447 /*
2448 * Get the byte following the op code and separate it into the
2449 * mode, register, and r/m fields.
2450 */
2451 static void
2453 {
2459 }
2460 }
2462 /*
2463 * Adjust register selection based on any REX prefix bits present.
2464 */
2465 /*ARGSUSED*/
2466 static void
2468 {
2477 }
2478 }
2480 /*
2481 * Adjust register selection based on any VEX prefix bits present.
2482 * Notes: VEX.R, VEX.X and VEX.B use the inverted form compared with REX prefix
2483 */
2484 /*ARGSUSED*/
2485 static void
2487 {
2496 }
2497 }
2499 /*
2500 * Get an immediate operand of the given size, with sign extension.
2501 */
2502 static void
2504 {
2521 else
2536 }
2548 }
2551 }
2552 /* Do sign extension */
2557 }
2558 #ifdef DIS_TEXT
2562 #endif
2563 }
2565 /*
2566 * Get an ip relative operand of the given size, with sign extension.
2567 */
2568 static void
2570 {
2572 #ifdef DIS_TEXT
2574 #endif
2575 }
2577 /*
2578 * Check to see if there is a segment override prefix pending.
2579 * If so, print it in the current 'operand' location and set
2580 * the override flag back to false.
2581 */
2582 /*ARGSUSED*/
2583 static void
2585 {
2586 #ifdef DIS_TEXT
2590 }
2591 #endif
2593 }
2596 /*
2597 * Process a single instruction Register or Memory operand.
2598 *
2599 * mode = addressing mode from ModRM byte
2600 * r_m = r_m (or reg if mode == 3) field from ModRM byte
2601 * wbit = indicates which register (8bit, 16bit, ... MMX, etc.) set to use.
2602 * o = index of operand that we are processing (0, 1 or 2)
2603 *
2604 * the value of reg or r_m must have already been adjusted for any REX prefix.
2605 */
2606 /*ARGSUSED*/
2607 static void
2609 {
2615 #ifdef DIS_TEXT
2617 #endif
2625 /*
2626 * first handle a simple register
2627 */
2629 #ifdef DIS_TEXT
2655 else
2666 else
2669 }
2672 }
2674 /*
2675 * if symbolic representation, skip override prefix, if any
2676 */
2679 /*
2680 * Handle 16 bit memory references first, since they decode
2681 * the mode values more simply.
2682 * mode 1 is r_m + 8 bit displacement
2683 * mode 2 is r_m + 16 bit displacement
2684 * mode 0 is just r_m, unless r_m is 6 which is 16 bit disp
2685 */
2691 #ifdef DIS_TEXT
2696 else
2699 #endif
2701 }
2703 /*
2704 * 32 and 64 bit addressing modes are more complex since they
2705 * can involve an SIB (scaled index and base) byte to decode.
2706 */
2719 }
2721 /*
2722 * Compute the displacement size and get its bytes
2723 */
2739 }
2741 #ifdef DIS_TEXT
2749 OPLEN);
2750 else
2752 OPLEN);
2756 OPLEN);
2759 MODE_RIPREL;
2760 }
2763 OPLEN);
2764 }
2765 }
2773 else
2779 else
2785 }
2787 /*
2788 * print the base (if any)
2789 */
2794 }
2799 }
2801 /*
2802 * print the index (if any)
2803 */
2811 }
2812 #endif
2813 }
2815 /*
2816 * Operand sequence for standard instruction involving one register
2817 * and one register/memory operand.
2818 * wbit indicates a byte(0) or opnd_size(1) operation
2819 * vbit indicates direction (0 for "opcode r,r_m") or (1 for "opcode r_m, r")
2820 */
2821 #define STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, vbit) { \
2822 dtrace_get_modrm(x, &mode, ®, &r_m); \
2823 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); \
2824 dtrace_get_operand(x, mode, r_m, wbit, vbit); \
2825 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1 - vbit); \
2826 }
2828 /*
2829 * Similar to above, but allows for the two operands to be of different
2830 * classes (ie. wbit).
2831 * wbit is for the r_m operand
2832 * w2 is for the reg operand
2833 */
2834 #define MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, w2, vbit) { \
2835 dtrace_get_modrm(x, &mode, ®, &r_m); \
2836 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); \
2837 dtrace_get_operand(x, mode, r_m, wbit, vbit); \
2838 dtrace_get_operand(x, REG_ONLY, reg, w2, 1 - vbit); \
2839 }
2841 /*
2842 * Similar, but for 2 operands plus an immediate.
2843 * vbit indicates direction
2844 * 0 for "opcode imm, r, r_m" or
2845 * 1 for "opcode imm, r_m, r"
2846 */
2847 #define THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, w2, immsize, vbit) { \
2848 dtrace_get_modrm(x, &mode, ®, &r_m); \
2849 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); \
2850 dtrace_get_operand(x, mode, r_m, wbit, 2-vbit); \
2851 dtrace_get_operand(x, REG_ONLY, reg, w2, 1+vbit); \
2852 dtrace_imm_opnd(x, wbit, immsize, 0); \
2853 }
2855 /*
2856 * Similar, but for 2 operands plus two immediates.
2857 */
2858 #define FOUROPERAND(x, mode, reg, r_m, rex_prefix, wbit, w2, immsize) { \
2859 dtrace_get_modrm(x, &mode, ®, &r_m); \
2860 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); \
2861 dtrace_get_operand(x, mode, r_m, wbit, 2); \
2862 dtrace_get_operand(x, REG_ONLY, reg, w2, 3); \
2863 dtrace_imm_opnd(x, wbit, immsize, 1); \
2864 dtrace_imm_opnd(x, wbit, immsize, 0); \
2865 }
2867 /*
2868 * 1 operands plus two immediates.
2869 */
2870 #define ONEOPERAND_TWOIMM(x, mode, reg, r_m, rex_prefix, wbit, immsize) { \
2871 dtrace_get_modrm(x, &mode, ®, &r_m); \
2872 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); \
2873 dtrace_get_operand(x, mode, r_m, wbit, 2); \
2874 dtrace_imm_opnd(x, wbit, immsize, 1); \
2875 dtrace_imm_opnd(x, wbit, immsize, 0); \
2876 }
2878 /*
2879 * Dissassemble a single x86 or amd64 instruction.
2880 *
2881 * Mode determines the default operating mode (SIZE16, SIZE32 or SIZE64)
2882 * for interpreting instructions.
2883 *
2884 * returns non-zero for bad opcode
2885 */
2886 int
2888 {
2890 #ifdef DIS_TEXT
2891 uint_t i;
2892 #endif
2893 #ifdef DIS_MEM
2895 #define NOMEM (nomem = 1)
2896 #else
2898 #endif
2903 uint_t vbit;
2917 /*
2918 * legacy prefixes come in 5 flavors, you should have only one of each
2919 */
2927 /*
2928 * Intel VEX instruction encoding prefix and fields
2929 */
2931 /* 0xC4 means 3 bytes prefix, 0xC5 means 2 bytes prefix */
2934 /*
2935 * VEX prefix byte 1, includes vex.r, vex.x and vex.b
2936 * (for 3 bytes prefix)
2937 */
2940 /*
2941 * For 32-bit mode, it should prefetch the next byte to
2942 * distinguish between AVX and les/lds
2943 */
2953 uint_t vex_L;
2956 #ifdef DIS_TEXT
2957 /* Instruction name for BLS* family of instructions */
2959 #endif
2963 instable_t dp_mmx;
2968 #ifdef DIS_TEXT
2978 }
2979 #endif
2994 }
2996 /*
2997 * Get one opcode byte and check for zero padding that follows
2998 * jump tables.
2999 */
3005 #ifdef DIS_TEXT
3007 #endif
3009 }
3011 /*
3012 * Gather up legacy x86 prefix bytes.
3013 */
3028 #ifdef DIS_TEXT
3030 #endif
3040 }
3046 }
3048 /*
3049 * Handle amd64 mode PREFIX values.
3050 * Some of the segment prefixes are no-ops. (only FS/GS actually work)
3051 * We might have a REX prefix (opcodes 0x40-0x4f)
3052 */
3064 /* AVX instructions */
3067 }
3069 /* LDS, LES or AVX */
3074 /* AVX */
3079 }
3080 }
3086 }
3091 /*
3092 * The vex.x and vex.b bits are not defined in two bytes
3093 * mode vex prefix, their default values are 1
3094 */
3120 }
3126 }
3150 /* Only these three vex_m values valid; others are reserved */
3162 &dis_opAVX660F
3166 &dis_opAVX660F38
3170 &dis_opAVX660F3A
3174 }
3179 &dis_opAVXF30F
3183 &dis_opAVXF30F38
3187 }
3192 &dis_opAVXF20F
3196 &dis_opAVXF20F3A
3200 &dis_opAVXF20F38
3204 }
3210 }
3211 }
3218 else
3220 }
3221 }
3223 /*
3224 * Deal with selection of operand and address size now.
3225 * Note that the REX.W bit being set causes opnd_size_prefix to be
3226 * ignored.
3227 */
3246 }
3247 /*
3248 * The pause instruction - a repz'd nop. This doesn't fit
3249 * with any of the other prefix goop added for SSE, so we'll
3250 * special-case it here.
3251 */
3255 }
3257 /*
3258 * Some 386 instructions have 2 bytes of opcode before the mod_r/m
3259 * byte so we may need to perform a table indirection.
3260 */
3266 uint_t subcode;
3284 #ifdef DIS_TEXT
3287 #endif
3294 }
3298 /* SSSE3 MMX instructions */
3302 #ifdef DIS_MEM
3304 #endif
3305 }
3309 }
3316 /*
3317 * Both crc32 and movbe have the same 3rd opcode
3318 * byte of either 0xF0 or 0xF1, so we use another
3319 * indirection to distinguish between the two.
3320 */
3326 /* It is movbe */
3327 dp++;
3328 }
3329 }
3331 /*
3332 * The adx family of instructions (adcx and adox)
3333 * continue the classic Intel tradition of abusing
3334 * arbitrary prefixes without actually meaning the
3335 * prefix bit. Therefore, if we find either the
3336 * opnd_size_prefix or rep_prefix we end up zeroing it
3337 * out after making our determination so as to ensure
3338 * that we don't get confused and accidentally print
3339 * repz prefixes and the like on these instructions.
3340 *
3341 * In addition, these instructions are actually much
3342 * closer to AVX instructions in semantics. Importantly,
3343 * they always default to having 32-bit operands.
3344 * However, if the CPU is in 64-bit mode, then and only
3345 * then, does it use REX.w promotes things to 64-bits
3346 * and REX.r allows 64-bit mode to use register r8-r15.
3347 */
3352 /* It is adox */
3353 dp++;
3356 /* It isn't adcx */
3358 }
3364 }
3366 #ifdef DIS_TEXT
3369 #endif
3378 }
3382 /* SSSE3 MMX instructions */
3386 #ifdef DIS_MEM
3388 #endif
3389 }
3394 }
3400 }
3404 }
3407 }
3408 }
3410 /*
3411 * If still not at a TERM decode entry, then a ModRM byte
3412 * exists and its fields further decode the instruction.
3413 */
3421 /*
3422 * decode 287 instructions (D8-DF) from opcodeN
3423 */
3436 else
3441 }
3442 }
3444 /*
3445 * In amd64 bit mode, ARPL opcode is changed to MOVSXD
3446 * (sign extend 32bit to 64 bit)
3447 */
3452 /*
3453 * at this point we should have a correct (or invalid) opcode
3454 */
3461 /*
3462 * deal with MMX/SSE opcodes which are changed by prefixes
3463 */
3481 /*
3482 * This is horrible. Some SIMD instructions take the
3483 * form 0x0F 0x?? ..., which is easily decoded using the
3484 * existing tables. Other SIMD instructions use various
3485 * prefix bytes to overload existing instructions. For
3486 * Example, addps is F0, 58, whereas addss is F3 (repz),
3487 * F0, 58. Presumably someone got a raise for this.
3488 *
3489 * If we see one of the instructions which can be
3490 * modified in this way (if we've got one of the SIMDO*
3491 * address modes), we'll check to see if the last prefix
3492 * was a repz. If it was, we strip the prefix from the
3493 * mnemonic, and we indirect using the dis_opSIMDrepz
3494 * table.
3495 */
3497 /*
3498 * Calculate our offset in dis_op0F
3499 */
3506 /*
3507 * Rewrite if this instruction used one of the magic prefixes.
3508 */
3512 else
3520 }
3524 /*
3525 * More horribleness: the group 9 (0xF0 0xC7) instructions are
3526 * allowed an optional prefix of 0x66 or 0xF3. This is similar
3527 * to the SIMD business described above, but with a different
3528 * addressing mode (and an indirect table), so we deal with it
3529 * separately (if similarly).
3530 *
3531 * Intel further complicated this with the release of Ivy Bridge
3532 * where they overloaded these instructions based on the ModR/M
3533 * bytes. The VMX instructions have a mode of 0 since they are
3534 * memory instructions but rdrand instructions have a mode of
3535 * 0b11 (REG_ONLY) because they only operate on registers. While
3536 * there are different prefix formats, for now it is sufficient
3537 * to use a single different table.
3538 */
3540 /*
3541 * Calculate our offset in dis_op0FC7 (the group 9 table)
3542 */
3549 /*
3550 * If we have a mode of 0b11 then we have to rewrite this.
3551 */
3556 }
3558 /*
3559 * Rewrite if this instruction used one of the magic prefixes.
3560 */
3564 else
3572 }
3577 /*
3578 * As with the "normal" SIMD instructions, the MMX
3579 * shuffle instructions are overloaded. These
3580 * instructions, however, are special in that they use
3581 * an extra byte, and thus an extra table. As of this
3582 * writing, they only use the opnd_size prefix.
3583 */
3585 /*
3586 * Calculate our offset in dis_op0F7123
3587 */
3599 }
3605 /*
3606 * Calculate our offset in dis_op0F
3607 */
3619 }
3620 }
3622 }
3624 /*
3625 * In 64 bit mode, some opcodes automatically use opnd_size == SIZE64.
3626 */
3631 #ifdef DIS_TEXT
3632 /*
3633 * At this point most instructions can format the opcode mnemonic
3634 * including the prefixes.
3635 */
3655 OPLEN);
3659 /* It's a cmovx.yy. Replace the suffix x */
3663 }
3668 /*
3669 * To handle PINSRD and PEXTRD
3670 */
3674 OPLEN);
3675 }
3676 }
3677 }
3678 #endif
3680 /*
3681 * Process operands based on the addressing modes.
3682 */
3684 /*
3685 * In vex mode the rex_prefix has no meaning
3686 */
3693 /*
3694 * amd64 instruction to sign extend 32 bit reg/mem operands
3695 * into 64 bit register values
3696 */
3698 #ifdef DIS_TEXT
3701 #endif
3711 /*
3712 * movsbl movsbw movsbq (0x0FBE) or movswl movswq (0x0FBF)
3713 * movzbl movzbw movzbq (0x0FB6) or movzwl movzwq (0x0FB7)
3714 * wbit lives in 2nd byte, note that operands
3715 * are different sized
3716 */
3719 /* target register size = 64 bit */
3721 }
3755 /* reg -> mem */
3759 /* mem -> reg */
3762 }
3765 /*
3766 * imul instruction, with either 8-bit or longer immediate
3767 * opcode 0x6B for byte, sign-extended displacement, 0x69 for word(s)
3768 */
3775 /* memory or register operand to register, with 'w' bit */
3782 /* register to memory or register operand, with 'w' bit */
3783 /* arpl happens to fit here also because it is odd */
3787 else
3792 /* xaddb instruction */
3798 /* MMX register to memory or register operand */
3801 #ifdef DIS_TEXT
3803 #else
3805 #endif
3809 /* MMX register to memory */
3818 /* Double shift. Has immediate operand specifying the shift. */
3828 /*
3829 * Double shift. With no immediate operand, specifies using %cl.
3830 */
3836 /* immediate to memory or register operand */
3841 /*
3842 * Have long immediate for opcode 0x81, but not 0x80 nor 0x83
3843 */
3847 /* immediate to memory or register operand with the */
3848 /* 'w' bit present */
3857 /* immediate to register with register in low 3 bits */
3858 /* of op code */
3860 /* w-bit here (with regs) is bit 3 */
3870 /* MMX immediate shift of register */
3876 /* SIMD immediate shift of register */
3879 mm_shift:
3884 NOMEM;
3887 /* accumulator to memory operand */
3890 /*FALLTHROUGH*/
3892 /* memory operand to accumulator */
3897 #ifdef DIS_TEXT
3899 #endif
3903 /* segment register to memory or register operand */
3906 /*FALLTHROUGH*/
3908 /* memory or register operand to segment register */
3916 /*
3917 * rotate or shift instructions, which may shift by 1 or
3918 * consult the cl register, depending on the 'v' bit
3919 */
3925 #ifdef DIS_TEXT
3932 }
3933 #endif
3935 /*
3936 * immediate rotate or shift instructions
3937 */
3940 normal_imm_mem:
3946 /* bit test instructions */
3951 /* single memory or register operand with 'w' bit present */
3954 just_mem:
3962 #ifdef DIS_TEXT
3964 #endif
3965 NOMEM;
3968 #ifdef DIS_TEXT
3970 #endif
3971 NOMEM;
3973 }
3975 /*FALLTHROUGH*/
3977 /* prefetch instruction - memory operand, but no memory acess */
3979 NOMEM;
3980 /*FALLTHROUGH*/
3982 /* single memory or register operand */
3988 /* single memory or register byte operand */
3995 #ifdef DIS_TEXT
4013 }
4016 #else
4019 #endif
4021 NOMEM;
4023 }
4024 /*FALLTHROUGH*/
4027 #if DIS_TEXT
4055 }
4058 #endif
4059 NOMEM;
4061 }
4062 /*FALLTHROUGH*/
4066 #ifdef DIS_TEXT
4068 #endif
4069 NOMEM;
4072 #ifdef DIS_TEXT
4074 #endif
4075 NOMEM;
4078 #ifdef DIS_TEXT
4080 #endif
4081 NOMEM;
4084 #ifdef DIS_TEXT
4086 #endif
4087 NOMEM;
4091 }
4092 }
4093 /*FALLTHROUGH*/
4097 #ifdef DIS_TEXT
4099 #endif
4100 NOMEM;
4103 #ifdef DIS_TEXT
4105 #endif
4106 NOMEM;
4110 }
4112 }
4113 /*FALLTHROUGH*/
4115 /* Similar to M, but only memory (no direct registers) */
4124 /* move special register to register or reverse if vbit */
4130 /*FALLTHROUGH*/
4137 /*FALLTHROUGH*/
4144 /*FALLTHROUGH*/
4149 }
4154 NOMEM;
4157 /*
4158 * single register operand with register in the low 3
4159 * bits of op code
4160 */
4164 else
4168 NOMEM;
4171 /*
4172 * register to accumulator with register in the low 3
4173 * bits of op code, xchg instructions
4174 */
4176 NOMEM;
4183 /*
4184 * single segment register operand, with register in
4185 * bits 3-4 of op code byte
4186 */
4188 NOMEM;
4193 /*
4194 * single segment register operand, with register in
4195 * bits 3-5 of op code
4196 */
4198 NOMEM;
4199 /* long seg reg from opcode */
4204 /* memory or register operand to register */
4218 /* MMX/SIMD-Int memory or mm reg to mm reg */
4221 #ifdef DIS_TEXT
4223 #else
4225 #endif
4230 #ifdef DIS_TEXT
4232 #else
4234 #endif
4245 /* MMX/SIMD-Int and SIMD-FP predicated mm reg to r32 */
4251 xmm3p:
4258 NOMEM;
4266 /* MMX/SIMD-Int predicated r32/mem to mm reg */
4275 xmmprm:
4279 /* MMX/SIMD-Int predicated mm/mem to mm reg */
4285 /* MMX/SIMD-Int mm reg to r32 */
4287 NOMEM;
4295 /* SIMD memory or xmm reg operand to xmm reg */
4307 #ifdef DIS_TEXT
4308 /*
4309 * movlps and movhlps share opcodes. They differ in the
4310 * addressing modes allowed for their operands.
4311 * movhps and movlhps behave similarly.
4312 */
4318 }
4319 #endif
4324 /* SIMD xmm reg to memory or xmm reg */
4330 #ifdef DIS_TEXT
4336 #endif
4341 /* SIMD memory to xmm reg */
4347 #ifdef DIS_TEXT
4351 else
4353 }
4354 #endif
4358 /* SIMD memory or r32 to xmm reg */
4369 /* SIMD memory or mm reg to xmm reg */
4371 /* SIMD mm to xmm */
4377 /* SIMD memory or xmm reg to mm reg */
4386 /* SIMD memory or xmm reg to r32 */
4392 /* SIMD xmm to r32 */
4401 NOMEM;
4404 /* SIMD predicated memory or xmm reg with/to xmm reg */
4413 #ifdef DIS_TEXT
4414 /*
4415 * cmpps and cmpss vary their instruction name based
4416 * on the value of imm8. Other XMMP instructions,
4417 * such as shufps, require explicit specification of
4418 * the predicate.
4419 */
4431 OPLEN);
4434 OPLEN);
4438 }
4439 #endif
4445 NOMEM;
4450 NOMEM;
4453 /* immediate operand to accumulator */
4458 NOMEM;
4461 /* memory or register operand to accumulator */
4468 /* si register to di register used to reference memory */
4470 #ifdef DIS_TEXT
4475 OPLEN);
4477 OPLEN);
4480 OPLEN);
4482 OPLEN);
4485 OPLEN);
4487 OPLEN);
4488 }
4489 #endif
4493 /* accumulator to di register */
4496 #ifdef DIS_TEXT
4502 OPLEN);
4505 OPLEN);
4506 else
4508 OPLEN);
4509 #endif
4512 /* si register to accumulator */
4515 #ifdef DIS_TEXT
4520 OPLEN);
4523 OPLEN);
4524 else
4526 OPLEN);
4528 #endif
4531 /*
4532 * single operand, a 16/32 bit displacement
4533 */
4537 NOMEM;
4540 /* jmp/call indirect to memory or register operand */
4542 #ifdef DIS_TEXT
4544 #endif
4550 /*
4551 * for long jumps and long calls -- a new code segment
4552 * register and an offset in IP -- stored in object
4553 * code in reverse order. Note - not valid in amd64
4554 */
4559 #ifdef DIS_TEXT
4561 #endif
4562 /* will now get segment operand */
4566 /*
4567 * jmp/call. single operand, 8 bit displacement.
4568 * added to current EIP in 'compofff'
4569 */
4572 NOMEM;
4575 /* single 32/16 bit immediate operand */
4581 /* single 8 bit immediate operand */
4601 }
4605 /* 16-bit immediate operand */
4611 /* single 8 bit port operand */
4615 NOMEM;
4618 /* single operand, dx register (variable port instruction) */
4622 #ifdef DIS_TEXT
4624 #endif
4625 NOMEM;
4628 /*
4629 * The int instruction, which has two forms:
4630 * int 3 (breakpoint) or
4631 * int n, where n is indicated in the subsequent
4632 * byte (format Ib). The int 3 instruction (opcode 0xCC),
4633 * where, although the 3 looks like an operand,
4634 * it is implied by the opcode. It must be converted
4635 * to the correct base and output.
4636 */
4638 #ifdef DIS_TEXT
4643 #endif
4644 NOMEM;
4647 /* single 8 bit immediate operand */
4650 NOMEM;
4653 /* an unused byte must be discarded */
4658 NOMEM;
4662 #ifdef DIS_TEXT
4667 else
4669 #endif
4671 NOMEM;
4675 #ifdef DIS_TEXT
4680 else
4682 #endif
4684 NOMEM;
4688 /*
4689 * sfence is sfence if mode is REG_ONLY. If mode isn't
4690 * REG_ONLY, mnemonic should be 'clflush'.
4691 */
4694 /* sfence doesn't take operands */
4695 #ifdef DIS_TEXT
4702 NOMEM;
4703 }
4704 #else
4708 NOMEM;
4709 }
4710 #endif
4713 /*
4714 * no disassembly, the mnemonic was all there was so go on
4715 */
4719 NOMEM;
4720 /*FALLTHROUGH*/
4725 /*
4726 * XRSTOR and LFENCE share the same opcode but differ in mode
4727 */
4731 /*
4732 * Only the following exact byte sequences are allowed:
4733 *
4734 * 0f ae e8 lfence
4735 * 0f ae f0 mfence
4736 */
4741 #ifdef DIS_TEXT
4743 #endif
4746 }
4749 /* float reg */
4751 #ifdef DIS_TEXT
4755 #endif
4756 NOMEM;
4759 /* float reg to float reg, with ret bit present */
4762 /*FALLTHROUGH*/
4764 #ifdef DIS_TEXT
4769 #endif
4770 NOMEM;
4773 /* AVX instructions */
4775 /* op(ModR/M.r/m) */
4778 #ifdef DIS_TEXT
4781 #endif
4787 /* ModR/M.reg := op(VEX.vvvv, ModR/M.r/m) */
4792 /*
4793 * In classic Intel fashion, the opcodes for all of the FMA
4794 * instructions all have two possible mnemonics which vary by
4795 * one letter, which is selected based on the value of the wbit.
4796 * When wbit is one, they have the 'd' suffix and when 'wbit' is
4797 * 0, they have the 's' suffix. Otherwise, the FMA instructions
4798 * are all a standard VEX_RMrX.
4799 */
4800 #ifdef DIS_TEXT
4807 }
4808 }
4809 #endif
4814 /* vmovsd <m64>, <xmm> */
4815 /* or vmovss <m64>, <xmm> */
4818 }
4819 }
4822 /*
4823 * VEX prefix uses the 1's complement form to encode the
4824 * XMM/YMM regs
4825 */
4830 /*
4831 * vcvtsi2si </r,m>, <xmm>, <xmm> or vcvtsi2ss </r,m>,
4832 * <xmm>, <xmm>
4833 */
4835 }
4836 #ifdef DIS_TEXT
4843 }
4844 #endif
4850 /* ModR/M.reg := op(MODR/M.r/m, VEX.vvvv) */
4856 /*
4857 * VEX prefix uses the 1's complement form to encode the
4858 * XMM/YMM regs
4859 */
4866 /* ModR/M.reg := op(MODR/M.r/m, VSIB, VEX.vvvv) */
4870 /*
4871 * All instructions that use VSIB are currently a mess. See the
4872 * comment around the dis_gather_regs_t structure definition.
4873 */
4877 #ifdef DIS_TEXT
4881 #endif
4887 /*
4888 * VEX prefix uses the 1's complement form to encode the
4889 * XMM/YMM regs
4890 */
4897 /* ModR/M.rm := op(VEX.vvvv, ModR/M.reg) */
4906 /* vmovsd <xmm>, <m64> */
4907 /* or vmovss <xmm>, <m64> */
4910 }
4911 }
4919 /* ModR/M.reg := op(VEX.vvvv, ModR/M.r_m, imm8[7:4]) */
4927 /* vinsertf128 <imm8>, <xmm>, <ymm>, <ymm> */
4931 /* vpinsrb <imm8>, <reg/mm>, <xmm>, <xmm> */
4932 /* or vpinsrw <imm8>, <reg/mm>, <xmm>, <xmm> */
4935 /* vpinsrd/q <imm8>, <reg/mm>, <xmm>, <xmm> */
4936 #ifdef DIS_TEXT
4939 #endif
4943 }
4945 /* one byte immediate number */
4948 /* vblendvpd, vblendvps, vblendvb use the imm encode the regs */
4952 #ifdef DIS_TEXT
4954 #endif
4956 #ifdef DIS_TEXT
4960 else
4963 #endif
4964 }
4968 /* ModR/M.reg := op(ModR/M.rm) */
4973 L_VEX_MX:
4978 /* vcvtpd2dq <ymm>, <xmm> */
4979 /* or vcvtpd2ps <ymm>, <xmm> */
4980 /* or vcvttpd2dq <ymm>, <xmm> */
4992 /* vcvtdq2pd <xmm>, <ymm> */
4993 /* or vcvtps2pd <xmm>, <ymm> */
4994 /* or vcvtph2ps <xmm>, <ymm> */
4995 /* or vbroadcasts* <xmm>, <ymm> */
4999 /* vmovd/q <reg/mem 32/64>, <xmm> */
5000 #ifdef DIS_TEXT
5003 #endif
5009 }
5014 /* ModR/M.reg := op(ModR/M.rm, imm8) */
5023 /* one byte immediate number */
5028 /* VEX.vvvv := op(ModR/M.rm, imm8) */
5032 #ifdef DIS_TEXT
5034 OPLEN);
5035 #endif
5041 /* one byte immediate number */
5046 /* ModR/M.reg (reg32/64) := op(ModR/M.rm) */
5048 /* vpextrw <imm8>, <xmm>, <reg> */
5054 }
5067 /* implicit(eflags/r32) := op(ModR/M.reg, ModR/M.rm) */
5077 /* ModR/M.rm := op(ModR/M.reg) */
5078 /* vextractf128 || vcvtps2ph */
5089 /* one byte immediate number */
5092 }
5103 /* ModR/M.rm := op(ModR/M.reg) */
5110 /* vmovd/q <reg/mem 32/64>, <xmm> */
5111 #ifdef DIS_TEXT
5114 #endif
5123 /* ModR/M.rm := op(ModR/M.reg, imm) */
5129 #ifdef DIS_TEXT
5131 /* vpextrd/q <imm>, <xmm>, <reg/mem 32/64> */
5134 }
5135 #endif
5139 /* one byte immediate number */
5143 /* ModR/M.rm := op(ModR/M.reg, imm) */
5151 /* one byte immediate number */
5156 /* ModR/M.rm := op(ModR/M.reg) */
5165 /* one byte immediate number */
5168 }
5173 L_VEX_RM:
5181 /* ModR/M.rm := op(VEX.vvvv, ModR/M.reg) */
5187 /* VEX use the 1's complement form encode the XMM/YMM regs */
5193 /* ModR/M.reg := op(VEX.vvvv, ModR/M.rm) */
5204 #ifdef DIS_TEXT
5207 #endif
5211 /*
5212 * The BLS instructions are VEX instructions that are based on
5213 * VEX.0F38.F3; however, they are considered special group 17
5214 * and like everything else, they use the bits in 3-5 of the
5215 * MOD R/M to determine the sub instruction. Unlike many others
5216 * like the VMX instructions, these are valid both for memory
5217 * and register forms.
5218 */
5225 #ifdef DIS_TEXT
5227 #endif
5230 #ifdef DIS_TEXT
5232 #endif
5235 #ifdef DIS_TEXT
5237 #endif
5241 }
5244 #ifdef DIS_TEXT
5246 #endif
5250 }
5251 /* an invalid op code */
5257 NOMEM;
5264 done:
5265 #ifdef DIS_MEM
5266 /*
5267 * compute the size of any memory accessed by the instruction
5268 */
5282 }
5287 /*
5288 * In 64 bit mode descriptor table entries
5289 * go up to 10 bytes and popf/pushf are always 8 bytes
5290 */
5296 else
5307 else
5315 }
5316 #endif
5319 error:
5320 #ifdef DIS_TEXT
5322 #endif
5324 }
5326 #ifdef DIS_TEXT
5328 /*
5329 * Some instructions should have immediate operands printed
5330 * as unsigned integers. We compare against this table.
5331 */
5335 0
5336 };
5339 static int
5341 {
5346 /*
5347 * Work back to start of last mnemonic, since we may have
5348 * prefixes on some opcodes.
5349 */
5362 }
5364 }
5366 /*
5367 * Print a numeric immediate into end of buf, maximum length buflen.
5368 * The immediate may be an address or a displacement. Mask is set
5369 * for address size. If the immediate is a "small negative", or
5370 * if it's a negative displacement of any magnitude, print as -<absval>.
5371 * Respect the "octal" flag. "Small negative" is defined as "in the
5372 * interval [NEG_LIMIT, 0)".
5373 *
5374 * Also, "isunsigned_op()" instructions never print negatives.
5375 *
5376 * Return whether we decided to print a negative value or not.
5377 */
5379 #define NEG_LIMIT -255
5383 static int
5386 {
5403 else
5408 }
5409 }
5412 static int
5414 {
5420 }
5422 }
5424 /* ARGSUSED */
5425 void
5428 {
5442 /*
5443 * For PC-relative jumps, the pc is really the next pc after executing
5444 * this instruction, so increment it appropriately.
5445 */
5456 /*
5457 * sv is for the signed, possibly-truncated immediate or
5458 * displacement; usv retains the original size and
5459 * unsignedness for symbol lookup.
5460 */
5464 /*
5465 * About masks: for immediates that represent
5466 * addresses, the appropriate display size is
5467 * the effective address size of the instruction.
5468 * This includes MODE_OFFSET, MODE_IPREL, and
5469 * MODE_RIPREL. Immediates that are simply
5470 * immediate values should display in the operand's
5471 * size, however, since they don't represent addresses.
5472 */
5474 /* d86_addr_size is SIZEnn, which is log2(real size) */
5477 /* d86_value_size and d86_imm_bytes are in bytes */
5497 buflen);
5502 }
5509 /*
5510 * We printed a negative value for an
5511 * immediate that wasn't a
5512 * displacement. Note that fact so we can
5513 * print the positive value as an
5514 * annotation.
5515 */
5519 }
5536 }
5544 }
5545 }
5547 /*
5548 * The symbol lookups may result in false positives,
5549 * particularly on object files, where small numbers may match
5550 * the 0-relative non-relocated addresses of symbols.
5551 */
5562 }
5564 /*
5565 * If we printed a negative immediate above, print the
5566 * positive in case our heuristic was unhelpful
5567 */
5573 }
5574 }
5577 /* Print symbol or effective address for reltgt */
5584 }
5585 }