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Merge illumos-gate
[unleashed.git] / kernel / drivers / net / e1000api / e1000_hw.h
blobff9f1ff4425ebc4305451b1959eda553738f8ff2
1 /******************************************************************************
2
3 Copyright (c) 2001-2015, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
19
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32 ******************************************************************************/
33 /*$FreeBSD$*/
34
35 #ifndef _E1000_HW_H_
36 #define _E1000_HW_H_
37
38 #include "e1000_osdep.h"
39 #include "e1000_regs.h"
40 #include "e1000_defines.h"
41
42 struct e1000_hw;
43
44 #define E1000_DEV_ID_82542 0x1000
45 #define E1000_DEV_ID_82543GC_FIBER 0x1001
46 #define E1000_DEV_ID_82543GC_COPPER 0x1004
47 #define E1000_DEV_ID_82544EI_COPPER 0x1008
48 #define E1000_DEV_ID_82544EI_FIBER 0x1009
49 #define E1000_DEV_ID_82544GC_COPPER 0x100C
50 #define E1000_DEV_ID_82544GC_LOM 0x100D
51 #define E1000_DEV_ID_82540EM 0x100E
52 #define E1000_DEV_ID_82540EM_LOM 0x1015
53 #define E1000_DEV_ID_82540EP_LOM 0x1016
54 #define E1000_DEV_ID_82540EP 0x1017
55 #define E1000_DEV_ID_82540EP_LP 0x101E
56 #define E1000_DEV_ID_82545EM_COPPER 0x100F
57 #define E1000_DEV_ID_82545EM_FIBER 0x1011
58 #define E1000_DEV_ID_82545GM_COPPER 0x1026
59 #define E1000_DEV_ID_82545GM_FIBER 0x1027
60 #define E1000_DEV_ID_82545GM_SERDES 0x1028
61 #define E1000_DEV_ID_82546EB_COPPER 0x1010
62 #define E1000_DEV_ID_82546EB_FIBER 0x1012
63 #define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D
64 #define E1000_DEV_ID_82546GB_COPPER 0x1079
65 #define E1000_DEV_ID_82546GB_FIBER 0x107A
66 #define E1000_DEV_ID_82546GB_SERDES 0x107B
67 #define E1000_DEV_ID_82546GB_PCIE 0x108A
68 #define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099
69 #define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5
70 #define E1000_DEV_ID_82541EI 0x1013
71 #define E1000_DEV_ID_82541EI_MOBILE 0x1018
72 #define E1000_DEV_ID_82541ER_LOM 0x1014
73 #define E1000_DEV_ID_82541ER 0x1078
74 #define E1000_DEV_ID_82541GI 0x1076
75 #define E1000_DEV_ID_82541GI_LF 0x107C
76 #define E1000_DEV_ID_82541GI_MOBILE 0x1077
77 #define E1000_DEV_ID_82547EI 0x1019
78 #define E1000_DEV_ID_82547EI_MOBILE 0x101A
79 #define E1000_DEV_ID_82547GI 0x1075
80 #define E1000_DEV_ID_82571EB_COPPER 0x105E
81 #define E1000_DEV_ID_82571EB_FIBER 0x105F
82 #define E1000_DEV_ID_82571EB_SERDES 0x1060
83 #define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9
84 #define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA
85 #define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4
86 #define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5
87 #define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5
88 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC
89 #define E1000_DEV_ID_82572EI_COPPER 0x107D
90 #define E1000_DEV_ID_82572EI_FIBER 0x107E
91 #define E1000_DEV_ID_82572EI_SERDES 0x107F
92 #define E1000_DEV_ID_82572EI 0x10B9
93 #define E1000_DEV_ID_82573E 0x108B
94 #define E1000_DEV_ID_82573E_IAMT 0x108C
95 #define E1000_DEV_ID_82573L 0x109A
96 #define E1000_DEV_ID_82574L 0x10D3
97 #define E1000_DEV_ID_82574LA 0x10F6
98 #define E1000_DEV_ID_82583V 0x150C
99 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096
100 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098
101 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA
102 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB
103 #define E1000_DEV_ID_ICH8_82567V_3 0x1501
104 #define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049
105 #define E1000_DEV_ID_ICH8_IGP_AMT 0x104A
106 #define E1000_DEV_ID_ICH8_IGP_C 0x104B
107 #define E1000_DEV_ID_ICH8_IFE 0x104C
108 #define E1000_DEV_ID_ICH8_IFE_GT 0x10C4
109 #define E1000_DEV_ID_ICH8_IFE_G 0x10C5
110 #define E1000_DEV_ID_ICH8_IGP_M 0x104D
111 #define E1000_DEV_ID_ICH9_IGP_M 0x10BF
112 #define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5
113 #define E1000_DEV_ID_ICH9_IGP_M_V 0x10CB
114 #define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD
115 #define E1000_DEV_ID_ICH9_BM 0x10E5
116 #define E1000_DEV_ID_ICH9_IGP_C 0x294C
117 #define E1000_DEV_ID_ICH9_IFE 0x10C0
118 #define E1000_DEV_ID_ICH9_IFE_GT 0x10C3
119 #define E1000_DEV_ID_ICH9_IFE_G 0x10C2
120 #define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC
121 #define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD
122 #define E1000_DEV_ID_ICH10_R_BM_V 0x10CE
123 #define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE
124 #define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF
125 #define E1000_DEV_ID_ICH10_D_BM_V 0x1525
126 #define E1000_DEV_ID_PCH_M_HV_LM 0x10EA
127 #define E1000_DEV_ID_PCH_M_HV_LC 0x10EB
128 #define E1000_DEV_ID_PCH_D_HV_DM 0x10EF
129 #define E1000_DEV_ID_PCH_D_HV_DC 0x10F0
130 #define E1000_DEV_ID_PCH2_LV_LM 0x1502
131 #define E1000_DEV_ID_PCH2_LV_V 0x1503
132 #define E1000_DEV_ID_PCH_LPT_I217_LM 0x153A
133 #define E1000_DEV_ID_PCH_LPT_I217_V 0x153B
134 #define E1000_DEV_ID_PCH_LPTLP_I218_LM 0x155A
135 #define E1000_DEV_ID_PCH_LPTLP_I218_V 0x1559
136 #define E1000_DEV_ID_PCH_I218_LM2 0x15A0
137 #define E1000_DEV_ID_PCH_I218_V2 0x15A1
138 #define E1000_DEV_ID_PCH_I218_LM3 0x15A2 /* Wildcat Point PCH */
139 #define E1000_DEV_ID_PCH_I218_V3 0x15A3 /* Wildcat Point PCH */
140 #define E1000_DEV_ID_PCH_SPT_I219_LM 0x156F /* Sunrise Point PCH */
141 #define E1000_DEV_ID_PCH_SPT_I219_V 0x1570 /* Sunrise Point PCH */
142 #define E1000_DEV_ID_PCH_SPT_I219_LM2 0x15B7 /* Sunrise Point-H PCH */
143 #define E1000_DEV_ID_PCH_SPT_I219_V2 0x15B8 /* Sunrise Point-H PCH */
144 #define E1000_DEV_ID_PCH_LBG_I219_LM3 0x15B9 /* LEWISBURG PCH */
145 #define E1000_DEV_ID_PCH_SPT_I219_LM4 0x15D7
146 #define E1000_DEV_ID_PCH_SPT_I219_V4 0x15D8
147 #define E1000_DEV_ID_PCH_SPT_I219_LM5 0x15E3
148 #define E1000_DEV_ID_PCH_SPT_I219_V5 0x15D6
149 #define E1000_DEV_ID_PCH_CNP_I219_LM6 0x15BD
150 #define E1000_DEV_ID_PCH_CNP_I219_V6 0x15BE
151 #define E1000_DEV_ID_PCH_CNP_I219_LM7 0x15BB
152 #define E1000_DEV_ID_PCH_CNP_I219_V7 0x15BC
153 #define E1000_DEV_ID_PCH_ICP_I219_LM8 0x15DF
154 #define E1000_DEV_ID_PCH_ICP_I219_V8 0x15E0
155 #define E1000_DEV_ID_PCH_ICP_I219_LM9 0x15E1
156 #define E1000_DEV_ID_PCH_ICP_I219_V9 0x15E2
157 #define E1000_DEV_ID_82576 0x10C9
158 #define E1000_DEV_ID_82576_FIBER 0x10E6
159 #define E1000_DEV_ID_82576_SERDES 0x10E7
160 #define E1000_DEV_ID_82576_QUAD_COPPER 0x10E8
161 #define E1000_DEV_ID_82576_QUAD_COPPER_ET2 0x1526
162 #define E1000_DEV_ID_82576_NS 0x150A
163 #define E1000_DEV_ID_82576_NS_SERDES 0x1518
164 #define E1000_DEV_ID_82576_SERDES_QUAD 0x150D
165 #define E1000_DEV_ID_82576_VF 0x10CA
166 #define E1000_DEV_ID_82576_VF_HV 0x152D
167 #define E1000_DEV_ID_I350_VF 0x1520
168 #define E1000_DEV_ID_I350_VF_HV 0x152F
169 #define E1000_DEV_ID_82575EB_COPPER 0x10A7
170 #define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9
171 #define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6
172 #define E1000_DEV_ID_82580_COPPER 0x150E
173 #define E1000_DEV_ID_82580_FIBER 0x150F
174 #define E1000_DEV_ID_82580_SERDES 0x1510
175 #define E1000_DEV_ID_82580_SGMII 0x1511
176 #define E1000_DEV_ID_82580_COPPER_DUAL 0x1516
177 #define E1000_DEV_ID_82580_QUAD_FIBER 0x1527
178 #define E1000_DEV_ID_I350_COPPER 0x1521
179 #define E1000_DEV_ID_I350_FIBER 0x1522
180 #define E1000_DEV_ID_I350_SERDES 0x1523
181 #define E1000_DEV_ID_I350_SGMII 0x1524
182 #define E1000_DEV_ID_I350_DA4 0x1546
183 #define E1000_DEV_ID_I210_COPPER 0x1533
184 #define E1000_DEV_ID_I210_COPPER_OEM1 0x1534
185 #define E1000_DEV_ID_I210_COPPER_IT 0x1535
186 #define E1000_DEV_ID_I210_FIBER 0x1536
187 #define E1000_DEV_ID_I210_SERDES 0x1537
188 #define E1000_DEV_ID_I210_SGMII 0x1538
189 #define E1000_DEV_ID_I210_COPPER_FLASHLESS 0x157B
190 #define E1000_DEV_ID_I210_SERDES_FLASHLESS 0x157C
191 #define E1000_DEV_ID_I211_COPPER 0x1539
192 #define E1000_DEV_ID_I354_BACKPLANE_1GBPS 0x1F40
193 #define E1000_DEV_ID_I354_SGMII 0x1F41
194 #define E1000_DEV_ID_I354_BACKPLANE_2_5GBPS 0x1F45
195 #define E1000_DEV_ID_DH89XXCC_SGMII 0x0438
196 #define E1000_DEV_ID_DH89XXCC_SERDES 0x043A
197 #define E1000_DEV_ID_DH89XXCC_BACKPLANE 0x043C
198 #define E1000_DEV_ID_DH89XXCC_SFP 0x0440
199
200 #define E1000_REVISION_0 0
201 #define E1000_REVISION_1 1
202 #define E1000_REVISION_2 2
203 #define E1000_REVISION_3 3
204 #define E1000_REVISION_4 4
205
206 #define E1000_FUNC_0 0
207 #define E1000_FUNC_1 1
208 #define E1000_FUNC_2 2
209 #define E1000_FUNC_3 3
210
211 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0
212 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3
213 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2 6
214 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3 9
215
216 /*
217 * This enumeration represents all of the different kinds of MAC chips that are
218 * used by both the e1000g and igb drivers. The ordering here is important as
219 * certain classes of MACs are very similar, but have minor differences and so
220 * are compared based on the ordering here. Changing the order here should not
221 * be done arbitrarily.
222 */
223 enum e1000_mac_type {
224 e1000_undefined = 0,
225 e1000_82542,
226 e1000_82543,
227 e1000_82544,
228 e1000_82540,
229 e1000_82545,
230 e1000_82545_rev_3,
231 e1000_82546,
232 e1000_82546_rev_3,
233 e1000_82541,
234 e1000_82541_rev_2,
235 e1000_82547,
236 e1000_82547_rev_2,
237 e1000_82571,
238 e1000_82572,
239 e1000_82573,
240 e1000_82574,
241 e1000_82583,
242 e1000_80003es2lan,
243 /*
244 * The following MACs all share the ich8 style of hardware and are
245 * implemented in ich8, though some are a little more different than
246 * others. The pch_lpt, pch_spt, and pch_cnp family are a bit more
247 * different than the others and just have slight variants in behavior
248 * between them. They are ordered based on release.
249 */
250 e1000_ich8lan,
251 e1000_ich9lan,
252 e1000_ich10lan,
253 e1000_pchlan,
254 e1000_pch2lan,
255 e1000_pch_lpt,
256 e1000_pch_spt,
257 e1000_pch_cnp,
258 /*
259 * After this point all MACs are used by the igb(7D) driver as opposed
260 * to e1000g(7D). If a new MAC is specific to e1000g series of devices,
261 * then it should be added above this.
262 */
263 e1000_82575,
264 e1000_82576,
265 e1000_82580,
266 e1000_i350,
267 e1000_i354,
268 e1000_i210,
269 e1000_i211,
270 e1000_vfadapt,
271 e1000_vfadapt_i350,
272 e1000_num_macs /* List is 1-based, so subtract 1 for TRUE count. */
273 };
274
275 enum e1000_media_type {
276 e1000_media_type_unknown = 0,
277 e1000_media_type_copper = 1,
278 e1000_media_type_fiber = 2,
279 e1000_media_type_internal_serdes = 3,
280 e1000_num_media_types
281 };
282
283 enum e1000_nvm_type {
284 e1000_nvm_unknown = 0,
285 e1000_nvm_none,
286 e1000_nvm_eeprom_spi,
287 e1000_nvm_eeprom_microwire,
288 e1000_nvm_flash_hw,
289 e1000_nvm_invm,
290 e1000_nvm_flash_sw
291 };
292
293 enum e1000_nvm_override {
294 e1000_nvm_override_none = 0,
295 e1000_nvm_override_spi_small,
296 e1000_nvm_override_spi_large,
297 e1000_nvm_override_microwire_small,
298 e1000_nvm_override_microwire_large
299 };
300
301 enum e1000_phy_type {
302 e1000_phy_unknown = 0,
303 e1000_phy_none,
304 e1000_phy_m88,
305 e1000_phy_igp,
306 e1000_phy_igp_2,
307 e1000_phy_gg82563,
308 e1000_phy_igp_3,
309 e1000_phy_ife,
310 e1000_phy_bm,
311 e1000_phy_82578,
312 e1000_phy_82577,
313 e1000_phy_82579,
314 e1000_phy_i217,
315 e1000_phy_82580,
316 e1000_phy_vf,
317 e1000_phy_i210,
318 };
319
320 enum e1000_bus_type {
321 e1000_bus_type_unknown = 0,
322 e1000_bus_type_pci,
323 e1000_bus_type_pcix,
324 e1000_bus_type_pci_express,
325 e1000_bus_type_reserved
326 };
327
328 enum e1000_bus_speed {
329 e1000_bus_speed_unknown = 0,
330 e1000_bus_speed_33,
331 e1000_bus_speed_66,
332 e1000_bus_speed_100,
333 e1000_bus_speed_120,
334 e1000_bus_speed_133,
335 e1000_bus_speed_2500,
336 e1000_bus_speed_5000,
337 e1000_bus_speed_reserved
338 };
339
340 enum e1000_bus_width {
341 e1000_bus_width_unknown = 0,
342 e1000_bus_width_pcie_x1,
343 e1000_bus_width_pcie_x2,
344 e1000_bus_width_pcie_x4 = 4,
345 e1000_bus_width_pcie_x8 = 8,
346 e1000_bus_width_32,
347 e1000_bus_width_64,
348 e1000_bus_width_reserved
349 };
350
351 enum e1000_1000t_rx_status {
352 e1000_1000t_rx_status_not_ok = 0,
353 e1000_1000t_rx_status_ok,
354 e1000_1000t_rx_status_undefined = 0xFF
355 };
356
357 enum e1000_rev_polarity {
358 e1000_rev_polarity_normal = 0,
359 e1000_rev_polarity_reversed,
360 e1000_rev_polarity_undefined = 0xFF
361 };
362
363 enum e1000_fc_mode {
364 e1000_fc_none = 0,
365 e1000_fc_rx_pause,
366 e1000_fc_tx_pause,
367 e1000_fc_full,
368 e1000_fc_default = 0xFF
369 };
370
371 enum e1000_ffe_config {
372 e1000_ffe_config_enabled = 0,
373 e1000_ffe_config_active,
374 e1000_ffe_config_blocked
375 };
376
377 enum e1000_dsp_config {
378 e1000_dsp_config_disabled = 0,
379 e1000_dsp_config_enabled,
380 e1000_dsp_config_activated,
381 e1000_dsp_config_undefined = 0xFF
382 };
383
384 enum e1000_ms_type {
385 e1000_ms_hw_default = 0,
386 e1000_ms_force_master,
387 e1000_ms_force_slave,
388 e1000_ms_auto
389 };
390
391 enum e1000_smart_speed {
392 e1000_smart_speed_default = 0,
393 e1000_smart_speed_on,
394 e1000_smart_speed_off
395 };
396
397 enum e1000_serdes_link_state {
398 e1000_serdes_link_down = 0,
399 e1000_serdes_link_autoneg_progress,
400 e1000_serdes_link_autoneg_complete,
401 e1000_serdes_link_forced_up
402 };
403
404 #define __le16 u16
405 #define __le32 u32
406 #define __le64 u64
407 /* Receive Descriptor */
408 struct e1000_rx_desc {
409 __le64 buffer_addr; /* Address of the descriptor's data buffer */
410 __le16 length; /* Length of data DMAed into data buffer */
411 __le16 csum; /* Packet checksum */
412 u8 status; /* Descriptor status */
413 u8 errors; /* Descriptor Errors */
414 __le16 special;
415 };
416
417 /* Receive Descriptor - Extended */
418 union e1000_rx_desc_extended {
419 struct {
420 __le64 buffer_addr;
421 __le64 reserved;
422 } read;
423 struct {
424 struct {
425 __le32 mrq; /* Multiple Rx Queues */
426 union {
427 __le32 rss; /* RSS Hash */
428 struct {
429 __le16 ip_id; /* IP id */
430 __le16 csum; /* Packet Checksum */
431 } csum_ip;
432 } hi_dword;
433 } lower;
434 struct {
435 __le32 status_error; /* ext status/error */
436 __le16 length;
437 __le16 vlan; /* VLAN tag */
438 } upper;
439 } wb; /* writeback */
440 };
441
442 #define MAX_PS_BUFFERS 4
443
444 /* Number of packet split data buffers (not including the header buffer) */
445 #define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1)
446
447 /* Receive Descriptor - Packet Split */
448 union e1000_rx_desc_packet_split {
449 struct {
450 /* one buffer for protocol header(s), three data buffers */
451 __le64 buffer_addr[MAX_PS_BUFFERS];
452 } read;
453 struct {
454 struct {
455 __le32 mrq; /* Multiple Rx Queues */
456 union {
457 __le32 rss; /* RSS Hash */
458 struct {
459 __le16 ip_id; /* IP id */
460 __le16 csum; /* Packet Checksum */
461 } csum_ip;
462 } hi_dword;
463 } lower;
464 struct {
465 __le32 status_error; /* ext status/error */
466 __le16 length0; /* length of buffer 0 */
467 __le16 vlan; /* VLAN tag */
468 } middle;
469 struct {
470 __le16 header_status;
471 /* length of buffers 1-3 */
472 __le16 length[PS_PAGE_BUFFERS];
473 } upper;
474 __le64 reserved;
475 } wb; /* writeback */
476 };
477
478 /* Transmit Descriptor */
479 struct e1000_tx_desc {
480 __le64 buffer_addr; /* Address of the descriptor's data buffer */
481 union {
482 __le32 data;
483 struct {
484 __le16 length; /* Data buffer length */
485 u8 cso; /* Checksum offset */
486 u8 cmd; /* Descriptor control */
487 } flags;
488 } lower;
489 union {
490 __le32 data;
491 struct {
492 u8 status; /* Descriptor status */
493 u8 css; /* Checksum start */
494 __le16 special;
495 } fields;
496 } upper;
497 };
498
499 /* Offload Context Descriptor */
500 struct e1000_context_desc {
501 union {
502 __le32 ip_config;
503 struct {
504 u8 ipcss; /* IP checksum start */
505 u8 ipcso; /* IP checksum offset */
506 __le16 ipcse; /* IP checksum end */
507 } ip_fields;
508 } lower_setup;
509 union {
510 __le32 tcp_config;
511 struct {
512 u8 tucss; /* TCP checksum start */
513 u8 tucso; /* TCP checksum offset */
514 __le16 tucse; /* TCP checksum end */
515 } tcp_fields;
516 } upper_setup;
517 __le32 cmd_and_length;
518 union {
519 __le32 data;
520 struct {
521 u8 status; /* Descriptor status */
522 u8 hdr_len; /* Header length */
523 __le16 mss; /* Maximum segment size */
524 } fields;
525 } tcp_seg_setup;
526 };
527
528 /* Offload data descriptor */
529 struct e1000_data_desc {
530 __le64 buffer_addr; /* Address of the descriptor's buffer address */
531 union {
532 __le32 data;
533 struct {
534 __le16 length; /* Data buffer length */
535 u8 typ_len_ext;
536 u8 cmd;
537 } flags;
538 } lower;
539 union {
540 __le32 data;
541 struct {
542 u8 status; /* Descriptor status */
543 u8 popts; /* Packet Options */
544 __le16 special;
545 } fields;
546 } upper;
547 };
548
549 /* Statistics counters collected by the MAC */
550 struct e1000_hw_stats {
551 u64 crcerrs;
552 u64 algnerrc;
553 u64 symerrs;
554 u64 rxerrc;
555 u64 mpc;
556 u64 scc;
557 u64 ecol;
558 u64 mcc;
559 u64 latecol;
560 u64 colc;
561 u64 dc;
562 u64 tncrs;
563 u64 sec;
564 u64 cexterr;
565 u64 rlec;
566 u64 xonrxc;
567 u64 xontxc;
568 u64 xoffrxc;
569 u64 xofftxc;
570 u64 fcruc;
571 u64 prc64;
572 u64 prc127;
573 u64 prc255;
574 u64 prc511;
575 u64 prc1023;
576 u64 prc1522;
577 u64 gprc;
578 u64 bprc;
579 u64 mprc;
580 u64 gptc;
581 u64 gorc;
582 u64 gotc;
583 u64 rnbc;
584 u64 ruc;
585 u64 rfc;
586 u64 roc;
587 u64 rjc;
588 u64 mgprc;
589 u64 mgpdc;
590 u64 mgptc;
591 u64 tor;
592 u64 tot;
593 u64 tpr;
594 u64 tpt;
595 u64 ptc64;
596 u64 ptc127;
597 u64 ptc255;
598 u64 ptc511;
599 u64 ptc1023;
600 u64 ptc1522;
601 u64 mptc;
602 u64 bptc;
603 u64 tsctc;
604 u64 tsctfc;
605 u64 iac;
606 u64 icrxptc;
607 u64 icrxatc;
608 u64 ictxptc;
609 u64 ictxatc;
610 u64 ictxqec;
611 u64 ictxqmtc;
612 u64 icrxdmtc;
613 u64 icrxoc;
614 u64 cbtmpc;
615 u64 htdpmc;
616 u64 cbrdpc;
617 u64 cbrmpc;
618 u64 rpthc;
619 u64 hgptc;
620 u64 htcbdpc;
621 u64 hgorc;
622 u64 hgotc;
623 u64 lenerrs;
624 u64 scvpc;
625 u64 hrmpc;
626 u64 doosync;
627 u64 o2bgptc;
628 u64 o2bspc;
629 u64 b2ospc;
630 u64 b2ogprc;
631 };
632
633 struct e1000_vf_stats {
634 u64 base_gprc;
635 u64 base_gptc;
636 u64 base_gorc;
637 u64 base_gotc;
638 u64 base_mprc;
639 u64 base_gotlbc;
640 u64 base_gptlbc;
641 u64 base_gorlbc;
642 u64 base_gprlbc;
643
644 u32 last_gprc;
645 u32 last_gptc;
646 u32 last_gorc;
647 u32 last_gotc;
648 u32 last_mprc;
649 u32 last_gotlbc;
650 u32 last_gptlbc;
651 u32 last_gorlbc;
652 u32 last_gprlbc;
653
654 u64 gprc;
655 u64 gptc;
656 u64 gorc;
657 u64 gotc;
658 u64 mprc;
659 u64 gotlbc;
660 u64 gptlbc;
661 u64 gorlbc;
662 u64 gprlbc;
663 };
664
665 struct e1000_phy_stats {
666 u32 idle_errors;
667 u32 receive_errors;
668 };
669
670 struct e1000_host_mng_dhcp_cookie {
671 u32 signature;
672 u8 status;
673 u8 reserved0;
674 u16 vlan_id;
675 u32 reserved1;
676 u16 reserved2;
677 u8 reserved3;
678 u8 checksum;
679 };
680
681 /* Host Interface "Rev 1" */
682 struct e1000_host_command_header {
683 u8 command_id;
684 u8 command_length;
685 u8 command_options;
686 u8 checksum;
687 };
688
689 #define E1000_HI_MAX_DATA_LENGTH 252
690 struct e1000_host_command_info {
691 struct e1000_host_command_header command_header;
692 u8 command_data[E1000_HI_MAX_DATA_LENGTH];
693 };
694
695 /* Host Interface "Rev 2" */
696 struct e1000_host_mng_command_header {
697 u8 command_id;
698 u8 checksum;
699 u16 reserved1;
700 u16 reserved2;
701 u16 command_length;
702 };
703
704 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
705 struct e1000_host_mng_command_info {
706 struct e1000_host_mng_command_header command_header;
707 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
708 };
709
710 #include "e1000_mac.h"
711 #include "e1000_phy.h"
712 #include "e1000_nvm.h"
713 #include "e1000_manage.h"
714 #include "e1000_mbx.h"
715
716 /* Function pointers for the MAC. */
717 struct e1000_mac_operations {
718 s32 (*init_params)(struct e1000_hw *);
719 s32 (*id_led_init)(struct e1000_hw *);
720 s32 (*blink_led)(struct e1000_hw *);
721 bool (*check_mng_mode)(struct e1000_hw *);
722 s32 (*check_for_link)(struct e1000_hw *);
723 s32 (*cleanup_led)(struct e1000_hw *);
724 void (*clear_hw_cntrs)(struct e1000_hw *);
725 void (*clear_vfta)(struct e1000_hw *);
726 s32 (*get_bus_info)(struct e1000_hw *);
727 void (*set_lan_id)(struct e1000_hw *);
728 s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
729 s32 (*led_on)(struct e1000_hw *);
730 s32 (*led_off)(struct e1000_hw *);
731 void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
732 s32 (*reset_hw)(struct e1000_hw *);
733 s32 (*init_hw)(struct e1000_hw *);
734 void (*shutdown_serdes)(struct e1000_hw *);
735 void (*power_up_serdes)(struct e1000_hw *);
736 s32 (*setup_link)(struct e1000_hw *);
737 s32 (*setup_physical_interface)(struct e1000_hw *);
738 s32 (*setup_led)(struct e1000_hw *);
739 void (*write_vfta)(struct e1000_hw *, u32, u32);
740 void (*config_collision_dist)(struct e1000_hw *);
741 int (*rar_set)(struct e1000_hw *, u8*, u32);
742 s32 (*read_mac_addr)(struct e1000_hw *);
743 s32 (*validate_mdi_setting)(struct e1000_hw *);
744 s32 (*set_obff_timer)(struct e1000_hw *, u32);
745 s32 (*acquire_swfw_sync)(struct e1000_hw *, u16);
746 void (*release_swfw_sync)(struct e1000_hw *, u16);
747 };
748
749 /* When to use various PHY register access functions:
750 *
751 * Func Caller
752 * Function Does Does When to use
753 * ~~~~~~~~~~~~ ~~~~~ ~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
754 * X_reg L,P,A n/a for simple PHY reg accesses
755 * X_reg_locked P,A L for multiple accesses of different regs
756 * on different pages
757 * X_reg_page A L,P for multiple accesses of different regs
758 * on the same page
759 *
760 * Where X=[read|write], L=locking, P=sets page, A=register access
761 *
762 */
763 struct e1000_phy_operations {
764 s32 (*init_params)(struct e1000_hw *);
765 s32 (*acquire)(struct e1000_hw *);
766 s32 (*cfg_on_link_up)(struct e1000_hw *);
767 s32 (*check_polarity)(struct e1000_hw *);
768 s32 (*check_reset_block)(struct e1000_hw *);
769 s32 (*commit)(struct e1000_hw *);
770 s32 (*force_speed_duplex)(struct e1000_hw *);
771 s32 (*get_cfg_done)(struct e1000_hw *hw);
772 s32 (*get_cable_length)(struct e1000_hw *);
773 s32 (*get_info)(struct e1000_hw *);
774 s32 (*set_page)(struct e1000_hw *, u16);
775 s32 (*read_reg)(struct e1000_hw *, u32, u16 *);
776 s32 (*read_reg_locked)(struct e1000_hw *, u32, u16 *);
777 s32 (*read_reg_page)(struct e1000_hw *, u32, u16 *);
778 void (*release)(struct e1000_hw *);
779 s32 (*reset)(struct e1000_hw *);
780 s32 (*set_d0_lplu_state)(struct e1000_hw *, bool);
781 s32 (*set_d3_lplu_state)(struct e1000_hw *, bool);
782 s32 (*write_reg)(struct e1000_hw *, u32, u16);
783 s32 (*write_reg_locked)(struct e1000_hw *, u32, u16);
784 s32 (*write_reg_page)(struct e1000_hw *, u32, u16);
785 void (*power_up)(struct e1000_hw *);
786 void (*power_down)(struct e1000_hw *);
787 s32 (*read_i2c_byte)(struct e1000_hw *, u8, u8, u8 *);
788 s32 (*write_i2c_byte)(struct e1000_hw *, u8, u8, u8);
789 };
790
791 /* Function pointers for the NVM. */
792 struct e1000_nvm_operations {
793 s32 (*init_params)(struct e1000_hw *);
794 s32 (*acquire)(struct e1000_hw *);
795 s32 (*read)(struct e1000_hw *, u16, u16, u16 *);
796 void (*release)(struct e1000_hw *);
797 void (*reload)(struct e1000_hw *);
798 s32 (*update)(struct e1000_hw *);
799 s32 (*valid_led_default)(struct e1000_hw *, u16 *);
800 s32 (*validate)(struct e1000_hw *);
801 s32 (*write)(struct e1000_hw *, u16, u16, u16 *);
802 };
803
804 struct e1000_mac_info {
805 struct e1000_mac_operations ops;
806 u8 addr[ETH_ADDR_LEN];
807 u8 perm_addr[ETH_ADDR_LEN];
808
809 enum e1000_mac_type type;
810
811 u32 collision_delta;
812 u32 ledctl_default;
813 u32 ledctl_mode1;
814 u32 ledctl_mode2;
815 u32 mc_filter_type;
816 u32 tx_packet_delta;
817 u32 txcw;
818
819 u16 current_ifs_val;
820 u16 ifs_max_val;
821 u16 ifs_min_val;
822 u16 ifs_ratio;
823 u16 ifs_step_size;
824 u16 mta_reg_count;
825 u16 uta_reg_count;
826
827 /* Maximum size of the MTA register table in all supported adapters */
828 #define MAX_MTA_REG 128
829 u32 mta_shadow[MAX_MTA_REG];
830 u16 rar_entry_count;
831
832 u8 forced_speed_duplex;
833
834 bool adaptive_ifs;
835 bool has_fwsm;
836 bool arc_subsystem_valid;
837 bool asf_firmware_present;
838 bool autoneg;
839 bool autoneg_failed;
840 bool get_link_status;
841 bool in_ifs_mode;
842 bool report_tx_early;
843 enum e1000_serdes_link_state serdes_link_state;
844 bool serdes_has_link;
845 bool tx_pkt_filtering;
846 u32 max_frame_size;
847 };
848
849 struct e1000_phy_info {
850 struct e1000_phy_operations ops;
851 enum e1000_phy_type type;
852
853 enum e1000_1000t_rx_status local_rx;
854 enum e1000_1000t_rx_status remote_rx;
855 enum e1000_ms_type ms_type;
856 enum e1000_ms_type original_ms_type;
857 enum e1000_rev_polarity cable_polarity;
858 enum e1000_smart_speed smart_speed;
859
860 u32 addr;
861 u32 id;
862 u32 reset_delay_us; /* in usec */
863 u32 revision;
864
865 enum e1000_media_type media_type;
866
867 u16 autoneg_advertised;
868 u16 autoneg_mask;
869 u16 cable_length;
870 u16 max_cable_length;
871 u16 min_cable_length;
872
873 u8 mdix;
874
875 bool disable_polarity_correction;
876 bool is_mdix;
877 bool polarity_correction;
878 bool speed_downgraded;
879 bool autoneg_wait_to_complete;
880 };
881
882 struct e1000_nvm_info {
883 struct e1000_nvm_operations ops;
884 enum e1000_nvm_type type;
885 enum e1000_nvm_override override;
886
887 u32 flash_bank_size;
888 u32 flash_base_addr;
889
890 u16 word_size;
891 u16 delay_usec;
892 u16 address_bits;
893 u16 opcode_bits;
894 u16 page_size;
895 };
896
897 struct e1000_bus_info {
898 enum e1000_bus_type type;
899 enum e1000_bus_speed speed;
900 enum e1000_bus_width width;
901
902 u16 func;
903 u16 pci_cmd_word;
904 };
905
906 struct e1000_fc_info {
907 u32 high_water; /* Flow control high-water mark */
908 u32 low_water; /* Flow control low-water mark */
909 u16 pause_time; /* Flow control pause timer */
910 u16 refresh_time; /* Flow control refresh timer */
911 bool send_xon; /* Flow control send XON */
912 bool strict_ieee; /* Strict IEEE mode */
913 enum e1000_fc_mode current_mode; /* FC mode in effect */
914 enum e1000_fc_mode requested_mode; /* FC mode requested by caller */
915 };
916
917 struct e1000_mbx_operations {
918 s32 (*init_params)(struct e1000_hw *hw);
919 s32 (*read)(struct e1000_hw *, u32 *, u16, u16);
920 s32 (*write)(struct e1000_hw *, u32 *, u16, u16);
921 s32 (*read_posted)(struct e1000_hw *, u32 *, u16, u16);
922 s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16);
923 s32 (*check_for_msg)(struct e1000_hw *, u16);
924 s32 (*check_for_ack)(struct e1000_hw *, u16);
925 s32 (*check_for_rst)(struct e1000_hw *, u16);
926 };
927
928 struct e1000_mbx_stats {
929 u32 msgs_tx;
930 u32 msgs_rx;
931
932 u32 acks;
933 u32 reqs;
934 u32 rsts;
935 };
936
937 struct e1000_mbx_info {
938 struct e1000_mbx_operations ops;
939 struct e1000_mbx_stats stats;
940 u32 timeout;
941 u32 usec_delay;
942 u16 size;
943 };
944
945 struct e1000_dev_spec_82541 {
946 enum e1000_dsp_config dsp_config;
947 enum e1000_ffe_config ffe_config;
948 u32 tx_fifo_head;
949 u32 tx_fifo_start;
950 u32 tx_fifo_size;
951 u16 dsp_reset_counter;
952 u16 spd_default;
953 bool phy_init_script;
954 bool ttl_workaround;
955 };
956
957 struct e1000_dev_spec_82542 {
958 bool dma_fairness;
959 };
960
961 struct e1000_dev_spec_82543 {
962 u32 tbi_compatibility;
963 bool dma_fairness;
964 bool init_phy_disabled;
965 };
966
967 struct e1000_dev_spec_82571 {
968 bool laa_is_present;
969 u32 smb_counter;
970 E1000_MUTEX swflag_mutex;
971 };
972
973 struct e1000_dev_spec_80003es2lan {
974 bool mdic_wa_enable;
975 };
976
977 struct e1000_shadow_ram {
978 u16 value;
979 bool modified;
980 };
981
982 #define E1000_SHADOW_RAM_WORDS 2048
983
984 /* I218 PHY Ultra Low Power (ULP) states */
985 enum e1000_ulp_state {
986 e1000_ulp_state_unknown,
987 e1000_ulp_state_off,
988 e1000_ulp_state_on,
989 };
990
991 struct e1000_dev_spec_ich8lan {
992 bool kmrn_lock_loss_workaround_enabled;
993 struct e1000_shadow_ram shadow_ram[E1000_SHADOW_RAM_WORDS];
994 E1000_MUTEX nvm_mutex;
995 E1000_MUTEX swflag_mutex;
996 bool nvm_k1_enabled;
997 bool disable_k1_off;
998 bool eee_disable;
999 u16 eee_lp_ability;
1000 enum e1000_ulp_state ulp_state;
1001 bool ulp_capability_disabled;
1002 bool during_suspend_flow;
1003 bool during_dpg_exit;
1004 };
1005
1006 struct e1000_dev_spec_82575 {
1007 bool sgmii_active;
1008 bool global_device_reset;
1009 bool eee_disable;
1010 bool module_plugged;
1011 bool clear_semaphore_once;
1012 u32 mtu;
1013 struct sfp_e1000_flags eth_flags;
1014 u8 media_port;
1015 bool media_changed;
1016 };
1017
1018 struct e1000_dev_spec_vf {
1019 u32 vf_number;
1020 u32 v2p_mailbox;
1021 };
1022
1023 struct e1000_hw {
1024 void *back;
1025
1026 u8 *hw_addr;
1027 u8 *flash_address;
1028 unsigned long io_base;
1029
1030 struct e1000_mac_info mac;
1031 struct e1000_fc_info fc;
1032 struct e1000_phy_info phy;
1033 struct e1000_nvm_info nvm;
1034 struct e1000_bus_info bus;
1035 struct e1000_mbx_info mbx;
1036 struct e1000_host_mng_dhcp_cookie mng_cookie;
1037
1038 union {
1039 struct e1000_dev_spec_82541 _82541;
1040 struct e1000_dev_spec_82542 _82542;
1041 struct e1000_dev_spec_82543 _82543;
1042 struct e1000_dev_spec_82571 _82571;
1043 struct e1000_dev_spec_80003es2lan _80003es2lan;
1044 struct e1000_dev_spec_ich8lan ich8lan;
1045 struct e1000_dev_spec_82575 _82575;
1046 struct e1000_dev_spec_vf vf;
1047 } dev_spec;
1048
1049 u16 device_id;
1050 u16 subsystem_vendor_id;
1051 u16 subsystem_device_id;
1052 u16 vendor_id;
1053
1054 u8 revision_id;
1055 };
1056
1057 #include "e1000_82541.h"
1058 #include "e1000_82543.h"
1059 #include "e1000_82571.h"
1060 #include "e1000_80003es2lan.h"
1061 #include "e1000_ich8lan.h"
1062 #include "e1000_82575.h"
1063 #include "e1000_i210.h"
1064
1065 /* These functions must be implemented by drivers */
1066 void e1000_pci_clear_mwi(struct e1000_hw *hw);
1067 void e1000_pci_set_mwi(struct e1000_hw *hw);
1068 s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
1069 s32 e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
1070 void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
1071 void e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
1072
1073 #endif
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