usr/src/uts/sun/io/audio/drv/audiocs/audio_4231.h

   1 /*
   2  * CDDL HEADER START
   3  *
   4  * The contents of this file are subject to the terms of the
   5  * Common Development and Distribution License (the "License").
   6  * You may not use this file except in compliance with the License.
   7  *
   8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
   9  * or http://www.opensolaris.org/os/licensing.
  10  * See the License for the specific language governing permissions
  11  * and limitations under the License.
  12  *
  13  * When distributing Covered Code, include this CDDL HEADER in each
  14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
  15  * If applicable, add the following below this CDDL HEADER, with the
  16  * fields enclosed by brackets "[]" replaced with your own identifying
  17  * information: Portions Copyright [yyyy] [name of copyright owner]
  18  *
  19  * CDDL HEADER END
  20  */
  21 /*
  22  * Copyright 2010 Sun Microsystems, Inc.  All rights reserved.
  23  * Use is subject to license terms.
  24  */
  25
  26 #ifndef _AUDIO_4231_H
  27 #define _AUDIO_4231_H
  28
  29 #ifdef __cplusplus
  30 extern "C" {
  31 #endif
  32
  33 /*
  34  * Header file for the audiocs device driver.
  35  */
  36
  37 /*
  38  * Values returned by the AUDIO_GETDEV ioctl()
  39  */
  40 #define CS_DEV_NAME             "SUNW,CS4231"
  41 #define CS_DEV_CONFIG_ONBRD1    "onboard1"
  42 #define CS_DEV_VERSION          "a"     /* SS5                          */
  43 #define CS_DEV_VERSION_A        CS_DEV_VERSION
  44 #define CS_DEV_VERSION_B        "b"     /* Electron - internal loopback */
  45 #define CS_DEV_VERSION_C        "c"     /* Positron                     */
  46 #define CS_DEV_VERSION_D        "d"     /* PowerPC - Retired            */
  47 #define CS_DEV_VERSION_E        "e"     /* x86 - Retired                */
  48 #define CS_DEV_VERSION_F        "f"     /* Tazmo                        */
  49 #define CS_DEV_VERSION_G        "g"     /* Quark Audio Module           */
  50 #define CS_DEV_VERSION_H        "h"     /* Darwin                       */
  51
  52 /*
  53  * Driver supported configuration information
  54  */
  55 #define CS4231_NAME             "audiocs"
  56 #define CS4231_MOD_NAME         "CS4231 audio driver"
  57
  58 /*
  59  * Implementation specific header file for the audiocs device driver.
  60  */
  61
  62 #ifdef _KERNEL
  63
  64 enum {
  65         CTL_VOLUME = 0,
  66         CTL_IGAIN,
  67         CTL_MGAIN,
  68         CTL_INPUTS,
  69         CTL_OUTPUTS,
  70         CTL_MICBOOST,
  71         CTL_NUM
  72 };
  73
  74 typedef struct CS_engine CS_engine_t;
  75 typedef struct CS_ctrl CS_ctrl_t;
  76 typedef struct CS_state CS_state_t;
  77
  78 /*
  79  * These are the registers for the APC DMA channel interface to the
  80  * 4231. One handle provides access the CODEC and the DMA engine's
  81  * registers.
  82  */
  83
  84 struct cs4231_apc {
  85         uint32_t        dmacsr;         /* APC CSR */
  86         uint32_t        lpad[3];        /* PAD */
  87         uint32_t        dmacva;         /* Capture Virtual Address */
  88         uint32_t        dmacc;          /* Capture Count */
  89         uint32_t        dmacnva;        /* Capture Next VAddress */
  90         uint32_t        dmacnc;         /* Capture next count */
  91         uint32_t        dmapva;         /* Playback Virtual Address */
  92         uint32_t        dmapc;          /* Playback Count */
  93         uint32_t        dmapnva;        /* Playback Next VAddress */
  94         uint32_t        dmapnc;         /* Playback Next Count */
  95 };
  96 typedef struct cs4231_apc cs4231_apc_t;
  97
  98 #define APC_DMACSR      state->cs_regs->apc.dmacsr
  99 #define APC_DMACVA      state->cs_regs->apc.dmacva
 100 #define APC_DMACC       state->cs_regs->apc.dmacc
 101 #define APC_DMACNVA     state->cs_regs->apc.dmacnva
 102 #define APC_DMACNC      state->cs_regs->apc.dmacnc
 103 #define APC_DMAPVA      state->cs_regs->apc.dmapva
 104 #define APC_DMAPC       state->cs_regs->apc.dmapc
 105 #define APC_DMAPNVA     state->cs_regs->apc.dmapnva
 106 #define APC_DMAPNC      state->cs_regs->apc.dmapnc
 107
 108 /*
 109  * APC CSR Register bit definitions
 110  */
 111
 112 #define APC_RESET       0x00000001u     /* Reset the DMA engine, R/W */
 113 #define APC_CDMA_GO     0x00000004u     /* Capture DMA go, R/W */
 114 #define APC_PDMA_GO     0x00000008u     /* Playback DMA go, R/W */
 115 #define APC_LOOP_BACK   0x00000010u     /* Loopback, Capture to Play */
 116 #define APC_COD_PDWN    0x00000020u     /* CODEC power down, R/W */
 117 #define APC_C_ABORT     0x00000040u     /* Capture abort, R/W */
 118 #define APC_P_ABORT     0x00000080u     /* Play abort, R/W */
 119 #define APC_CXI_EN      0x00000100u     /* Capture expired int. enable, R/W */
 120 #define APC_CXI         0x00000200u     /* Capture expired interrupt, R/W */
 121 #define APC_CD          0x00000400u     /* Capture next VA dirty, R/O */
 122 #define APC_CX          0x00000800u     /* Capture expired (pipe empty), R/O */
 123 #define APC_PMI_EN      0x00001000u     /* Play pipe empty int. enable, R/W */
 124 #define APC_PD          0x00002000u     /* Playback next VA dirty, R/O */
 125 #define APC_PM          0x00004000u     /* Play pipe empty, R/O */
 126 #define APC_PMI         0x00008000u     /* Play pipe empty interrupt, R/W */
 127 #define APC_EIE         0x00010000u     /* Error interrupt enable, R/W */
 128 #define APC_CIE         0x00020000u     /* Capture interrupt enable, R/W */
 129 #define APC_PIE         0x00040000u     /* Playback interrupt enable, R/W */
 130 #define APC_IE          0x00080000u     /* Interrupt enable, R/W */
 131 #define APC_EI          0x00100000u     /* Error interrupt, R/W */
 132 #define APC_CI          0x00200000u     /* Capture interrupt, R/W */
 133 #define APC_PI          0x00400000u     /* Playback interrupt, R/W */
 134 #define APC_IP          0x00800000u     /* Interrupt Pending, R/O */
 135 #define APC_ID          0xff000000u     /* ID bits, set to 7E, R/O */
 136
 137 #define APC_ID_VALUE    0x7E000000u     /* ID read from CSR */
 138 #define APC_CLEAR_RESET_VALUE   0x00
 139
 140 #define APC_PINTR_MASK          (APC_PI|APC_PMI)
 141 #define APC_CINTR_MASK          (APC_CI|APC_CXI)
 142 #define APC_COMMON_MASK         (APC_IP|APC_EI)
 143 #define APC_PINTR_ENABLE        (APC_PIE|APC_PMI_EN)
 144 #define APC_CINTR_ENABLE        (APC_CIE|APC_CXI_EN)
 145 #define APC_COMMON_ENABLE       (APC_IE|APC_EIE)
 146
 147 #define APC_PLAY_ENABLE         (APC_PDMA_GO)
 148 #define APC_PLAY_DISABLE        (APC_PDMA_GO)
 149 #define APC_CAP_ENABLE          (APC_CDMA_GO)
 150 #define APC_CAP_DISABLE         (APC_CDMA_GO)
 151
 152 /*
 153  * These are the registers for the EBUS2 DMA channel interface to the
 154  * 4231. One struct per channel for playback and record, therefore there
 155  * individual handles for the CODEC and the two DMA engines.
 156  */
 157
 158 struct cs4231_eb2regs {
 159         uint32_t        eb2csr;         /* Ebus 2 csr */
 160         uint32_t        eb2acr;         /* ebus 2 Addrs */
 161         uint32_t        eb2bcr;         /* ebus 2 counts */
 162 };
 163 typedef struct cs4231_eb2regs cs4231_eb2regs_t;
 164
 165 #define EB2_PLAY_CSR    state->cs_eb2_regs.play->eb2csr
 166 #define EB2_PLAY_ACR    state->cs_eb2_regs.play->eb2acr
 167 #define EB2_PLAY_BCR    state->cs_eb2_regs.play->eb2bcr
 168 #define EB2_REC_CSR     state->cs_eb2_regs.record->eb2csr
 169 #define EB2_REC_ACR     state->cs_eb2_regs.record->eb2acr
 170 #define EB2_REC_BCR     state->cs_eb2_regs.record->eb2bcr
 171 #define EB2_AUXIO_REG   state->cs_eb2_regs.auxio
 172
 173 /*
 174  * Audio auxio register definitions
 175  */
 176 #define EB2_AUXIO_COD_PDWN      0x00000001u     /* power down Codec */
 177
 178 /*
 179  * EBUS 2 CSR definitions
 180  */
 181
 182 #define EB2_INT_PEND            0x00000001u     /* Interrupt pending, R/O */
 183 #define EB2_ERR_PEND            0x00000002u     /* Error interrupt, R/O */
 184 #define EB2_DRAIN               0x00000004u     /* FIFO being drained, R/O */
 185 #define EB2_INT_EN              0x00000010u     /* Enable interrupts, R/W */
 186 #define EB2_RESET               0x00000080u     /* Reset DMA engine, R/W */
 187 #define EB2_WRITE               0x00000100u     /* DMA direction (to mem) R/W */
 188 #define EB2_READ                0x00000000u     /* DMA direction (to dev) R/W */
 189 #define EB2_EN_DMA              0x00000200u     /* Enable DMA, R/W */
 190 #define EB2_CYC_PENDING         0x00000400u     /* DMA cycle pending, R/O */
 191 #define EB2_DIAG_RD_DONE        0x00000800u     /* Diag RD done, R/O */
 192 #define EB2_DIAG_WR_DONE        0x00001000u     /* Diag WR done, R/O */
 193 #define EB2_EN_CNT              0x00002000u     /* Enable byte count, R/W */
 194 #define EB2_TC                  0x00004000u     /* Terminal count, R/W */
 195 #define EB2_DIS_CSR_DRN         0x00010000u     /* Dis. drain with W-CSR, R/W */
 196 #define EB2_16                  0x00000000u     /* 19,18 == 0,0, R/W */
 197 #define EB2_32                  0x00040000u     /* 19,18 == 0,1, R/W */
 198 #define EB2_4                   0x00080000u     /* 19,18 == 1,0, R/W */
 199 #define EB2_64                  0x000C0000u     /* 19,18 == 1,1, R/W */
 200 #define EB2_DIAG_EN             0x00100000u     /* DMA diag. enable, R/W */
 201 #define EB2_DIS_ERR_PEND        0x00400000u     /* Disable Error int., R/W */
 202 #define EB2_TCI_DIS             0x00800000u     /* Disable TC int., R/W */
 203 #define EB2_EN_NEXT             0x01000000u     /* Next addr. enabled, R/W */
 204 #define EB2_DMA_ON              0x02000000u     /* DMA engine enabled, R/O */
 205 #define EB2_A_LOADED            0x04000000u     /* Address loaded, R/O */
 206 #define EB2_NA_LOADED           0x08000000u     /* Next add. loaded, R/O */
 207 #define EB2_DEV_ID              0xf0000000u     /* Device ID -0x0C, R/O */
 208
 209 #define EB2_ID_VALUE            0xC0000000u     /* ID read from CSR */
 210 #define EB2_PCLEAR_RESET_VALUE  (EB2_READ|EB2_EN_NEXT|EB2_EN_CNT)
 211 #define EB2_RCLEAR_RESET_VALUE  (EB2_WRITE|EB2_EN_NEXT|EB2_EN_CNT)
 212
 213 #define EB2_PLAY_ENABLE         (EB2_EN_DMA|EB2_EN_CNT|EB2_64|\
 214                                         EB2_PCLEAR_RESET_VALUE)
 215
 216 #define EB2_REC_ENABLE          (EB2_EN_DMA|EB2_EN_CNT|EB2_64|\
 217                                         EB2_RCLEAR_RESET_VALUE)
 218
 219 #define EB2_FIFO_DRAIN          (EB2_DRAIN|EB2_CYC_PENDING)
 220
 221 /*
 222  * Misc. defines
 223  */
 224 #define CS4231_REGS                     (32)
 225 #define CS4231_NCOMPONENTS              (1)
 226 #define CS4231_COMPONENT                (0)
 227 #define CS4231_PWR_OFF                  (0)
 228 #define CS4231_PWR_ON                   (1)
 229 #define CS4231_TIMEOUT                  (100000)
 230 #define CS4231_300MS                    (300*1000)
 231 #define CS4231_PLAY                     0
 232 #define CS4231_REC                      1
 233 #define CS4231_NFRAMES                  4096
 234 #define CS4231_NFRAGS                   2
 235 #define CS4231_FRAGSZ                   ((CS4231_NFRAMES / CS4231_NFRAGS) * 4)
 236 #define CS4231_BUFSZ                    (CS4231_NFRAMES * 4)
 237
 238 /*
 239  * Supported dma engines and the ops vector
 240  */
 241 enum cs_dmae_types {APC_DMA, EB2_DMA};
 242 typedef enum cs_dmae_types cs_dmae_types_e;
 243
 244 /*
 245  * Hardware registers
 246  */
 247 struct cs4231_pioregs {
 248         uint8_t iar;            /* index address register */
 249         uint8_t pad1[3];                /* pad */
 250         uint8_t idr;            /* indexed data register */
 251         uint8_t pad2[3];                /* pad */
 252         uint8_t statr;          /* status register */
 253         uint8_t pad3[3];                /* pad */
 254         uint8_t piodr;          /* PIO data regsiter */
 255         uint8_t pad4[3];
 256 };
 257 typedef struct cs4231_pioregs cs4231_pioregs_t;
 258
 259
 260 struct cs4231_eb2 {
 261         cs4231_eb2regs_t        *play;          /* play EB2 registers */
 262         cs4231_eb2regs_t        *record;        /* record EB2 registers */
 263         uint_t                  *auxio;         /* aux io - power down */
 264 };
 265 typedef struct cs4231_eb2 cs4231_eb2_t;
 266
 267 struct cs4231_regs {
 268         cs4231_pioregs_t        codec;          /* CS4231 CODEC registers */
 269         cs4231_apc_t            apc;            /* gets mapped with CODEC */
 270 };
 271 typedef struct cs4231_regs cs4231_regs_t;
 272
 273 #define CS4231_IAR      state->cs_regs->codec.iar       /* Index Add. Reg. */
 274 #define CS4231_IDR      state->cs_regs->codec.idr       /* Index Data Reg. */
 275 #define CS4231_STATUS   state->cs_regs->codec.statr     /* Status Reg. */
 276 #define CS4231_PIODR    state->cs_regs->codec.piodr     /* PIO Data Reg. */
 277
 278 /*
 279  * Misc. state enumerations and structures
 280  */
 281 struct cs4231_handle {
 282         ddi_acc_handle_t        cs_codec_hndl;  /* CODEC handle, APC & EB2 */
 283         ddi_acc_handle_t        cs_eb2_play_hndl; /* EB2 only, play handle */
 284         ddi_acc_handle_t        cs_eb2_rec_hndl; /* EB2 only, record handle */
 285         ddi_acc_handle_t        cs_eb2_auxio_hndl; /* EB2 only, auxio handle */
 286 };
 287 typedef struct cs4231_handle cs4231_handle_t;
 288 #define CODEC_HANDLE    state->cs_handles.cs_codec_hndl
 289 #define APC_HANDLE      state->cs_handles.cs_codec_hndl
 290 #define EB2_PLAY_HNDL   state->cs_handles.cs_eb2_play_hndl
 291 #define EB2_REC_HNDL    state->cs_handles.cs_eb2_rec_hndl
 292 #define EB2_AUXIO_HNDL  state->cs_handles.cs_eb2_auxio_hndl
 293
 294 /*
 295  * CS_port_t - per port (playback or record) state
 296  */
 297 struct CS_engine {
 298         CS_state_t              *ce_state;
 299         audio_engine_t          *ce_engine;
 300         int                     ce_num;
 301         unsigned                ce_syncdir;
 302         boolean_t               ce_started;
 303         uint64_t                ce_count;
 304
 305         caddr_t                 ce_kaddr;
 306         ddi_dma_handle_t        ce_dmah;
 307         ddi_acc_handle_t        ce_acch;
 308         uint32_t                ce_paddr;
 309         uint32_t                ce_curoff;
 310         int                     ce_curidx;
 311
 312         /* registers (EB2 only) */
 313         ddi_acc_handle_t        ce_regsh;
 314         cs4231_eb2regs_t        *ce_eb2regs;    /* EB2 registers */
 315
 316         /* codec enable */
 317         uint8_t                 ce_codec_en;
 318 };
 319
 320 struct CS_ctrl {
 321         CS_state_t              *cc_state;
 322         audio_ctrl_t            *cc_ctrl;
 323         uint32_t                cc_num;
 324         uint64_t                cc_val;
 325 };
 326
 327 /*
 328  * CS_state_t - per instance state and operation data
 329  */
 330 struct CS_state {
 331         kmutex_t                cs_lock;        /* state protection lock */
 332         kcondvar_t              cs_cv;          /* suspend/resume cond. var. */
 333         dev_info_t              *cs_dip;        /* used by cs4231_getinfo() */
 334         audio_dev_t             *cs_adev;       /* audio device state */
 335
 336         cs_dmae_types_e         cs_dma_engine;  /* dma engine for this h/w */
 337         struct cs4231_dma_ops   *cs_dma_ops;    /* dma engine ops vector */
 338         cs4231_regs_t           *cs_regs;       /* hardware registers */
 339         cs4231_eb2_t            cs_eb2_regs;    /* eb2 DMA registers */
 340         cs4231_handle_t         cs_handles;     /* hardware handles */
 341
 342         boolean_t               cs_suspended;   /* power management state */
 343         boolean_t               cs_powered;     /* device powered up? */
 344
 345         CS_engine_t             *cs_engines[2];
 346
 347         boolean_t               cs_revA;        /* B_TRUE if Rev A CODEC */
 348         uint8_t                 cs_save[CS4231_REGS];   /* PM reg. storage */
 349
 350         /*
 351          * Control related fields.
 352          */
 353         uint64_t                cs_imask;
 354         uint64_t                cs_omask;
 355         uint64_t                cs_omod;        /* modifiable ports */
 356
 357         CS_ctrl_t               *cs_ogain;
 358         CS_ctrl_t               *cs_igain;
 359         CS_ctrl_t               *cs_micboost;
 360         CS_ctrl_t               *cs_mgain;
 361         CS_ctrl_t               *cs_outputs;
 362         CS_ctrl_t               *cs_inputs;
 363 };
 364
 365 /*
 366  * DMA ops vector definition
 367  */
 368 struct cs4231_dma_ops {
 369         char    *dma_device;
 370         ddi_dma_attr_t  *cs_dma_attr;
 371         int     (*cs_dma_map_regs)(CS_state_t *);
 372         void    (*cs_dma_unmap_regs)(CS_state_t *);
 373         void    (*cs_dma_reset)(CS_state_t *);
 374         int     (*cs_dma_start)(CS_engine_t *);
 375         void    (*cs_dma_stop)(CS_engine_t *);
 376         void    (*cs_dma_power)(CS_state_t *, int);
 377         void    (*cs_dma_reload)(CS_engine_t *);
 378         uint32_t        (*cs_dma_addr)(CS_engine_t *);
 379 };
 380 typedef struct cs4231_dma_ops cs4231_dma_ops_t;
 381
 382 extern cs4231_dma_ops_t cs4231_apcdma_ops;
 383 extern cs4231_dma_ops_t cs4231_eb2dma_ops;
 384
 385 #define CS4231_DMA_MAP_REGS(S)          ((S)->cs_dma_ops->cs_dma_map_regs)(S)
 386 #define CS4231_DMA_UNMAP_REGS(S)        ((S)->cs_dma_ops->cs_dma_unmap_regs)(S)
 387 #define CS4231_DMA_RESET(S)             ((S)->cs_dma_ops->cs_dma_reset)(S)
 388 #define CS4231_DMA_START(S, E)          ((S)->cs_dma_ops->cs_dma_start)(E)
 389 #define CS4231_DMA_STOP(S, E)           ((S)->cs_dma_ops->cs_dma_stop)(E)
 390 #define CS4231_DMA_POWER(S, L)          ((S)->cs_dma_ops->cs_dma_power)(S, L)
 391 #define CS4231_DMA_ATTR(S)              ((S)->cs_dma_ops->cs_dma_attr)
 392 #define CS4231_DMA_RELOAD(S, E)         ((S)->cs_dma_ops->cs_dma_reload)(E)
 393 #define CS4231_DMA_ADDR(S, E)           ((S)->cs_dma_ops->cs_dma_addr)(E)
 394
 395 /*
 396  * Useful bit twiddlers
 397  */
 398 #define CS4231_RETRIES          10
 399
 400 #define OR_SET_WORD(handle, addr, val)                                  \
 401         ddi_put32((handle), (uint_t *)(addr),                           \
 402                 (ddi_get32((handle), (uint_t *)(addr)) | (uint_t)(val)))
 403
 404 #define AND_SET_WORD(handle, addr, val)                                 \
 405         ddi_put32((handle), (uint_t *)(addr),                           \
 406                 (ddi_get32((handle), (uint_t *)(addr)) & (uint_t)(val)))
 407
 408 /*
 409  * CS4231 Register Set Definitions
 410  */
 411 /* Index Address Register */
 412 #define IAR_ADDRESS_MASK        0x1f    /* mask for index addresses, R/W */
 413 #define IAR_TRD                 0x20    /* Transfer Request Disable, R/W */
 414 #define IAR_MCE                 0x40    /* Mode Change Enable, R/W */
 415 #define IAR_INIT                0x80    /* 4231 init cycle, R/O */
 416
 417 /* Status Register */
 418 #define STATUS_INT              0x01    /* Interrupt status, R/O */
 419 #define STATUS_PRDY             0x02    /* Playback Data Ready */
 420 #define STATUS_PLR              0x04    /* Playback Left/Right sample */
 421 #define STATUS_PUL              0x08    /* Playback Upper/Lower byte */
 422 #define STATUS_SER              0x10    /* Sample Error, see Index 24 */
 423 #define STATUS_CRDY             0x20    /* Capture Data Ready */
 424 #define STATUS_CLR              0x40    /* Capture Left/Right sample */
 425 #define STATUS_CUL              0x80    /* Capture Upper/Lower byte */
 426 #define STATUS_RESET            0x00    /* Reset the status register */
 427
 428 /* Index 00 - Left ADC Input Control, Modes 1&2 */
 429 #define LADCI_REG               0x00    /* Left ADC Register */
 430 #define LADCI_GAIN_MASK         0x0f    /* Left gain mask, 1.5 dB/step */
 431 #define LADCI_LMGE              0x20    /* Left Mic Gain Enable, 20 dB stage */
 432 #define LADCI_LLINE             0x00    /* Left Line in enable */
 433 #define LADCI_LAUX1             0x40    /* Left AUX1 in enable */
 434 #define LADCI_LMIC              0x80    /* Left MIC in enable */
 435 #define LADCI_LLOOP             0xc0    /* Left Loopback enable */
 436 #define LADCI_IN_MASK           0xc0    /* Left input mask */
 437 #define LADCI_VALID_MASK        0xef    /* Left valid bits mask */
 438
 439 /* Index 01 - Right ADC Input Control, Modes 1&2 */
 440 #define RADCI_REG               0x01    /* Right ADC Register */
 441 #define RADCI_GAIN_MASK         0x0f    /* Right gain mask, 1.5 dB/step */
 442 #define RADCI_RMGE              0x20    /* Right Mic Gain Enable, 20 dB stage */
 443 #define RADCI_RLINE             0x00    /* Right Line in enable */
 444 #define RADCI_RAUX1             0x40    /* Right AUX1 in enable */
 445 #define RADCI_RMIC              0x80    /* Right MIC in enable */
 446 #define RADCI_RLOOP             0xc0    /* Right Loopback enable */
 447 #define RADCI_IN_MASK           0xc0    /* Right input mask */
 448 #define RADCI_VALID_MASK        0xef    /* Right valid bits mask */
 449
 450 /* Index 02 - Left Aux #1 Input Control, Modes 1&2 */
 451 #define LAUX1_REG               0x02    /* Left Aux#1 Register */
 452 #define LAUX1_GAIN_MASK         0x1f    /* Left Aux#1 gain mask, 1.5 dB/step */
 453 #define LAUX1_LX1M              0x80    /* Left Aux#1 mute */
 454 #define LAUX1_UNITY_GAIN        0x08    /* Left Aux#1 unity gain */
 455 #define LAUX1_VALID_MASK        0x9f    /* Left valid bits mask */
 456
 457 /* Index 03 - Right Aux #1 Input Control, Modes 1&2 */
 458 #define RAUX1_REG               0x03    /* Right Aux#1 Register */
 459 #define RAUX1_GAIN_MASK         0x1f    /* Right Aux#1 gain mask, 1.5 dB/step */
 460 #define RAUX1_RX1M              0x80    /* Right Aux#1 mute */
 461 #define RAUX1_UNITY_GAIN        0x08    /* Right Aux#1 unity gain */
 462 #define RAUX1_VALID_MASK        0x9f    /* Right valid bits mask */
 463
 464 /* Index 04 - Left Aux #2 Input Control, Modes 1&2 */
 465 #define LAUX2_REG               0x04    /* Left Aux#2 Register */
 466 #define LAUX2_GAIN_MASK         0x1f    /* Left Aux#2 gain mask, 1.5 dB/step */
 467 #define LAUX2_LX2M              0x80    /* Left Aux#2 mute */
 468 #define LAUX2_UNITY_GAIN        0x08    /* Left Aux#2 unity gain */
 469 #define LAUX2_VALID_MASK        0x9f    /* Left valid bits mask */
 470
 471 /* Index 05 - Right Aux #2 Input Control, Modes 1&2 */
 472 #define RAUX2_REG               0x05    /* Right Aux#2 Register */
 473 #define RAUX2_GAIN_MASK         0x1f    /* Right Aux#2 gain mask, 1.5 dB/step */
 474 #define RAUX2_RX2M              0x80    /* Right Aux#2 mute */
 475 #define RAUX2_UNITY_GAIN        0x08    /* Right Aux#2 unity gain */
 476 #define RAUX2_VALID_MASK        0x9f    /* Right valid bits mask */
 477
 478 /* Index 06 - Left DAC Output Control, Modes 1&2 */
 479 #define LDACO_REG               0x06    /* Left DAC Register */
 480 #define LDACO_ATTEN_MASK        0x3f    /* Left attenuation mask, 1.5 dB/setp */
 481 #define LDACO_LDM               0x80    /* Left mute */
 482 #define LDACO_MID_GAIN          0x11    /* Left DAC mid gain */
 483 #define LDAC0_VALID_MASK        0xbf    /* Left valid bits mask */
 484
 485 /* Index 07 - Right DAC Output Control, Modes 1&2 */
 486 #define RDACO_REG               0x07    /* Right DAC Register */
 487 #define RDACO_ATTEN_MASK        0x3f    /* Right atten. mask, 1.5 dB/setp */
 488 #define RDACO_RDM               0x80    /* Right mute */
 489 #define RDACO_MID_GAIN          0x11    /* Right DAC mid gain */
 490 #define RDAC0_VALID_MASK        0xbf    /* Right valid bits mask */
 491
 492 /* Index 08 - Sample Rate and Data Format, Mode 2 only */
 493 #define FSDF_REG                0x08    /* Sample Rate & Data Format Register */
 494 #define FS_5510                 0x01    /* XTAL2, Freq. Divide #0 */
 495 #define FS_6620                 0x0f    /* XTAL2, Freq. Divide #7 */
 496 #define FS_8000                 0x00    /* XTAL1, Freq. Divide #0 */
 497 #define FS_9600                 0x0e    /* XTAL2, Freq. Divide #7 */
 498 #define FS_11025                0x03    /* XTAL2, Freq. Divide #1 */
 499 #define FS_16000                0x02    /* XTAL1, Freq. Divide #1 */
 500 #define FS_18900                0x05    /* XTAL2, Freq. Divide #2 */
 501 #define FS_22050                0x07    /* XTAL2, Freq. Divide #3 */
 502 #define FS_27420                0x04    /* XTAL1, Freq. Divide #2 */
 503 #define FS_32000                0x06    /* XTAL1, Freq. Divide #3 */
 504 #define FS_33075                0x0d    /* XTAL2, Freq. Divide #6 */
 505 #define FS_37800                0x09    /* XTAL2, Freq. Divide #4 */
 506 #define FS_44100                0x0b    /* XTAL2, Freq. Divide #5 */
 507 #define FS_48000                0x0c    /* XTAL1, Freq. Divide #6 */
 508 #define PDF_STEREO              0x10    /* Stereo Playback */
 509 #define PDF_MONO                0x00    /* Mono Playback */
 510 #define PDF_LINEAR8             0x00    /* Linear, 8-bit unsigned */
 511 #define PDF_ULAW8               0x20    /* u-Law, 8-bit companded */
 512 #define PDF_LINEAR16LE          0x40    /* Linear, 16-bit signed, little end. */
 513 #define PDF_ALAW8               0x60    /* A-Law, 8-bit companded */
 514 #define PDF_ADPCM4              0xa0    /* ADPCM, 4-bit, IMA compatible */
 515 #define PDF_LINEAR16BE          0xc0    /* Linear, 16-bit signed, big endian */
 516 #define FSDF_VALID_MASK         0xff    /* Valid bits mask */
 517 #ifdef  _BIG_ENDIAN
 518 #define PDF_LINEAR16NE          PDF_LINEAR16BE
 519 #else
 520 #define PDF_LINEAR16NE          PDF_LINEAR16LE
 521 #endif
 522
 523 /* Index 09 - Interface Configuration, Mode 1&2 */
 524 #define INTC_REG                0x09    /* Interrupt Configuration Register */
 525 #define INTC_PEN                0x01    /* Playback enable */
 526 #define INTC_CEN                0x02    /* Capture enable */
 527 #define INTC_SDC                0x04    /* Single DMA channel */
 528 #define INTC_DDC                0x00    /* Dual DMA channels */
 529 #define INTC_ACAL               0x08    /* Auto-Calibrate Enable */
 530 #define INTC_PPIO               0x40    /* Playback vi PIO */
 531 #define INTC_PDMA               0x00    /* Playback vi DMA */
 532 #define INTC_CPIO               0x80    /* Capture vi PIO */
 533 #define INTC_CDMA               0x00    /* Capture vi DMA */
 534 #define INTC_VALID_MASK         0xcf    /* Valid bits mask */
 535
 536 /* Index 10 - Pin Control, Mode 1&2 */
 537 #define PC_REG                  0x0a    /* Pin Control Register */
 538 #define PC_IEN                  0x02    /* Interrupt Enable */
 539 #define PC_DEN                  0x04    /* Dither Enable */
 540 #define PC_XCTL0                0x40    /* External control 0 */
 541 #define PC_LINE_OUT_MUTE        0x40    /* Line Out Mute */
 542 #define PC_XCTL1                0x80    /* External control 1 */
 543 #define PC_HEADPHONE_MUTE       0x80    /* Headphone Mute */
 544 #define PC_VALID_MASK           0xca    /* Valid bits mask */
 545
 546 /* Index 11 - Error Status and Initialization, Mode 1&2 */
 547 #define ESI_REG                 0x0b    /* Error Status & Init. Register */
 548 #define ESI_ORL_MASK            0x03    /* Left ADC Overrange */
 549 #define ESI_ORR_MASK            0x0c    /* Right ADC Overrange */
 550 #define ESI_DRS                 0x10    /* DRQ status */
 551 #define ESI_ACI                 0x20    /* Auto-Calibrate In Progress */
 552 #define ESI_PUR                 0x40    /* Playback Underrun */
 553 #define ESI_COR                 0x80    /* Capture Overrun */
 554 #define ESI_VALID_MASK          0xff    /* Valid bits mask */
 555
 556 /* Index 12 - Mode and ID, Modes 1&2 */
 557 #define MID_REG                 0x0c    /* Mode and ID Register */
 558 #define MID_ID_MASK             0x0f    /* CODEC ID */
 559 #define MID_MODE2               0x40    /* Mode 2 enable */
 560 #define MID_VALID_MASK          0xcf    /* Valid bits mask */
 561
 562 /* Index 13 - Loopback Control, Modes 1&2 */
 563 #define LC_REG                  0x0d    /* Loopback Control Register */
 564 #define LC_LBE                  0x01    /* Loopback Enable */
 565 #define LC_ATTEN_MASK           0xfc    /* Loopback attenuation mask */
 566 #define LC_OFF                  0x00    /* Loopback off */
 567 #define LC_VALID_MASK           0xfd    /* Valid bits mask */
 568
 569 /* Index 14 - Playback Upper Base, Mode 2 only */
 570 #define PUB_REG                 0x0e    /* Playback Upper Base Register */
 571 #define PUB_VALID_MASK          0xff    /* Valid bits mask */
 572
 573 /* Index 15 - Playback Lower Base, Mode 2 only */
 574 #define PLB_REG                 0x0f    /* Playback Lower Base Register */
 575 #define PLB_VALID_MASK          0xff    /* Valid bits mask */
 576
 577 /* Index 16 - Alternate Feature Enable 1, Mode 2 only */
 578 #define AFE1_REG                0x10    /* Alternate Feature Enable 1 Reg */
 579 #define AFE1_DACZ               0x01    /* DAC Zero */
 580 #define AFE1_TE                 0x40    /* Timer Enable */
 581 #define AFE1_OLB                0x80    /* Output Level Bit, 1=2.8Vpp, 0=2Vpp */
 582 #define AFE1_VALID_MASK         0xc1    /* Valid bits mask */
 583
 584 /* Index 17 - Alternate Feature Enable 2, Mode 2 only */
 585 #define AFE2_REG                0x11    /* Alternate Feature Enable 2 Reg */
 586 #define AFE2_HPF                0x01    /* High Pass Filter - DC blocking */
 587 #define AFE2_VALID_MASK         0x01    /* Valid bits mask */
 588
 589 /* Index 18 - Left Line Input Control, Mode 2 only */
 590 #define LLIC_REG                0x12    /* Left Line Input Control Register */
 591 #define LLIC_MIX_GAIN_MASK      0x1f    /* Left Mix Gain Mask, 1.5 dB/step */
 592 #define LLIC_LLM                0x80    /* Left Line Mute */
 593 #define LLIC_UNITY_GAIN         0x08    /* Left unit gain */
 594 #define LLIC_VALID_MASK         0x9f    /* Left valid bits mask */
 595
 596 /* Index 19 - Right Line Input Control, Mode 2 only */
 597 #define RLIC_REG                0x13    /* Right Line Input Control Register */
 598 #define RLIC_MIX_GAIN_MASK      0x1f    /* Right Mix Gain Mask, 1.5 dB/step */
 599 #define RLIC_RLM                0x80    /* Right Line Mute */
 600 #define RLIC_UNITY_GAIN         0x08    /* Right unit gain */
 601 #define RLIC_VALID_MASK         0x9f    /* Right valid bits mask */
 602
 603 /* Index 20 - Timer Lower Byte, Mode 2 only */
 604 #define TLB_REG                 0x14    /* Timer Lower Byte Register */
 605 #define TLB_VALID_MASK          0xff    /* Valid bits mask */
 606
 607 /* Index 21 - Timer Upper Byte, Mode 2 only */
 608 #define TUB_REG                 0x15    /* Timer Upper Byte Register */
 609 #define TUB_VALID_MASK          0xff    /* Valid bits mask */
 610
 611 /* Index 22 and 23 are reserved */
 612
 613 /* Index 24 - Alternate Feature Status, Mode 2 only */
 614 #define AFS_REG                 0x18    /* Alternate Feature Status Register */
 615 #define AFS_PU                  0x01    /* Playback Underrun */
 616 #define AFS_PO                  0x02    /* Playback Overrun */
 617 #define AFS_CO                  0x04    /* Capture Overrun */
 618 #define AFS_CU                  0x08    /* Capture Underrun */
 619 #define AFS_PI                  0x10    /* Playback Interrupt */
 620 #define AFS_CI                  0x20    /* Capture Interrupt */
 621 #define AFS_TI                  0x40    /* Timer Interrupt */
 622 #define AFS_RESET_STATUS        0x00    /* Reset the status register */
 623 #define AFS_VALID_MASK          0x7f    /* Valid bits mask */
 624
 625 /* Index 25 - Version and ID, Mode 2 only */
 626 #define VID_REG                 0x19    /* Version and ID Register */
 627 #define VID_CID_MASK            0x07    /* Chip ID Mask */
 628 #define VID_VERSION_MASK        0xe0    /* Version number Mask */
 629 #define VID_A                   0x20    /* Version A */
 630 #define VID_CDE                 0x80    /* Versions C, D or E */
 631 #define VID_VALID_MASK          0xe7    /* Valid bits mask */
 632
 633 /* Index 26 - Mono I/O Control, Mode 2 only */
 634 #define MIOC_REG                0x1a    /* Mono I/O Control Register */
 635 #define MIOC_MI_ATTEN_MASK      0x0f    /* Mono In Attenuation Mask */
 636 #define MIOC_MOM                0x40    /* Mono Out Mute */
 637 #define MIOC_MONO_SPKR_MUTE     0x40    /* Mono (internal) speaker mute */
 638 #define MIOC_MIM                0x80    /* Mono In Mute */
 639 #define MIOC_VALID_MASK         0xcf    /* Valid bits mask */
 640
 641 /* Index 27 is reserved */
 642
 643 /* Index 28 - Capture Data Format, Mode 2 only */
 644 #define CDF_REG                 0x1c    /* Capture Date Foramt Register */
 645 #define CDF_STEREO              0x10    /* Stereo Capture */
 646 #define CDF_MONO                0x00    /* Mono Capture */
 647 #define CDF_LINEAR8             0x00    /* Linear, 8-bit unsigned */
 648 #define CDF_ULAW8               0x20    /* u-Law, 8-bit companded */
 649 #define CDF_LINEAR16LE          0x40    /* Linear, 16-bit signed, little end. */
 650 #define CDF_ALAW8               0x60    /* A-Law, 8-bit companded */
 651 #define CDF_ADPCM4              0xa0    /* ADPCM, 4-bit, IMA compatible */
 652 #define CDF_LINEAR16BE          0xc0    /* Linear, 16-bit signed, big endian */
 653 #define CDF_VALID_MASK          0xf0    /* Valid bits mask */
 654 #ifdef  _BIG_ENDIAN
 655 #define CDF_LINEAR16NE          CDF_LINEAR16BE
 656 #else
 657 #define CDF_LINEAR16NE          CDF_LINEAR16LE
 658 #endif
 659
 660 /* Index 29 is reserved */
 661
 662 /* Index 30 - Capture Upper Base, Mode 2 only */
 663 #define CUB_REG                 0x1e    /* Capture Upper Base Register */
 664 #define CUB_VALID_MASK          0xff    /* Valid bits mask */
 665
 666 /* Index 31 - Capture Lower Base, Mode 2 only */
 667 #define CLB_REG                 0x1f    /* Capture Lower Base Register */
 668 #define CLB_VALID_MASK          0xff    /* Valid bits mask */
 669
 670 #endif  /* _KERNEL */
 671
 672 #ifdef __cplusplus
 673 }
 674 #endif
 675
 676 #endif  /* _AUDIO_4231_H */